From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55C66C3DA61 for ; Mon, 29 Jul 2024 04:37:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9XHsPEuavmY4myAD+KBkbOfQO+0/CK0npjDj22Duulo=; b=w6oXIn5orZg0+RJbp+y+5SmJAc nO/NPQtG8n4rJgFFCumDkyClplFLSxxIWr7xyIo5603uWk2P2TqmVC0h8Nf6Gf/FCLVEBotU97Tko K5A0fNTpjbpwl6QDYwHgEZ9wSg/01qr9LuJvS5yuGCugeUYkPsRGwiNJblu8/uZJLxRjgctFR3uLL 544K2y+MZe8ywLXmOWMzB9LFMKnZJBgWVXOy30f/0ZPLspC6thJn6Rc2HMWrr/Cx70KmNJw7TlgI3 eDjLbrh6+w3TbW7ajJ+U4Wx/x+jFrZ3PqI06JwDS8h1eNoZafuKfyi7TcPtx6D94esDX2hXNn1o6J B3sKFTig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI8H-00000009xzJ-2YXe; Mon, 29 Jul 2024 04:37:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI7U-00000009xqC-37SU for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 04:36:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 588671007; Sun, 28 Jul 2024 21:36:49 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3E6E63F5A1; Sun, 28 Jul 2024 21:36:21 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [PATCH V2 1/3] aarch64: Enable access into SCTLR2_ELx registers from EL2 and below Date: Mon, 29 Jul 2024 10:06:04 +0530 Message-Id: <20240729043606.871451-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729043606.871451-1-anshuman.khandual@arm.com> References: <20240729043606.871451-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_213624_875687_34CEF53B X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_SCTLR2 adds SCTLR2_EL1 and SCTLR2_EL2 system registers. But access into these register from EL2 and below exception levels, will trap into EL3 unless SCR_EL3.SCTLR2En is set. Enable access to SCTLR2_ELx registers when they are implemented. Given that SCTLR2_ELx registers reset to UNKNOWN values - when the highest implemented exception level is not ELx, this resets SCTLR2_ELx registers. Otherwise any kernel which is not aware of these SCTLR2_ELx registers, will be subject to arbitrary behaviour as a result of the SCTLR2_ELx bits which it will not have configured. Signed-off-by: Anshuman Khandual --- arch/aarch64/include/asm/cpu.h | 7 ++++++- arch/aarch64/init.c | 6 ++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 846b89f..85e735b 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -20,6 +20,9 @@ #define TCR2_EL2 s3_4_c2_c0_3 #define TCR2_EL1 s3_0_c2_c0_3 +#define SCTLR2_EL1 s3_0_c1_c0_3 +#define SCTLR2_EL2 s3_4_c1_c0_3 + /* * RES1 bit definitions definitions as of ARM DDI 0487G.b * @@ -56,6 +59,7 @@ #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) +#define SCR_EL3_SCTLR2En BIT(44) #define SCR_EL3_PIEN BIT(45) #define HCR_EL2_RES1 BIT(1) @@ -80,7 +84,8 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) -#define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) +#define ID_AA64MMFR3_EL1_TCRX BITS(3, 0) +#define ID_AA64MMFR3_EL1_SCTLRX BITS(7, 4) #define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) #define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) #define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 37cb45f..fc0d2e3 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -89,6 +89,12 @@ void cpu_init_el3(void) if (!kernel_is_32bit()) scr |= SCR_EL3_RW; + if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) { + scr |= SCR_EL3_SCTLR2En; + msr(SCTLR2_EL2, 0); + msr(SCTLR2_EL1, 0); + } + msr(SCR_EL3, scr); msr(CPTR_EL3, cptr); -- 2.25.1