From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C8FBC3DA61 for ; Tue, 30 Jul 2024 05:47:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=9rcEkTjWZ1rTz6W+zL6ndgPFOtLGnpMeeryjDtQ0+yQ=; b=aL2beTfwQmMg38q9R3/GIKjg2H z4oHKRGENZfsfs5ZqKdefb3FFMCnj1v58YKfYXpilrtcvHpIerJ0qHubR0KuylBxd1xBy3twrWBV0 CKbgq2uAtHzq0lW+ldDLFQQNYe04j6KePyyLiGSzeUam+eC7r7+MTdDvN2aYm8nS4TXWAnnUlXlwz HhbjR+VTdqXLppEq4FfvMfi302ituKoVtt9GBNhAXWsPqgm/vY+Kwc8cpU/l3iSwzhUpG/DeMCzsd kAMCY3TNwG8bISBQnQ/89RvLouBM7ghMS447iI3X5SbQr1H1qGlD6gn7LWWKz8ohnWmVuFPhAgwpR s22YMpDA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYfhk-0000000Dkfq-3uCI; Tue, 30 Jul 2024 05:47:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYfhI-0000000Dkde-1fmJ for linux-arm-kernel@lists.infradead.org; Tue, 30 Jul 2024 05:46:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50125106F; Mon, 29 Jul 2024 22:47:16 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.55.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 153A33F5A1; Mon, 29 Jul 2024 22:46:48 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [boot-wrapper] aarch64: Enable access into FEAT_FGT2 registers from EL2 and below Date: Tue, 30 Jul 2024 11:16:43 +0530 Message-Id: <20240730054643.157295-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240729_224656_498002_AAB46958 X-CRM114-Status: UNSURE ( 8.08 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_FGT2 adds system registers HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, HFGRTR2_EL2 and HFGWTR2_EL2. But access into these system registers from EL2 and below exception levels, will trap into EL3 unless SCR_EL3.FGTEN2 is set. Enable access to FEAT_FGT2 registers when they are implemented. Given that these new FEAT_FGT2 trap registers have fields that reset to UNKNOWN values when resets are taken to EL3, this initialises all registers as cleared. Signed-off-by: Anshuman Khandual --- This picks up from an earlier discussion regarding [PATCH 2/2]. https://lore.kernel.org/all/20240404073726.947215-1-anshuman.khandual@arm.com/ arch/aarch64/include/asm/cpu.h | 7 +++++++ arch/aarch64/init.c | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index a5744e1..878d03d 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -23,6 +23,12 @@ #define SCTLR2_EL1 s3_0_c1_c0_3 #define SCTLR2_EL2 s3_4_c1_c0_3 +#define HDFGRTR2_EL2 s3_4_c3_c1_0 +#define HDFGWTR2_EL2 s3_4_c3_c1_1 +#define HFGRTR2_EL2 s3_4_c3_c1_2 +#define HFGWTR2_EL2 s3_4_c3_c1_3 +#define HFGITR2_EL2 s3_4_c3_c1_7 + /* * RES1 bit definitions definitions as of ARM DDI 0487G.b * @@ -63,6 +69,7 @@ #define SCR_EL3_SCTLR2En BIT(44) #define SCR_EL3_PIEN BIT(45) #define SCR_EL3_D128En BIT(47) +#define SCR_EL3_FGTEN2 BIT(59) #define HCR_EL2_RES1 BIT(1) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index c9fc7f1..b4d64a0 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -68,6 +68,15 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR0_EL1, FGT)) scr |= SCR_EL3_FGTEN; + if (mrs_field(ID_AA64MMFR0_EL1, FGT) >= 2) { + scr |= SCR_EL3_FGTEN2; + msr(HDFGRTR2_EL2, 0); + msr(HDFGWTR2_EL2, 0); + msr(HFGITR2_EL2, 0); + msr(HFGRTR2_EL2, 0); + msr(HFGWTR2_EL2, 0); + } + if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) scr |= SCR_EL3_ECVEN; -- 2.25.1