From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CFBBC3DA7F for ; Thu, 1 Aug 2024 00:31:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WRjUE7hGTazbyslbXiOEpyiloBYmaKei5vJ44psD9Lo=; b=kd5t1heT+znwtOUt8iquMgyqZN n3nP55btYBPvTDZw/aJdatkqy0VaIegILI0/rwBm49qAtd40y24JKBFOkl0iQzabp7EC2IoyZ1dOO WR1ja+Td0e/6RNx3hUzc3XDOZkTythBlSTYty1l9tv8LnHCQSFQ77NQ0NV5dcypwktH8J0zEL5oe5 hn2X0742v95z2vfuoyAqhSMLXY3jaXuMoJqLNSLBYjnGHL8oyWFIA9txtcnKIrFFYb9iM0PHVe/CC TCEQRMY0buoC/q2HKS8Ie/XASEjXx/su9xKGiNL0TcAEILp2pq9Xcltl5//ZSVVMU+kjDpF9edcUL o4A7YDVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZJin-000000031NA-1QDR; Thu, 01 Aug 2024 00:31:09 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZJi0-0000000316l-3iQO for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 00:30:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 39DC5624C0; Thu, 1 Aug 2024 00:30:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23F4CC32786; Thu, 1 Aug 2024 00:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722472220; bh=aQOPGRDuca0jP6BFG+wUCutmfPwa2tzy8A7TzRxZPUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s7ap+HiZuKlSI5svQOoyzBvxheD0AzRJcFg3je9eaDLcemNkkZO1t946gjfHONOkw l9hP29IbUy6sVf4Z50QWqvbZAsmOIBNvzr/hNgE6SyipBfSVW9D7UrQZam2o0MyLdl 7G/K/YJmYdjPn00jAc59gqCbNNfSetx/569zEHa5EkBqvx+fNVdPOSdxBKX85Jzazo cxvgP4VnDQ50kHnv08Cgo1BI7YZAftOOQI2C6jbCamMlZibF5dkGwsIrBW5tUMmgR6 i3ZeIi9YbYjKSeWOLCmF+1s9kvD7ifVBIB95U2R2F5J+Th3TJACBJ7nzGYWhvKuT2z trTZcur4UgLnw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ken Sloat , Michal Simek , Sean Anderson , Sasha Levin , linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.1 33/61] pwm: xilinx: Fix u32 overflow issue in 32-bit width PWM mode. Date: Wed, 31 Jul 2024 20:25:51 -0400 Message-ID: <20240801002803.3935985-33-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240801002803.3935985-1-sashal@kernel.org> References: <20240801002803.3935985-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.102 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_173021_011852_EDEBF057 X-CRM114-Status: GOOD ( 15.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ken Sloat [ Upstream commit 56f45266df67aa0f5b2a6881c8c4d16dbfff6b7d ] This timer HW supports 8, 16 and 32-bit timer widths. This driver currently uses a u32 to store the max possible value of the timer. However, statements perform addition of 2 in xilinx_pwm_apply() when calculating the period_cycles and duty_cycles values. Since priv->max is a u32, this will result in an overflow to 1 which will not only be incorrect but fail on range comparison. This results in making it impossible to set the PWM in this timer mode. There are two obvious solutions to the current problem: 1. Cast each instance where overflow occurs to u64. 2. Change priv->max from a u32 to a u64. Solution #1 requires more code modifications, and leaves opportunity to introduce similar overflows if other math statements are added in the future. These may also go undetected if running in non 32-bit timer modes. Solution #2 is the much smaller and cleaner approach and thus the chosen method in this patch. This was tested on a Zynq UltraScale+ with multiple instances of the PWM IP. Signed-off-by: Ken Sloat Reviewed-by: Michal Simek Reviewed-by: Sean Anderson Link: https://lore.kernel.org/r/SJ0P222MB0107490C5371B848EF04351CA1E19@SJ0P222MB0107.NAMP222.PROD.OUTLOOK.COM Signed-off-by: Michal Simek Signed-off-by: Sasha Levin --- include/clocksource/timer-xilinx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h index c0f56fe6d22ae..d116f18de899c 100644 --- a/include/clocksource/timer-xilinx.h +++ b/include/clocksource/timer-xilinx.h @@ -41,7 +41,7 @@ struct regmap; struct xilinx_timer_priv { struct regmap *map; struct clk *clk; - u32 max; + u64 max; }; /** -- 2.43.0