From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0BC2C3DA64 for ; Thu, 1 Aug 2024 05:45:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=wwy+w4L4cplARb4sEWNuVLJmQhtUSUefKkIQ+GurauI=; b=dn7mvL9+mJEnULs/TqKrAEB3Xy jp1gRaasaoNPBasd4g75S26wU1k19ZFEtBm3HHSvEQDkcwVNd2Rl/HKvJzUEzKm9TO5Yjpo8PBtZV g1JQtwD5Hj1h9+KqqdxtZd0vzMGQFDK0ALFCDX/Jdkr3VyrxKzA7UvW9OvFuwoatlGqkEBOJyyUNV Ej6DeoakG+hohdOblELEfeNXJvYhHRifW4ss9PZGqR0sHNoOe6SSH7ksIgt/Y7bhabrSCZh/zcmu2 YW3hD8+/8bQ+OqIA3tknOJUiHfHRE4spDDT7+ymjo1wh8swZSXGFzgeEJQYYVwm1bmc09aBv08p73 mlGADxZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZOco-00000003nuq-1YXV; Thu, 01 Aug 2024 05:45:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZOcK-00000003noZ-14p3 for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 05:44:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8D311007; Wed, 31 Jul 2024 22:45:09 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BD3053F5A1; Wed, 31 Jul 2024 22:44:41 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Date: Thu, 1 Aug 2024 11:14:35 +0530 Message-Id: <20240801054436.612024-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_224448_404986_52C09399 X-CRM114-Status: UNSURE ( 7.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_SYSREG128 enables 128 bit wide system registers which also need to be defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two new field types i.e Sysreg128 and SysregFields128 for that same purpose. It utilizes recently added macro GENMASK_U128() while also adding some helpers such as define_field_128() and parse_bitdef_128(). This patch applies after the following series which adds GENMASK_U128() https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/ A. Example for SysregFields128 ------------------------------ SysregFields128 TTBRx_D128_EL1 Res0 127:88 Field 87:80 BADDR_HIGH Res0 79:64 Field 63:48 ASID Field 47:5 BADDR_LOW Res0 4:3 Field 2:1 SKL Field 0 CnP EndSysregFields128 ------------------------------ The above input generates the following macros #define TTBRx_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80) #define TTBRx_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80) #define TTBRx_D128_EL1_BADDR_HIGH_SHIFT 80 #define TTBRx_D128_EL1_BADDR_HIGH_WIDTH 8 #define TTBRx_D128_EL1_ASID GENMASK_U128(63, 48) #define TTBRx_D128_EL1_ASID_MASK GENMASK_U128(63, 48) #define TTBRx_D128_EL1_ASID_SHIFT 48 #define TTBRx_D128_EL1_ASID_WIDTH 16 #define TTBRx_D128_EL1_BADDR_LOW GENMASK_U128(47, 5) #define TTBRx_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5) #define TTBRx_D128_EL1_BADDR_LOW_SHIFT 5 #define TTBRx_D128_EL1_BADDR_LOW_WIDTH 43 #define TTBRx_D128_EL1_SKL GENMASK_U128(2, 1) #define TTBRx_D128_EL1_SKL_MASK GENMASK_U128(2, 1) #define TTBRx_D128_EL1_SKL_SHIFT 1 #define TTBRx_D128_EL1_SKL_WIDTH 2 #define TTBRx_D128_EL1_CnP GENMASK_U128(0, 0) #define TTBRx_D128_EL1_CnP_MASK GENMASK_U128(0, 0) #define TTBRx_D128_EL1_CnP_SHIFT 0 #define TTBRx_D128_EL1_CnP_WIDTH 1 #define TTBRx_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3)) #define TTBRx_D128_EL1_RES1 (UL(0)) #define TTBRx_D128_EL1_UNKN (UL(0)) B. Example Sysreg128 ------------------------------ Sysreg128 TTBR1_D128_EL1 3 0 2 0 1 Res0 127:88 Field 87:80 BADDR_HIGH Res0 79:64 Field 63:48 ASID Field 47:5 BADDR_LOW Res0 4:3 Field 2:1 SKL Field 0 CnP EndSysreg128 ------------------------------ The above input generates the following macros #define REG_TTBR1_D128_EL1 S3_0_C2_C0_1 #define SYS_TTBR1_D128_EL1 sys_reg(3, 0, 2, 0, 1) #define SYS_TTBR1_D128_EL1_Op0 3 #define SYS_TTBR1_D128_EL1_Op1 0 #define SYS_TTBR1_D128_EL1_CRn 2 #define SYS_TTBR1_D128_EL1_CRm 0 #define SYS_TTBR1_D128_EL1_Op2 1 #define TTBR1_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80) #define TTBR1_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80) #define TTBR1_D128_EL1_BADDR_HIGH_SHIFT 80 #define TTBR1_D128_EL1_BADDR_HIGH_WIDTH 8 #define TTBR1_D128_EL1_ASID GENMASK_U128(63, 48) #define TTBR1_D128_EL1_ASID_MASK GENMASK_U128(63, 48) #define TTBR1_D128_EL1_ASID_SHIFT 48 #define TTBR1_D128_EL1_ASID_WIDTH 16 #define TTBR1_D128_EL1_BADDR_LOW GENMASK_U128(47, 5) #define TTBR1_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5) #define TTBR1_D128_EL1_BADDR_LOW_SHIFT 5 #define TTBR1_D128_EL1_BADDR_LOW_WIDTH 43 #define TTBR1_D128_EL1_SKL GENMASK_U128(2, 1) #define TTBR1_D128_EL1_SKL_MASK GENMASK_U128(2, 1) #define TTBR1_D128_EL1_SKL_SHIFT 1 #define TTBR1_D128_EL1_SKL_WIDTH 2 #define TTBR1_D128_EL1_CnP GENMASK_U128(0, 0) #define TTBR1_D128_EL1_CnP_MASK GENMASK_U128(0, 0) #define TTBR1_D128_EL1_CnP_SHIFT 0 #define TTBR1_D128_EL1_CnP_WIDTH 1 #define TTBR1_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3)) #define TTBR1_D128_EL1_RES1 (UL(0)) #define TTBR1_D128_EL1_UNKN (UL(0)) Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Anshuman Khandual (1): arm64/tools/sysreg: Add Sysreg128/SysregFields128 arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) -- 2.30.2