From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35A85C3DA4A for ; Thu, 1 Aug 2024 13:50:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UPXhMW/hsZn1jzW/kALbOlfC97WG+asRu+wAj2mgg/Y=; b=iIpGfL4QQltPxEbKqZWdDbxf38 JXmfDIrSfmKwKIGhaOuukCChYRKmBNKd7FoaPJIaA5Lt7HU5A0Plb2XFrgVH7sfTOrofegsmefGkg wk3M1T2ULwCRbP3h3rx20A4UCUhrXGHDDSLV0oxUp7WtmqGGzB2Ds0MC/Vz6xX3GqSRBdmAt1WZse FGHM1t2uHWpCmBEbnAANVCDnAh9CX4nfasL8UmPSaJWFkrVHJp7yZIH0LTDZBDr3yZhGknWjS9sFN VI0J4qvJAfNPI3Nj9PkvdGS7lPQDLtrU7NawS4pdFRJpiVHBV90Lpa3ZorYZ72Z65B+n0htX3Q50w fgpSku7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZWBy-00000005Zk4-2SE4; Thu, 01 Aug 2024 13:50:06 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZWBT-00000005ZeY-24oh for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 13:49:37 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id B7A22CE19DE; Thu, 1 Aug 2024 13:49:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A804C32786; Thu, 1 Aug 2024 13:49:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722520173; bh=CVMwyr/VWlEfAbnRsX2KuyfnVqmOcHOWfWdrH5vHlmY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=MHSn1MMWeHepXaZFMREbFf8s/xN+mJIdRUjd0WWYNim155nc7oX+ZYOK58GHZXV9m dEsYd6on6tjDGG88koFU2gB34G6XCbhCt6MheQQ9Z8RennceyxGtX6Z1o9p+1Tk3WV RjGditim8l9agQ8+0sxpX0CQJBqjFQiSi6HN7r3UIALcEOSoD3tDHLDQYKn7DdneWY TpFGTIDwfyvBtiHoHfMWdcMPK1q4rAs/eCGwl0C3Vz6TRY4zgU4O5LTMkQRtGSLcw6 +UtBY9v9o5CNUKkaRcPChdK+SCKOBlIpVk/is0WVPJwoJy+FtWHm3EsDGE+U8hdRVu aBqlsFtgSlWqA== Date: Thu, 1 Aug 2024 14:49:28 +0100 From: Will Deacon To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, james.morse@arm.com Subject: Re: [PATCH 3/3] arm64: errata: Expand speculative SSBS workaround (again) Message-ID: <20240801134928.GC4794@willie-the-truck> References: <20240801101803.1982459-4-mark.rutland@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240801101803.1982459-4-mark.rutland@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_064936_048280_557C35A2 X-CRM114-Status: GOOD ( 19.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 01, 2024 at 11:18:03AM +0100, Mark Rutland wrote: > A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS > special-purpose register does not affect subsequent speculative > instructions, permitting speculative store bypassing for a window of > time. > > We worked around this for a number of CPUs in commits: > > * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") > * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") > > Since then, similar errata have been published for a number of other Arm > Ltd CPUs, for which the same mitigation is sufficient. This is described > in their respective Software Developer Errata Notice (SDEN) documents: > > * Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 > https://developer.arm.com/documentation/SDEN-885749/3100/ > > * Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 > https://developer.arm.com/documentation/SDEN-1152370/1900/ > > * Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 > https://developer.arm.com/documentation/SDEN-1401784/2100/ > > * Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 > https://developer.arm.com/documentation/SDEN-1707916/1600/ > > * Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 > https://developer.arm.com/documentation/SDEN-2004089/1000/ > > * Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 > https://developer.arm.com/documentation/SDEN-2832921/0500/ > > * Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 > https://developer.arm.com/documentation/SDEN-1401782/2100/ > > * Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 > https://developer.arm.com/documentation/SDEN-1707914/1600/ > > * Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 > https://developer.arm.com/documentation/SDEN-885747/3200/ > > * Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 > https://developer.arm.com/documentation/SDEN-1401781/1900/ > > Note that due to the manner in which Arm develops IP and tracks errata, > some CPUs share a common erratum number and some CPUs have multiple > erratum numbers for the same HW issue. > > On parts without SB, it is necessary to use ISB for the workaround. The > spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" > sequence in this case, which is sufficient on all affected parts. > > Enable the existing mitigation by adding the relevant MIDRs to > erratum_spec_ssbs_list. The list is sorted alphanumerically (involving > moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and > potentially extend again in future. The Kconfig text is also updated to > clarify the set of affected parts and the mitigation. > > Signed-off-by: Mark Rutland > Cc: James Morse > Cc: Will Deacon > Cc: Catalin Marinas > --- > Documentation/arch/arm64/silicon-errata.rst | 18 +++++++++++++++++ > arch/arm64/Kconfig | 22 +++++++++++++++------ > arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- > 3 files changed, 44 insertions(+), 7 deletions(-) Thanks. This looks correct as far as I can tell: Acked-by: Will Deacon Will