From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50C30C3DA4A for ; Fri, 2 Aug 2024 11:27:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pQ/0CqSPKnZEwYvThJFIOJwRL2MoZPdGV3Ntpt2vOb8=; b=Dat9+O0O/rMZ6X9hj6/DLSwA8V EVkj5AyPaY9iq0to4HCdjCn0eFX9NGz2jU+PIduXE4STgnV44M7aNkGrLeHX0tbQjpJ/blSbo7V4P iPQJ3Lxj7vL3UuLuVqafFx89WK1UwIMroAjVZJTqcxMxqJIwrqrj5a/BPEIeWkKCOYH5kp36UFdch c1G9ZHr4VpczSSNUgQV1AUhJ34AYDGMr9y7uLV5K4huGzrD724ec1sUy8+GDO7mTyBcWZczYE/fx5 hnsbL4P3AqrjkkhGwTq+XI2t3o1kaLlQZMHK6otvwVGXLrHIu4U0hjr+6xF71eR3+P65kTS/JkWG7 44lHhGUw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZqRP-00000008gQS-09L5; Fri, 02 Aug 2024 11:27:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZqQu-00000008gNK-205O for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 11:26:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A1ECC1007; Fri, 2 Aug 2024 04:27:14 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 277273F64C; Fri, 2 Aug 2024 04:26:48 -0700 (PDT) Date: Fri, 2 Aug 2024 12:26:39 +0100 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, luca.fancellu@arm.com, maz@kernel.org Subject: Re: [BOOT-WRAPPER 01/11] Always enter AArch32 kernels in ARM mode Message-ID: <20240802122639.30aebecb@donnerap.manchester.arm.com> In-Reply-To: <20240729161501.1806271-2-mark.rutland@arm.com> References: <20240729161501.1806271-1-mark.rutland@arm.com> <20240729161501.1806271-2-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_042652_619318_C4FE812A X-CRM114-Status: GOOD ( 27.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 29 Jul 2024 17:14:51 +0100 Mark Rutland wrote: > Currnetly we try to support entering AArch32 kernels, but this is I think you are missing "in Thumb mode" here? The read is a bit confusing otherwise. > unnecessary, and the code is never exercised. > > Per Linux's Documentation/arch/arm/booting.txt, AArch32 kernels > supported by the AArch64 boot-wrapper should always be entered in ARM > mode: > > | The boot loader is expected to call the kernel image by jumping > | directly to the first instruction of the kernel image. > | > | On CPUs supporting the ARM instruction set, the entry must be > | made in ARM state, even for a Thumb-2 kernel. > | > | On CPUs supporting only the Thumb instruction set such as > | Cortex-M class CPUs, the entry must be made in Thumb state. > > Additionally, the kernel__start symbol that we use as the kernel > entrypoint is always PHYS_OFFSET + KERNEL_OFFSET, which doesn't take > into account any ARM/Thumb distinction in the AArch32 kernel image, and > hence we'll never try to set the Thumb bit in the SPSR. Is that true? I see the first_spin code path for CPU 0 using those values, which indeed never have bit 0 set, but the address could come from *mbox as well, given by the live kernel in the PSCI code path, and we don't have any control over that. Or do I miss anything here? I think the patch is still valid, but we might need to relax the commit message here a bit? Cheers, Andre > > Remove the redundant code. > > Signed-off-by: Mark Rutland > Cc: Akos Denke > Cc: Andre Przywara > Cc: Luca Fancellu > Cc: Marc Zyngier > --- > arch/aarch32/boot.S | 4 ---- > arch/aarch64/boot.S | 7 ------- > 2 files changed, 11 deletions(-) > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > index 4d16c9c..5c2a183 100644 > --- a/arch/aarch32/boot.S > +++ b/arch/aarch32/boot.S > @@ -105,10 +105,6 @@ ASM_FUNC(jump_kernel) > bxeq lr @ no EL3 > > ldr r4, =SPSR_KERNEL > - /* Return in thumb2 mode when bit 0 of address is 1 */ > - tst lr, #1 > - orrne r4, #PSR_T > - > msr spsr_cxf, r4 > movs pc, lr > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index da5fa65..b889137 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -136,13 +136,6 @@ ASM_FUNC(jump_kernel) > br x19 // No EL3 > > 1: mov x4, #SPSR_KERNEL > - > - /* > - * If bit 0 of the kernel address is set, we're entering in AArch32 > - * thumb mode. Set SPSR.T accordingly. > - */ > - bfi x4, x19, #5, #1 > - > msr elr_el3, x19 > msr spsr_el3, x4 > eret