From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 058E9C3DA7F for ; Mon, 5 Aug 2024 14:00:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ep6mTxsOU5n8vCMF7kTWb48lSehR9ce7HYh3+Oj9boY=; b=zwf8+wqS2p5g34rE9/cu3I4rmS Eg+xLYSBZegbsAFLXH2YfRZGEVMEK7zJmrHcUzR4IyIYLJO7pPDIb1T67acuee5wPGHBmAyR9gOFT xDviCir1AgrKyjYM0RqI6V0nHRB1AEZARiKORHVMkZsx0uj8gZu8HR9N+Ii0BUSFHKAZNjJDFBh9Q 0Ye8lAMFtCFf+JaVbP3G026o28qTh1quG13tFYvWM0zqNjRbtily4x0J+j/oPdABrlGcfyYK2jbO2 yxnIJo93MQdpVRJu21xOoKCeRLMChJTbJpP7Zwmb4AVb0bKIFoDtlaFesW5gJrK9dFXBRdpQD75q8 MXLCP6PQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sayGK-0000000G2rt-1HaO; Mon, 05 Aug 2024 14:00:36 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sayFb-0000000G2e3-2ScC for linux-arm-kernel@lists.infradead.org; Mon, 05 Aug 2024 13:59:53 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id B43A8CE0AF6; Mon, 5 Aug 2024 13:59:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5FD6C32782; Mon, 5 Aug 2024 13:59:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722866389; bh=EyTSiPAafa66YyrGSKzx20HNcdBnILGm5FLS3y8oypQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t998Gk2NceJq97cj5UOfzb+BNyyqsd+QrO/qJtIHwHaTHZfGFYz/JwMmwj2B5rU2A Miotl4sWUylpJK0ztkIzPC7o/Q48bl7ddXrBkQ/F7AJ3Jrr3cj9oG/XnXmpPOCdcBi 7HRg7VC6jB0TgldZ2hCMo0Yxyt8CmLVyeW1y1OJnpxSQa8FKAeLwOZpMEoUgmlXS4s ZEheMORGq04OHCqjK1c5Y0Iu4m2SeQJ+rKfFqf4nGHwxFRjfxE0Y+9eCwzitBGpwKQ 4MXZL0C6NLmJn4kxpfadbii3WDDLsMei7h3YitRxXOMp/Iw9/T4BzKVDGQo3qeAP5j iPVhTasgeVZ4w== Date: Mon, 5 Aug 2024 14:59:42 +0100 From: Will Deacon To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [RFC V2 1/3] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Message-ID: <20240805135942.GA9866@willie-the-truck> References: <20240620092607.267132-1-anshuman.khandual@arm.com> <20240620092607.267132-2-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240620092607.267132-2-anshuman.khandual@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240805_065951_847035_EC720A75 X-CRM114-Status: GOOD ( 17.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jun 20, 2024 at 02:56:05PM +0530, Anshuman Khandual wrote: > This adds required field details for ID_AA64DFR1_EL1, and also drops dummy > ftr_raz[] array which is now redundant. These register fields will be used > to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 > later. > > Cc: Catalin Marinas > Cc: Will Deacon > cc: Mark Brown > Cc: Mark Rutland > Cc: Marc Zyngier > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 48e7029f1054..12f0a5181bf2 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -527,6 +527,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABL_CMPs_SHIFT, 8, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DPFZS_SHIFT, 4, 0), I only got this far in the patch, but why is this FTR_STRICT + FTR_LOWER_SAFE? The behaviour of the cycle counter on an SPE management event sounds like it would be fine to differ between cores, no? Please go through all the new fields, bearing in mind that most of the PMU stuff is per-CPU type rather than global. Will