From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: "Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"NXP Linux Team" <linux-imx@nxp.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
linux-pci@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, bpf@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v8 05/11] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
Date: Wed, 7 Aug 2024 08:06:42 +0530 [thread overview]
Message-ID: <20240807023642.GC3412@thinkpad> (raw)
In-Reply-To: <20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com>
On Mon, Jul 29, 2024 at 04:18:12PM -0400, Frank Li wrote:
> Instead of using the switch case statement to enable/disable the reference
> clock handled by this driver itself, let's introduce a new callback
> enable_ref_clk() and define it for platforms that require it. This
> simplifies the code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 111 ++++++++++++++++------------------
> 1 file changed, 51 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 443c7c75f2842..b68a817ccc86b 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -102,6 +102,7 @@ struct imx_pcie_drvdata {
> const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> const struct pci_epc_features *epc_features;
> int (*init_phy)(struct imx_pcie *pcie);
> + int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
> };
>
> struct imx_pcie {
> @@ -583,21 +584,20 @@ static int imx_pcie_attach_pd(struct device *dev)
> return 0;
> }
>
> -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - unsigned int offset;
> - int ret = 0;
> + if (enable)
> + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
>
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6SX:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> - break;
> - case IMX6QP:
> - case IMX6Q:
> + return 0;
> +}
> +
> +static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + if (enable) {
> /* power up core phy and enable ref clock */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
> /*
> * the async reset input need ref clock to sync internally,
> * when the ref clock comes after reset, internal synced
> @@ -605,55 +605,33 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
> * add one ~10us delay here.
> */
> usleep_range(10, 100);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> - break;
> - case IMX7D:
> - case IMX95:
> - case IMX95_EP:
> - break;
> - case IMX8MM:
> - case IMX8MM_EP:
> - case IMX8MQ:
> - case IMX8MQ_EP:
> - case IMX8MP:
> - case IMX8MP_EP:
> - offset = imx_pcie_grp_offset(imx_pcie);
> - /*
> - * Set the over ride low and enabled
> - * make sure that REF_CLK is turned on.
> - */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> - 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> - break;
> + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
> + } else {
> + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
> + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
> }
>
> - return ret;
> + return 0;
> }
>
> -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6QP:
> - case IMX6Q:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD,
> - IMX6Q_GPR1_PCIE_TEST_PD);
> - break;
> - case IMX7D:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> - break;
> - default:
> - break;
> + int offset = imx_pcie_grp_offset(imx_pcie);
> +
> + if (enable) {
> + regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
> + regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> }
> +
> + return 0;
> +}
> +
> +static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + if (!enable)
> + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> + return 0;
> }
>
> static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> @@ -666,10 +644,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> if (ret)
> return ret;
>
> - ret = imx_pcie_enable_ref_clk(imx_pcie);
> - if (ret) {
> - dev_err(dev, "unable to enable pcie ref clock\n");
> - goto err_ref_clk;
> + if (imx_pcie->drvdata->enable_ref_clk) {
> + ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
> + if (ret) {
> + dev_err(dev, "Failed to enable PCIe REFCLK\n");
> + goto err_ref_clk;
> + }
> }
>
> /* allow the clocks to stabilize */
> @@ -684,7 +664,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
>
> static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
> {
> - imx_pcie_disable_ref_clk(imx_pcie);
> + if (imx_pcie->drvdata->enable_ref_clk)
> + imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
> clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> }
>
> @@ -1460,6 +1441,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx_pcie_init_phy,
> + .enable_ref_clk = imx6q_pcie_enable_ref_clk,
> },
> [IMX6SX] = {
> .variant = IMX6SX,
> @@ -1474,6 +1456,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx6sx_pcie_init_phy,
> + .enable_ref_clk = imx6sx_pcie_enable_ref_clk,
> },
> [IMX6QP] = {
> .variant = IMX6QP,
> @@ -1489,6 +1472,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx_pcie_init_phy,
> + .enable_ref_clk = imx6q_pcie_enable_ref_clk,
> },
> [IMX7D] = {
> .variant = IMX7D,
> @@ -1501,6 +1485,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx7d_pcie_init_phy,
> + .enable_ref_clk = imx7d_pcie_enable_ref_clk,
> },
> [IMX8MQ] = {
> .variant = IMX8MQ,
> @@ -1514,6 +1499,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[1] = IOMUXC_GPR12,
> .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> .init_phy = imx8mq_pcie_init_phy,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX8MM] = {
> .variant = IMX8MM,
> @@ -1525,6 +1511,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx8mm_clks),
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX8MP] = {
> .variant = IMX8MP,
> @@ -1536,6 +1523,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx8mm_clks),
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX95] = {
> .variant = IMX95,
> @@ -1562,6 +1550,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> .epc_features = &imx8m_pcie_epc_features,
> .init_phy = imx8mq_pcie_init_phy,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX8MM_EP] = {
> .variant = IMX8MM_EP,
> @@ -1574,6 +1563,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .epc_features = &imx8m_pcie_epc_features,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> @@ -1586,6 +1576,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .epc_features = &imx8m_pcie_epc_features,
> + .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> },
> [IMX95_EP] = {
> .variant = IMX95_EP,
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-08-07 2:37 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-29 20:18 [PATCH v8 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-07-29 20:18 ` [PATCH v8 01/11] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Frank Li
2024-09-02 20:59 ` Bjorn Helgaas
2024-09-02 22:57 ` Frank Li
2024-09-02 21:12 ` Bjorn Helgaas
2024-09-02 22:51 ` Frank Li
2024-09-02 22:59 ` Bjorn Helgaas
2024-07-29 20:18 ` [PATCH v8 02/11] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Frank Li
2024-07-29 20:18 ` [PATCH v8 03/11] PCI: imx6: Fix missing call to phy_power_off() in error handling Frank Li
2024-08-07 2:35 ` Manivannan Sadhasivam
2024-07-29 20:18 ` [PATCH v8 04/11] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-09-03 19:37 ` Bjorn Helgaas
2024-09-03 19:50 ` Frank Li
2024-07-29 20:18 ` [PATCH v8 05/11] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
2024-08-07 2:36 ` Manivannan Sadhasivam [this message]
2024-07-29 20:18 ` [PATCH v8 06/11] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-07-29 20:18 ` [PATCH v8 07/11] PCI: imx6: Improve comment for workaround ERR010728 Frank Li
2024-07-29 20:18 ` [PATCH v8 08/11] PCI: imx6: Consolidate redundant if-checks Frank Li
2024-07-29 20:18 ` [PATCH v8 09/11] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li
2024-07-29 20:18 ` [PATCH v8 10/11] PCI: imx6: Call common PHY API to set mode, speed, and submode Frank Li
2024-07-29 20:18 ` [PATCH v8 11/11] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Frank Li
2024-09-03 1:49 ` Bjorn Helgaas
2024-09-03 20:35 ` Frank Li
2024-09-03 21:09 ` Bjorn Helgaas
2024-09-11 14:07 ` Bjorn Helgaas
2024-09-11 15:19 ` Frank Li
2024-09-11 16:33 ` Bjorn Helgaas
2024-09-11 18:07 ` Frank Li
2024-08-06 20:33 ` [PATCH v8 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-08-07 2:38 ` Manivannan Sadhasivam
2024-08-15 14:56 ` Frank Li
2024-08-22 17:03 ` Frank Li
2024-08-29 21:25 ` Frank Li
2024-09-01 17:55 ` Krzysztof Wilczyński
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240807023642.GC3412@thinkpad \
--to=manivannan.sadhasivam@linaro.org \
--cc=Frank.Li@nxp.com \
--cc=bhelgaas@google.com \
--cc=bpf@vger.kernel.org \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=hongxing.zhu@nxp.com \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=l.stach@pengutronix.de \
--cc=lgirdwood@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).