From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Cyril Brulebois" <kibi@debian.org>,
"Stanimir Varbanov" <svarbanov@suse.de>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
"Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 05/12] PCI: brcmstb: Use swinit reset if available
Date: Wed, 7 Aug 2024 08:33:42 +0530 [thread overview]
Message-ID: <20240807030342.GH3412@thinkpad> (raw)
In-Reply-To: <20240731222831.14895-6-james.quinlan@broadcom.com>
On Wed, Jul 31, 2024 at 06:28:19PM -0400, Jim Quinlan wrote:
> The 7712 SOC adds a software init reset device for the PCIe HW.
> If found in the DT node, use it.
>
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 4d68fe318178..948fd4d176bc 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -266,6 +266,7 @@ struct brcm_pcie {
> struct reset_control *rescal;
> struct reset_control *perst_reset;
> struct reset_control *bridge_reset;
> + struct reset_control *swinit_reset;
> int num_memc;
> u64 memc_size[PCIE_BRCM_MAX_MEMC];
> u32 hw_rev;
> @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> if (IS_ERR(pcie->bridge_reset))
> return PTR_ERR(pcie->bridge_reset);
>
> + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit");
> + if (IS_ERR(pcie->swinit_reset))
> + return PTR_ERR(pcie->swinit_reset);
> +
> ret = clk_prepare_enable(pcie->clk);
> if (ret)
> return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
>
> pcie->bridge_sw_init_set(pcie, 0);
>
> + if (pcie->swinit_reset) {
You already have a callback called 'bridge_sw_init_set', so this 'swinit_reset'
is different from 'bridge_sw_init'? If so, does it make sense to move this into
the callback itself to have all reset sequence in one place?
- Mani
> + ret = reset_control_assert(pcie->swinit_reset);
> + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n"))
> + goto clk_disable_unprepare;
> +
> + /* HW team recommends 1us for proper sync and propagation of reset */
> + udelay(1);
> +
> + ret = reset_control_deassert(pcie->swinit_reset);
> + if (dev_err_probe(&pdev->dev, ret,
> + "could not de-assert reset 'swinit' after asserting\n"))
> + goto clk_disable_unprepare;
> + }
> +
> ret = reset_control_reset(pcie->rescal);
> if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"))
> goto clk_disable_unprepare;
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-08-07 3:04 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-31 22:28 [PATCH v5 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-08-01 16:35 ` Florian Fainelli
2024-08-02 6:43 ` Krzysztof Kozlowski
2024-08-12 22:07 ` Jim Quinlan
2024-08-13 8:27 ` Krzysztof Kozlowski
2024-08-14 17:35 ` Jim Quinlan
2024-08-14 18:05 ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-01 16:36 ` Florian Fainelli
2024-08-02 7:18 ` Krzysztof Kozlowski
2024-07-31 22:28 ` [PATCH v5 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 2:52 ` Manivannan Sadhasivam
2024-08-12 20:12 ` Jim Quinlan
2024-08-07 2:54 ` Manivannan Sadhasivam
2024-08-13 16:45 ` Stanimir Varbanov
2024-08-13 17:06 ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 2:59 ` Manivannan Sadhasivam
2024-08-09 11:16 ` Stanimir Varbanov
2024-08-12 15:13 ` Jim Quinlan
2024-08-12 15:46 ` Jim Quinlan
2024-08-12 22:28 ` Stanimir Varbanov
2024-08-13 15:46 ` James Quinlan
2024-07-31 22:28 ` [PATCH v5 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-01 16:37 ` Florian Fainelli
2024-08-07 3:03 ` Manivannan Sadhasivam [this message]
2024-08-12 17:54 ` Jim Quinlan
2024-08-09 9:53 ` Stanimir Varbanov
2024-08-12 13:43 ` Jim Quinlan
2024-08-12 15:57 ` Manivannan Sadhasivam
2024-08-12 22:05 ` Stanimir Varbanov
2024-07-31 22:28 ` [PATCH v5 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-07 3:05 ` Manivannan Sadhasivam
2024-07-31 22:28 ` [PATCH v5 09/12] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-01 16:39 ` Florian Fainelli
2024-08-06 22:58 ` Stanimir Varbanov
2024-08-07 14:04 ` Manivannan Sadhasivam
2024-08-07 14:16 ` Florian Fainelli
2024-08-07 15:03 ` Manivannan Sadhasivam
2024-08-12 19:14 ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-07 14:11 ` Manivannan Sadhasivam
2024-08-12 18:20 ` Jim Quinlan
2024-07-31 22:28 ` [PATCH v5 11/12] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-01 16:34 ` Florian Fainelli
2024-07-31 22:28 ` [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-08-07 14:12 ` Manivannan Sadhasivam
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