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Wed, 7 Aug 2024 08:20:54 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 Aug 2024 08:20:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 Aug 2024 08:20:54 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 477DKsrE119250; Wed, 7 Aug 2024 08:20:54 -0500 Date: Wed, 7 Aug 2024 08:20:54 -0500 From: Nishanth Menon To: Manorit Chawdhry CC: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye Subject: Re: [PATCH v3 4/9] arm64: dts: ti: Split k3-j784s4-j742s2-main-common.dtsi Message-ID: <20240807132054.jcz5fdokc5yk3mbo@entrust> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> <20240731-b4-upstream-j742s2-v3-4-da7fe3aa9e90@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240731-b4-upstream-j742s2-v3-4-da7fe3aa9e90@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_062104_941075_971FDCD8 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22:40-20240731, Manorit Chawdhry wrote: > k3-j784s4-j742s2-main-common.dtsi will be included in k3-j742s2-main.dtsi at a > later point so move j784s4 related stuff to k3-j784s4-main.dtsi > > Signed-off-by: Manorit Chawdhry > --- > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 13 ------------- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 21 +++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ > 3 files changed, 23 insertions(+), 13 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > index 17abd0f1560a..91352b1f63d2 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > @@ -2405,19 +2405,6 @@ c71_2: dsp@66800000 { > status = "disabled"; > }; > > - c71_3: dsp@67800000 { > - compatible = "ti,j721s2-c71-dsp"; > - reg = <0x00 0x67800000 0x00 0x00080000>, > - <0x00 0x67e00000 0x00 0x0000c000>; > - reg-names = "l2sram", "l1dram"; > - ti,sci = <&sms>; > - ti,sci-dev-id = <40>; > - ti,sci-proc-ids = <0x33 0xff>; > - resets = <&k3_reset 40 1>; > - firmware-name = "j784s4-c71_3-fw"; > - status = "disabled"; > - }; > - This patch can be squashed in. > main_esm: esm@700000 { > compatible = "ti,j721e-esm"; > reg = <0x00 0x700000 0x00 0x1000>; > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > new file mode 100644 > index 000000000000..2ea470d1206d > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -0,0 +1,21 @@ > +// SPDX-License-Identifier: GPL-2.0-only OR MIT > +/* > + * Device Tree Source for J784S4 SoC Family Main Domain peripherals > + * > + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&cbass_main { > + c71_3: dsp@67800000 { > + compatible = "ti,j721s2-c71-dsp"; > + reg = <0x00 0x67800000 0x00 0x00080000>, > + <0x00 0x67e00000 0x00 0x0000c000>; > + reg-names = "l2sram", "l1dram"; > + ti,sci = <&sms>; > + ti,sci-dev-id = <40>; > + ti,sci-proc-ids = <0x33 0xff>; > + resets = <&k3_reset 40 1>; > + firmware-name = "j784s4-c71_3-fw"; > + status = "disabled"; > + }; > +}; I am looking at https://www.ti.com/lit/ug/spruje3/spruje3.pdf (page 26), Device Comparison: CPSW/Serdes, PCIE is also different? Was that missed? > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > index 16ade4fd9cbd..f5afa32157cb 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > @@ -168,3 +168,5 @@ cpu7: cpu@103 { > }; > }; > }; > + > +#include "k3-j784s4-main.dtsi" > > -- > 2.45.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D