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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?KIPR8cSbfXtio+OCOoX212a68JNy+xEoTKa0fi8tkUeQI7SCo3NSeTgX2wS+?= =?us-ascii?Q?WvgqDvQUwXtog/gL0KWNFcuqPhzNSsdBI3DAcJ1OOVGUreIXJ3patdO2yYEk?= =?us-ascii?Q?QYvf+tervWuWLpjLCw+ZsTqjF3H/UUo4WTEJuXV/TRPViU48W/yuuqR3l2OB?= =?us-ascii?Q?lTcJTftUqidF+cASAeEnjBnoKYyoX0+eRhCrTIndTFgsB1G3rvkpmsH0nfU4?= =?us-ascii?Q?mCZ0CvpS47V7HmcDF8xvWhnSNeF6W3q6woz58T5YntHbzZO+pjvb6C56FOjl?= =?us-ascii?Q?0MNhjmeFFu/PnbQ3x+Jr9djadWYzCDKZvE1I6Z0ivxIuyHwrHSIqoPAzpRiu?= =?us-ascii?Q?pTVtg1rmA1jOclbB18dWwqXfgASynLqEfxbuR+2zLzC0wvesQcS569WAVmDD?= =?us-ascii?Q?nC4ngQb1b51WCQsamHxzmI9XIVG76xMCHjDVp2BaOL2gOJ6Qdi8CdErIAedP?= =?us-ascii?Q?bz3aGi7HSiAEuF/HrRJV8UwHwPTTI8lireJAvQ5g9sqnWfQTCTBJvgzSPWLp?= =?us-ascii?Q?AKxLQsTkvfVGUhura6UlZM7Oga4frIjLAKLlYPkrg2K1c+zjD7kbVSj7gIMz?= =?us-ascii?Q?RR0MiPHgPhSzEZEZ0TEndsOtzdZc0svRKn1gYo5pzOF11mqrgpa51O4qXmRG?= =?us-ascii?Q?IpxkAC2r9Qdt636qsTfI0IC1LdK2CJCPsN/8+40e+Lpmj/Z3zmCIvPbQWQxr?= =?us-ascii?Q?cUZYSJSLO7rwfb99S8/rgSeznzcwfEfrB4Bqx85scvu+07lp5N23kuMc45GF?= =?us-ascii?Q?iguxEigDgg7gqfN8XJzCPDgGXmyucC2I0jsbgUxEpSgva6PzBZhY60pq5CBe?= =?us-ascii?Q?WBE8AUpiA/GJ7d9NhclrUedEcKryK5YSGsbXYjaLluUco968NXDDuJuJfVtf?= =?us-ascii?Q?9+ZkSiKKf0IcQB86L8phjSPETXUMS/woDGBxNdTk8A92yJALjo2mtSjRd9ES?= =?us-ascii?Q?gbE0P8YFC3Fdz7soZNv3c4AR4bgxb28XMl+85M0as2a01kEvqPWsTsCNbX9j?= =?us-ascii?Q?6xqm4WSexcG6y1UZJolPcNXUgoujXf44nRiRHW/s+mRUjOoO7sxTIzV3s1H8?= =?us-ascii?Q?LPs6aqPp5vfVKBts0v13vo9+V4tBTgZ5poanWoE43ooX5ewo8jzEGW8WSa7j?= =?us-ascii?Q?y9URLfRU3w2thSTbiiBedvnJ7CJdmLFbEXMXTtEJuVwkeRhNEfnj1uPMmQGS?= =?us-ascii?Q?euhqiqpjMRWyXOmwnaK9tisu7JddAye7KPgJeBh1De8mm1LxaPALxVGApSFe?= =?us-ascii?Q?Ni4hIrxmxvzAoaMhSCzpZouaNppWHUuXifJQKlEIQpy6oMgnywYGXYNQbQNo?= =?us-ascii?Q?b+OIj6NmF1waddvnFW1klr2iHo+Ne7sOqJJz15M+DQ2bZgEMfBEFXvFA6MXG?= =?us-ascii?Q?vazkKEdtN/V0BE4wyl9giCvT5SVK5tufl5yZhUslJeRpjpdjGTS2cPMB3/LH?= =?us-ascii?Q?Q2EU1fFNxZvqMuq4BZhXr4EQ4d+LRKgSb/ajk/TL9PHSFaVxH8Jji49tFSBc?= =?us-ascii?Q?bb08cyk7qsjLuKUI7dAQKswI+jny284UjK3OfqYYk/9r19UnshvXqyIgZ40t?= =?us-ascii?Q?owkZnihxmPqeQPHbQ+o=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4cbad76-5d82-43bc-826b-08dcb877330d X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB7763.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2024 13:28:47.8208 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pDhsPaQRevCLmk82tpwUQH+jgFYIai+ksWXwkrYwTnc3UMNrXZm1+cv2WkLZ+mkJ X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8809 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240809_062900_110026_0B6A8117 X-CRM114-Status: GOOD ( 28.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 09, 2024 at 02:36:14AM +0000, Tian, Kevin wrote: > > From: Jason Gunthorpe > > Sent: Thursday, August 8, 2024 2:19 AM > > > > PCI ATS has a global Smallest Translation Unit field that is located in > > the PF but shared by all of the VFs. > > > > The expectation is that the STU will be set to the root port's global STU > > capability which is driven by the IO page table configuration of the iommu > > HW. Today it becomes set when the iommu driver first enables ATS. > > > > Thus, to enable ATS on the VF, the PF must have already had the correct > > STU programmed, even if ATS is off on the PF. > > > > Unfortunately the PF only programs the STU when the PF enables ATS. The > > iommu drivers tend to leave ATS disabled when IDENTITY translation is > > being used. > > Is there more context on this? How do you mean? > Looking at intel-iommu driver ATS is disabled for IDENETITY when > the iommu is in legacy mode: > > dmar_domain_attach_device() > { > ... > if (sm_supported(info->iommu) || !domain_type_is_si(info->domain)) > iommu_enable_pci_caps(info); > ... > } > > But this follows what VT-d spec says (section 9.3): > > TT: Translate Type > 10b: Untranslated requests are processed as pass-through. The SSPTPTR > field is ignored by hardware. Translated and Translation Requests are > blocked. Yes, HW like this is exactly the problem, it ends up not enabling ATS on the PF and then we don't have the STU programmed so the VF is effectively disabled too. Ideally iommus would continue to work with translated requests when ATS is enabled. Not supporting this configuration creates a nasty problem for devices that are using PASID. The PASID may require ATS to be enabled (ie SVA), but the RID may be IDENTITY for performance. The poor device has no idea it is not allowed to use ATS on the RID side :( > > +/** > > + * pci_prepare_ats - Setup the PS for ATS > > + * @dev: the PCI device > > + * @ps: the IOMMU page shift > > + * > > + * This must be done by the IOMMU driver on the PF before any VFs are > > created to > > + * ensure that the VF can have ATS enabled. > > + * > > + * Returns 0 on success, or negative on failure. > > + */ > > +int pci_prepare_ats(struct pci_dev *dev, int ps) > > +{ > > + u16 ctrl; > > + > > + if (!pci_ats_supported(dev)) > > + return -EINVAL; > > + > > + if (WARN_ON(dev->ats_enabled)) > > + return -EBUSY; > > + > > + if (ps < PCI_ATS_MIN_STU) > > + return -EINVAL; > > + > > + if (dev->is_virtfn) > > + return 0; > > missed a check that 'ps' matches pf's ats_stu. Deliberate, that check is done when enabling ats: > > + > > + dev->ats_stu = ps; > > + ctrl = PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); > > + pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(pci_prepare_ats); > > + > > Then there is no need to keep the 'ps' parameter in pci_enable_ats(). Which is why I left it here. Jason