* [PATCH v3 0/2] Add support for Xilinx XDMA Soft IP as Root Port
@ 2024-08-09 6:09 Thippeswamy Havalige
2024-08-09 6:09 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige
2024-08-09 6:09 ` [PATCH v3 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige
0 siblings, 2 replies; 6+ messages in thread
From: Thippeswamy Havalige @ 2024-08-09 6:09 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzk+dt, conor+dt
Cc: linux-kernel, devicetree, linux-pci, thippeswamy.havalige,
linux-arm-kernel, michal.simek, Thippeswamy Havalige
This series of patch add support for Xilinx QDMA Soft IP as Root Port.
The Xilinx QDMA Soft IP support's 32 bit and 64bit BAR's.
As Root Port it supports MSI and legacy interrupts.
Thippeswamy Havalige (2):
dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root
Port Bridge
PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver
.../devicetree/bindings/pci/xlnx,xdma-host.yaml | 36 ++++++++++++++-
drivers/pci/controller/pcie-xilinx-dma-pl.c | 54 +++++++++++++++++++++-
2 files changed, 87 insertions(+), 3 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-08-09 6:09 [PATCH v3 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige @ 2024-08-09 6:09 ` Thippeswamy Havalige 2024-08-09 14:50 ` Conor Dooley 2024-08-09 18:10 ` Rob Herring 2024-08-09 6:09 ` [PATCH v3 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige 1 sibling, 2 replies; 6+ messages in thread From: Thippeswamy Havalige @ 2024-08-09 6:09 UTC (permalink / raw) To: lpieralisi, kw, robh, bhelgaas, krzk+dt, conor+dt Cc: linux-kernel, devicetree, linux-pci, thippeswamy.havalige, linux-arm-kernel, michal.simek, Thippeswamy Havalige Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) --- changes in v3 - constrain the new entry to only the new compatible. - Remove example. changes in v2 - update dt node label with pcie. --- diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 2f59b3a..f1efd919 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -14,10 +14,21 @@ allOf: properties: compatible: - const: xlnx,xdma-host-3.00 + enum: + - xlnx,xdma-host-3.00 + - xlnx,qdma-host-3.00 reg: - maxItems: 1 + items: + - description: configuration region and XDMA bridge register. + - description: QDMA bridge register. + minItems: 1 + + reg-names: + items: + - const: cfg + - const: breg + minItems: 1 ranges: maxItems: 2 @@ -76,6 +87,27 @@ required: - "#interrupt-cells" - interrupt-controller +if: + properties: + compatible: + contains: + enum: + - xlnx,qdma-host-3.00 +then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + required: + - reg-names +else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + unevaluatedProperties: false examples: -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-08-09 6:09 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige @ 2024-08-09 14:50 ` Conor Dooley 2024-08-09 18:10 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Conor Dooley @ 2024-08-09 14:50 UTC (permalink / raw) To: Thippeswamy Havalige Cc: lpieralisi, kw, robh, bhelgaas, krzk+dt, conor+dt, linux-kernel, devicetree, linux-pci, thippeswamy.havalige, linux-arm-kernel, michal.simek [-- Attachment #1: Type: text/plain, Size: 269 bytes --] On Fri, Aug 09, 2024 at 11:39:54AM +0530, Thippeswamy Havalige wrote: > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port > Bridge. > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-08-09 6:09 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige 2024-08-09 14:50 ` Conor Dooley @ 2024-08-09 18:10 ` Rob Herring 2024-08-11 2:13 ` Havalige, Thippeswamy 1 sibling, 1 reply; 6+ messages in thread From: Rob Herring @ 2024-08-09 18:10 UTC (permalink / raw) To: Thippeswamy Havalige Cc: lpieralisi, kw, bhelgaas, krzk+dt, conor+dt, linux-kernel, devicetree, linux-pci, thippeswamy.havalige, linux-arm-kernel, michal.simek On Fri, Aug 09, 2024 at 11:39:54AM +0530, Thippeswamy Havalige wrote: > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port > Bridge. > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > --- > .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 36 ++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) > --- > changes in v3 > - constrain the new entry to only the new compatible. > - Remove example. > > changes in v2 > - update dt node label with pcie. > --- > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > index 2f59b3a..f1efd919 100644 > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > @@ -14,10 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,xdma-host-3.00 > + enum: > + - xlnx,xdma-host-3.00 > + - xlnx,qdma-host-3.00 Kind of odd that both IP have the exact same version number. Please explain in the commit message where it comes from. If you just copied it from the previous one, then nak. > > reg: > - maxItems: 1 > + items: > + - description: configuration region and XDMA bridge register. > + - description: QDMA bridge register. > + minItems: 1 > + > + reg-names: > + items: > + - const: cfg > + - const: breg > + minItems: 1 > > ranges: > maxItems: 2 > @@ -76,6 +87,27 @@ required: > - "#interrupt-cells" > - interrupt-controller > > +if: > + properties: > + compatible: > + contains: > + enum: > + - xlnx,qdma-host-3.00 > +then: > + properties: > + reg: > + minItems: 2 > + reg-names: > + minItems: 2 > + required: > + - reg-names > +else: > + properties: > + reg: > + maxItems: 1 > + reg-names: > + maxItems: 1 > + > unevaluatedProperties: false > > examples: > -- > 1.8.3.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-08-09 18:10 ` Rob Herring @ 2024-08-11 2:13 ` Havalige, Thippeswamy 0 siblings, 0 replies; 6+ messages in thread From: Havalige, Thippeswamy @ 2024-08-11 2:13 UTC (permalink / raw) To: Rob Herring Cc: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Simek, Michal Hi Rob Herring, > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Friday, August 9, 2024 11:40 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> > Cc: lpieralisi@kernel.org; kw@linux.com; bhelgaas@google.com; > krzk+dt@kernel.org; conor+dt@kernel.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; linux-pci@vger.kernel.org; Havalige, > Thippeswamy <thippeswamy.havalige@amd.com>; linux-arm- > kernel@lists.infradead.org; Simek, Michal <michal.simek@amd.com> > Subject: Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for > Xilinx QDMA PCIe Root Port Bridge > > On Fri, Aug 09, 2024 at 11:39:54AM +0530, Thippeswamy Havalige wrote: > > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port > > Bridge. > > > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > > --- > > .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 36 > ++++++++++++++++++++-- > > 1 file changed, 34 insertions(+), 2 deletions(-) > > --- > > changes in v3 > > - constrain the new entry to only the new compatible. > > - Remove example. > > > > changes in v2 > > - update dt node label with pcie. > > --- > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > index 2f59b3a..f1efd919 100644 > > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > @@ -14,10 +14,21 @@ allOf: > > > > properties: > > compatible: > > - const: xlnx,xdma-host-3.00 > > + enum: > > + - xlnx,xdma-host-3.00 > > + - xlnx,qdma-host-3.00 > > Kind of odd that both IP have the exact same version number. Please > explain in the commit message where it comes from. If you just copied it > from the previous one, then nak. When QDMA IP bought up we were using 3.0 version initially so the compatible String is xlnx,qdma-host-3.00 > > > > > reg: > > - maxItems: 1 > > + items: > > + - description: configuration region and XDMA bridge register. > > + - description: QDMA bridge register. > > + minItems: 1 > > + > > + reg-names: > > + items: > > + - const: cfg > > + - const: breg > > + minItems: 1 > > > > ranges: > > maxItems: 2 > > @@ -76,6 +87,27 @@ required: > > - "#interrupt-cells" > > - interrupt-controller > > > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - xlnx,qdma-host-3.00 > > +then: > > + properties: > > + reg: > > + minItems: 2 > > + reg-names: > > + minItems: 2 > > + required: > > + - reg-names > > +else: > > + properties: > > + reg: > > + maxItems: 1 > > + reg-names: > > + maxItems: 1 > > + > > unevaluatedProperties: false > > > > examples: > > -- > > 1.8.3.1 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver 2024-08-09 6:09 [PATCH v3 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige 2024-08-09 6:09 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige @ 2024-08-09 6:09 ` Thippeswamy Havalige 1 sibling, 0 replies; 6+ messages in thread From: Thippeswamy Havalige @ 2024-08-09 6:09 UTC (permalink / raw) To: lpieralisi, kw, robh, bhelgaas, krzk+dt, conor+dt Cc: linux-kernel, devicetree, linux-pci, thippeswamy.havalige, linux-arm-kernel, michal.simek, Thippeswamy Havalige Add support for Xilinx QDMA Soft IP core as Root Port. The Versal Prime devices support QDMA soft IP module in programmable logic. The integrated QDMA Soft IP block has integrated bridge function that can act as PCIe Root Port. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- drivers/pci/controller/pcie-xilinx-dma-pl.c | 54 ++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) --- changes in v3: - Modify macro value to lower case. - Change return type based QDMA compatible. changes in v2: - Add description for struct pl_dma_pcie --- diff --git a/drivers/pci/controller/pcie-xilinx-dma-pl.c b/drivers/pci/controller/pcie-xilinx-dma-pl.c index 5be5dfd..1ea6a1d 100644 --- a/drivers/pci/controller/pcie-xilinx-dma-pl.c +++ b/drivers/pci/controller/pcie-xilinx-dma-pl.c @@ -13,6 +13,7 @@ #include <linux/msi.h> #include <linux/of_address.h> #include <linux/of_pci.h> +#include <linux/of_platform.h> #include "../pci.h" #include "pcie-xilinx-common.h" @@ -71,10 +72,24 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11) +#define QDMA_BRIDGE_BASE_OFF 0xcd8 /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 64 +enum xilinx_pl_dma_version { + XDMA, + QDMA, +}; + +/** + * struct xilinx_pl_dma_variant - PL DMA PCIe variant information + * @version: DMA version + */ +struct xilinx_pl_dma_variant { + enum xilinx_pl_dma_version version; +}; + struct xilinx_msi { struct irq_domain *msi_domain; unsigned long *bitmap; @@ -88,6 +103,7 @@ struct xilinx_msi { * struct pl_dma_pcie - PCIe port information * @dev: Device pointer * @reg_base: IO Mapped Register Base + * @cfg_base: IO Mapped Configuration Base * @irq: Interrupt number * @cfg: Holds mappings of config space window * @phys_reg_base: Physical address of reg base @@ -97,10 +113,12 @@ struct xilinx_msi { * @msi: MSI information * @intx_irq: INTx error interrupt number * @lock: Lock protecting shared register access + * @variant: PL DMA PCIe version check pointer */ struct pl_dma_pcie { struct device *dev; void __iomem *reg_base; + void __iomem *cfg_base; int irq; struct pci_config_window *cfg; phys_addr_t phys_reg_base; @@ -110,16 +128,23 @@ struct pl_dma_pcie { struct xilinx_msi msi; int intx_irq; raw_spinlock_t lock; + const struct xilinx_pl_dma_variant *variant; }; static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) { + if (port->variant->version == QDMA) + return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); + return readl(port->reg_base + reg); } static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg) { - writel(val, port->reg_base + reg); + if (port->variant->version == QDMA) + writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); + else + writel(val, port->reg_base + reg); } static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port) @@ -173,6 +198,9 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus, if (!xilinx_pl_dma_pcie_valid_device(bus, devfn)) return NULL; + if (port->variant->version == QDMA) + return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } @@ -731,6 +759,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port, port->reg_base = port->cfg->win; + if (port->variant->version == QDMA) { + port->cfg_base = port->cfg->win; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); + port->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(port->reg_base)) + return PTR_ERR(port->reg_base); + port->phys_reg_base = res->start; + } + err = xilinx_request_msi_irq(port); if (err) { pci_ecam_free(port->cfg); @@ -760,6 +797,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) if (!bus) return -ENODEV; + port->variant = of_device_get_match_data(dev); + err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -791,9 +830,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) return err; } +static const struct xilinx_pl_dma_variant xdma_host = { + .version = XDMA, +}; + +static const struct xilinx_pl_dma_variant qdma_host = { + .version = QDMA, +}; + static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = { { .compatible = "xlnx,xdma-host-3.00", + .data = &xdma_host, + }, + { + .compatible = "xlnx,qdma-host-3.00", + .data = &qdma_host, }, {} }; -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-08-11 2:14 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-08-09 6:09 [PATCH v3 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige 2024-08-09 6:09 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige 2024-08-09 14:50 ` Conor Dooley 2024-08-09 18:10 ` Rob Herring 2024-08-11 2:13 ` Havalige, Thippeswamy 2024-08-09 6:09 ` [PATCH v3 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige
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