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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: "Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Robert Moore" <robert.moore@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Drew Fustini" <dfustini@tenstorrent.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Björn Töpel" <bjorn@rivosinc.com>
Subject: [PATCH v8 09/17] ACPI: RISC-V: Implement PCI related functionality
Date: Mon, 12 Aug 2024 06:29:21 +0530	[thread overview]
Message-ID: <20240812005929.113499-10-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240812005929.113499-1-sunilvl@ventanamicro.com>

Replace the dummy implementation for PCI related functions with actual
implementation. This needs ECAM and MCFG CONFIG options to be enabled
for RISC-V.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
---
 arch/riscv/Kconfig       |  2 ++
 arch/riscv/kernel/acpi.c | 33 +++++++++++++++------------------
 drivers/pci/pci-acpi.c   |  2 +-
 3 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0f3cd7c3a436..a269e577284e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -13,6 +13,7 @@ config 32BIT
 config RISCV
 	def_bool y
 	select ACPI_GENERIC_GSI if ACPI
+	select ACPI_MCFG if (ACPI && PCI)
 	select ACPI_PPTT if ACPI
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 	select ACPI_SPCR_TABLE if ACPI
@@ -188,6 +189,7 @@ config RISCV
 	select OF_EARLY_FLATTREE
 	select OF_IRQ
 	select PCI_DOMAINS_GENERIC if PCI
+	select PCI_ECAM if (ACPI && PCI)
 	select PCI_MSI if PCI
 	select RISCV_ALTERNATIVE if !XIP_KERNEL
 	select RISCV_APLIC
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
index ba957aaca5cb..6e0d333f57e5 100644
--- a/arch/riscv/kernel/acpi.c
+++ b/arch/riscv/kernel/acpi.c
@@ -311,29 +311,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 #ifdef CONFIG_PCI
 
 /*
- * These interfaces are defined just to enable building ACPI core.
- * TODO: Update it with actual implementation when external interrupt
- * controller support is added in RISC-V ACPI.
+ * raw_pci_read/write - Platform-specific PCI config space access.
  */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-		 int reg, int len, u32 *val)
+int raw_pci_read(unsigned int domain, unsigned int bus,
+		 unsigned int devfn, int reg, int len, u32 *val)
 {
-	return PCIBIOS_DEVICE_NOT_FOUND;
+	struct pci_bus *b = pci_find_bus(domain, bus);
+
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->read(b, devfn, reg, len, val);
 }
 
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-		  int reg, int len, u32 val)
+int raw_pci_write(unsigned int domain, unsigned int bus,
+		  unsigned int devfn, int reg, int len, u32 val)
 {
-	return PCIBIOS_DEVICE_NOT_FOUND;
+	struct pci_bus *b = pci_find_bus(domain, bus);
+
+	if (!b)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return b->ops->write(b, devfn, reg, len, val);
 }
 
-int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
-{
-	return -1;
-}
-
-struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
-{
-	return NULL;
-}
 #endif	/* CONFIG_PCI */
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 8ed81a373bd7..af370628e583 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1543,7 +1543,7 @@ static int __init acpi_pci_init(void)
 }
 arch_initcall(acpi_pci_init);
 
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 
 /*
  * Try to assign the IRQ number when probing a new device
-- 
2.43.0



  parent reply	other threads:[~2024-08-12  2:15 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-12  0:59 [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-08-12  0:59 ` [PATCH v8 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-08-12 18:09   ` Bjorn Helgaas
2024-08-14  5:32     ` Sunil V L
2024-08-12  0:59 ` [PATCH v8 02/17] ACPI: scan: Add a weak arch_sort_irqchip_probe() to order the IRQCHIP probe Sunil V L
2024-08-12  0:59 ` [PATCH v8 03/17] ACPI: bus: Add acpi_riscv_init() function Sunil V L
2024-08-12  0:59 ` [PATCH v8 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-08-12  0:59 ` [PATCH v8 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-08-12  0:59 ` [PATCH v8 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-08-12  0:59 ` [PATCH v8 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-08-12  0:59 ` [PATCH v8 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-08-22 21:44   ` Bjorn Helgaas
2024-08-23  6:33     ` Sunil V L
2024-08-23 17:45       ` Bjorn Helgaas
2024-08-12  0:59 ` Sunil V L [this message]
2024-08-12  0:59 ` [PATCH v8 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-08-12  0:59 ` [PATCH v8 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-08-12  0:59 ` [PATCH v8 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-08-12  0:59 ` [PATCH v8 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-08-12  0:59 ` [PATCH v8 14/17] irqchip/riscv-imsic-state: Create separate function for DT Sunil V L
2024-08-12  0:59 ` [PATCH v8 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-08-12  0:59 ` [PATCH v8 16/17] irqchip/riscv-aplic: " Sunil V L
2024-08-12  0:59 ` [PATCH v8 17/17] irqchip/sifive-plic: " Sunil V L
2024-08-12  1:07 ` [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-08-26 15:25   ` Thomas Gleixner
2024-08-26 16:15     ` Rafael J. Wysocki
2024-08-26 17:13       ` Sunil V L
2024-08-26 17:27         ` Rafael J. Wysocki
2024-08-26 21:17           ` Thomas Gleixner
2024-08-27 16:20             ` Rafael J. Wysocki
2024-08-27 17:04               ` Sunil V L
2024-08-27 17:12                 ` Rafael J. Wysocki
2024-08-27 17:31                   ` Sunil V L
2024-08-27 17:56                     ` Rafael J. Wysocki
2024-08-27 18:12                       ` Sunil V L

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