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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: "Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Robert Moore" <robert.moore@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Drew Fustini" <dfustini@tenstorrent.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Björn Töpel" <bjorn@rivosinc.com>
Subject: [PATCH v8 14/17] irqchip/riscv-imsic-state: Create separate function for DT
Date: Mon, 12 Aug 2024 06:29:26 +0530	[thread overview]
Message-ID: <20240812005929.113499-15-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240812005929.113499-1-sunilvl@ventanamicro.com>

While populating IMSIC global structure, many fields are initialized
using DT properties. Make the code which uses DT properties as separate
function so that it is easier to add ACPI support later. No
functionality added/changed.

Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
---
 drivers/irqchip/irq-riscv-imsic-state.c | 97 ++++++++++++++-----------
 1 file changed, 55 insertions(+), 42 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
index 5479f872e62b..f9e70832863a 100644
--- a/drivers/irqchip/irq-riscv-imsic-state.c
+++ b/drivers/irqchip/irq-riscv-imsic-state.c
@@ -510,6 +510,60 @@ static int __init imsic_matrix_init(void)
 	return 0;
 }
 
+static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode,
+					   struct imsic_global_config *global,
+					   u32 *nr_parent_irqs)
+{
+	int rc;
+
+	/* Find number of guest index bits in MSI address */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
+				  &global->guest_index_bits);
+	if (rc)
+		global->guest_index_bits = 0;
+
+	/* Find number of HART index bits */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
+				  &global->hart_index_bits);
+	if (rc) {
+		/* Assume default value */
+		global->hart_index_bits = __fls(*nr_parent_irqs);
+		if (BIT(global->hart_index_bits) < *nr_parent_irqs)
+			global->hart_index_bits++;
+	}
+
+	/* Find number of group index bits */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
+				  &global->group_index_bits);
+	if (rc)
+		global->group_index_bits = 0;
+
+	/*
+	 * Find first bit position of group index.
+	 * If not specified assumed the default APLIC-IMSIC configuration.
+	 */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
+				  &global->group_index_shift);
+	if (rc)
+		global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
+
+	/* Find number of interrupt identities */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
+				  &global->nr_ids);
+	if (rc) {
+		pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
+		return rc;
+	}
+
+	/* Find number of guest interrupt identities */
+	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
+				  &global->nr_guest_ids);
+	if (rc)
+		global->nr_guest_ids = global->nr_ids;
+
+	return 0;
+}
+
 static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
 					  u32 index, unsigned long *hartid)
 {
@@ -578,50 +632,9 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
 		return -EINVAL;
 	}
 
-	/* Find number of guest index bits in MSI address */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
-				  &global->guest_index_bits);
+	rc = imsic_populate_global_dt(fwnode, global, nr_parent_irqs);
 	if (rc)
-		global->guest_index_bits = 0;
-
-	/* Find number of HART index bits */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
-				  &global->hart_index_bits);
-	if (rc) {
-		/* Assume default value */
-		global->hart_index_bits = __fls(*nr_parent_irqs);
-		if (BIT(global->hart_index_bits) < *nr_parent_irqs)
-			global->hart_index_bits++;
-	}
-
-	/* Find number of group index bits */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
-				  &global->group_index_bits);
-	if (rc)
-		global->group_index_bits = 0;
-
-	/*
-	 * Find first bit position of group index.
-	 * If not specified assumed the default APLIC-IMSIC configuration.
-	 */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
-				  &global->group_index_shift);
-	if (rc)
-		global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
-
-	/* Find number of interrupt identities */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
-				  &global->nr_ids);
-	if (rc) {
-		pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
 		return rc;
-	}
-
-	/* Find number of guest interrupt identities */
-	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
-				  &global->nr_guest_ids);
-	if (rc)
-		global->nr_guest_ids = global->nr_ids;
 
 	/* Sanity check guest index bits */
 	i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
-- 
2.43.0



  parent reply	other threads:[~2024-08-12  2:15 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-12  0:59 [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-08-12  0:59 ` [PATCH v8 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-08-12 18:09   ` Bjorn Helgaas
2024-08-14  5:32     ` Sunil V L
2024-08-12  0:59 ` [PATCH v8 02/17] ACPI: scan: Add a weak arch_sort_irqchip_probe() to order the IRQCHIP probe Sunil V L
2024-08-12  0:59 ` [PATCH v8 03/17] ACPI: bus: Add acpi_riscv_init() function Sunil V L
2024-08-12  0:59 ` [PATCH v8 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-08-12  0:59 ` [PATCH v8 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-08-12  0:59 ` [PATCH v8 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-08-12  0:59 ` [PATCH v8 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-08-12  0:59 ` [PATCH v8 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-08-22 21:44   ` Bjorn Helgaas
2024-08-23  6:33     ` Sunil V L
2024-08-23 17:45       ` Bjorn Helgaas
2024-08-12  0:59 ` [PATCH v8 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-08-12  0:59 ` [PATCH v8 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-08-12  0:59 ` [PATCH v8 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-08-12  0:59 ` [PATCH v8 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-08-12  0:59 ` [PATCH v8 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-08-12  0:59 ` Sunil V L [this message]
2024-08-12  0:59 ` [PATCH v8 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-08-12  0:59 ` [PATCH v8 16/17] irqchip/riscv-aplic: " Sunil V L
2024-08-12  0:59 ` [PATCH v8 17/17] irqchip/sifive-plic: " Sunil V L
2024-08-12  1:07 ` [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-08-26 15:25   ` Thomas Gleixner
2024-08-26 16:15     ` Rafael J. Wysocki
2024-08-26 17:13       ` Sunil V L
2024-08-26 17:27         ` Rafael J. Wysocki
2024-08-26 21:17           ` Thomas Gleixner
2024-08-27 16:20             ` Rafael J. Wysocki
2024-08-27 17:04               ` Sunil V L
2024-08-27 17:12                 ` Rafael J. Wysocki
2024-08-27 17:31                   ` Sunil V L
2024-08-27 17:56                     ` Rafael J. Wysocki
2024-08-27 18:12                       ` Sunil V L

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