From: Joey Gouly <joey.gouly@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Alexandru Elisei <alexandru.elisei@arm.com>
Subject: Re: [PATCH 03/10] KVM: arm64: Add TCR2_EL2 to the sysreg arrays
Date: Tue, 13 Aug 2024 16:03:48 +0100 [thread overview]
Message-ID: <20240813150348.GA3321997@e124191.cambridge.arm.com> (raw)
In-Reply-To: <20240813144738.2048302-4-maz@kernel.org>
On Tue, Aug 13, 2024 at 03:47:31PM +0100, Marc Zyngier wrote:
> Add the TCR2_EL2 register to the per-vcpu sysreg register
> array, as well as the sysreg descriptor array.
>
> Access to this register is conditionned on ID_AA64MMFR3_EL1.TCRX
> being advertised.
s/conditionned/conditional based/
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/kvm_host.h | 1 +
> arch/arm64/kvm/sys_regs.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index a33f5996ca9f..5a9e0ad35580 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -462,6 +462,7 @@ enum vcpu_sysreg {
> TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
> TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
> TCR_EL2, /* Translation Control Register (EL2) */
> + TCR2_EL2, /* Extended Translation Control Register (EL2) */
> SPSR_EL2, /* EL2 saved program status register */
> ELR_EL2, /* EL2 exception link register */
> AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 95832881fd66..52250db3c122 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -436,6 +436,18 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
> return true;
> }
>
> +static bool access_tcr2_el2(struct kvm_vcpu *vcpu,
> + struct sys_reg_params *p,
> + const struct sys_reg_desc *r)
> +{
> + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) {
> + kvm_inject_undefined(vcpu);
> + return false;
> + }
> +
> + return access_rw(vcpu, p, r);
> +}
> +
> static bool access_actlr(struct kvm_vcpu *vcpu,
> struct sys_reg_params *p,
> const struct sys_reg_desc *r)
> @@ -2783,6 +2795,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
> EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
> EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
> + EL2_REG(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1),
> EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
> EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
>
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
next prev parent reply other threads:[~2024-08-13 15:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-13 14:47 [PATCH 00/10] KVM: arm64: Add EL2 support to FEAT_S1PIE Marc Zyngier
2024-08-13 14:47 ` [PATCH 01/10] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Marc Zyngier
2024-08-13 14:47 ` [PATCH 02/10] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2024-08-13 14:47 ` [PATCH 03/10] KVM: arm64: Add TCR2_EL2 to the sysreg arrays Marc Zyngier
2024-08-13 15:03 ` Joey Gouly [this message]
2024-08-13 14:47 ` [PATCH 04/10] KVM: arm64: Add save/restore for TCR2_EL2 Marc Zyngier
2024-08-13 14:47 ` [PATCH 05/10] arm64: Add encoding for PIRE0_EL2 Marc Zyngier
2024-08-13 15:06 ` Joey Gouly
2024-08-13 14:47 ` [PATCH 06/10] arm64: Remove VNCR definition " Marc Zyngier
2024-08-13 15:10 ` Joey Gouly
2024-08-13 14:47 ` [PATCH 07/10] KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays Marc Zyngier
2024-08-13 14:47 ` [PATCH 08/10] KVM: arm64: Add save/restore for PIR{,E0}_EL2 Marc Zyngier
2024-08-13 14:47 ` [PATCH 09/10] KVM: arm64: Handle PIR{,E0}_EL2 traps Marc Zyngier
2024-08-13 15:24 ` Joey Gouly
2024-08-13 15:45 ` Marc Zyngier
2024-08-13 16:19 ` Joey Gouly
2024-08-13 14:47 ` [PATCH 10/10] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Marc Zyngier
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