From: Will Deacon <will@kernel.org>
To: Peter Collingbourne <pcc@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Yichao Yu <yyc1992@gmail.com>,
Robert O'Callahan <robert@ocallahan.org>,
Keno Fischer <keno@juliacomputing.com>
Subject: Re: [PATCH v2] arm64: Implement prctl(PR_{G,S}ET_TSC)
Date: Fri, 16 Aug 2024 11:20:04 +0100 [thread overview]
Message-ID: <20240816102004.GA23304@willie-the-truck> (raw)
In-Reply-To: <CAMn1gO4SB_HDyyDH5EJXTaKQf=2Evr=bsuLy2wH_JOgXfdApiw@mail.gmail.com>
Hi Peter,
On Mon, Jun 10, 2024 at 01:24:51PM -0700, Peter Collingbourne wrote:
> On Fri, May 17, 2024 at 2:25 PM Peter Collingbourne <pcc@google.com> wrote:
> >
> > On arm64, this prctl controls access to CNTVCT_EL0, CNTVCTSS_EL0 and
> > CNTFRQ_EL0 via CNTKCTL_EL1.EL0VCTEN. Since this bit is also used to
> > implement various erratum workarounds, check whether the CPU needs
> > a workaround whenever we potentially need to change it.
>
> Ping.
Chatting with Marc and Catalin about this, we're a little uneasy about
exposing a prctl() for this. Ptrace does seem like a much better fit.
Can you add a new regset for the counter instead?
Will
next prev parent reply other threads:[~2024-08-16 10:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-17 21:25 [PATCH v2] arm64: Implement prctl(PR_{G,S}ET_TSC) Peter Collingbourne
2024-06-10 20:24 ` Peter Collingbourne
2024-08-16 10:20 ` Will Deacon [this message]
2024-08-16 19:04 ` Peter Collingbourne
2024-08-16 22:07 ` Robert O'Callahan
2024-08-23 12:02 ` Will Deacon
2024-08-23 12:01 ` Will Deacon
2024-08-24 1:54 ` Peter Collingbourne
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