From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3C46C52D7C for ; Mon, 19 Aug 2024 17:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=J6q+/sqffM/zDDrEY9OpNzw056+m4uXIUlHOCfASXhc=; b=eQUMQjwmdW9RwmIFfszBsfrQTJ UIEF28JfiHFMp7eUwbrwisRfHKRl9+2u/xATYOWmFa1pIP8T4yKT9K7jHcD+9kIcEO+rDigd2ZDna Y5wmOFUeXxJSN88LdfRm2MhSZPZDc7d9qq3BgrPBSRD/pmcGbXivGq+b/T01TXYjIFcR8CMjNIGGf wEPUreTS2vNMDSGGDzxmAjnl8pHdHHbk56xT9kerWJlwnGRLBV3sk3FtoHZIEaSlQ2LoVL6UlIxwl ry9SfXLeCiwc4Q2mYwFEALTPVI492Vz/mNqT59drNtso24uMooprkCfOYzzmw6AmetYuLndKd07kd kQ0Rh3rg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sg6Qv-00000002RL8-1I0r; Mon, 19 Aug 2024 17:44:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sg64j-00000002O8s-1I8c for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2024 17:21:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 787BC339; Mon, 19 Aug 2024 10:22:14 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 92C3B3F58B; Mon, 19 Aug 2024 10:21:47 -0700 (PDT) Date: Mon, 19 Aug 2024 18:21:45 +0100 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, luca.fancellu@arm.com, maz@kernel.org Subject: Re: [BOOT-WRAPPER v2 04/10] aarch32: Refactor inital entry Message-ID: <20240819182145.470ad74f@donnerap.manchester.arm.com> In-Reply-To: <20240812101555.3558589-5-mark.rutland@arm.com> References: <20240812101555.3558589-1-mark.rutland@arm.com> <20240812101555.3558589-5-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240819_102149_434888_3B48173B X-CRM114-Status: GOOD ( 21.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 12 Aug 2024 11:15:49 +0100 Mark Rutland wrote: > For historical reasons the early AArch32 code is structured differently > from the early AArch64 code, with some common code (including stack > setup) performed before we identify the mode we were entered in. > > Align the structure of the early AArch32 code with that of the early > AArch64 code. This will make subsequent refactoring easier. Right, the result of this patch looks like it can be further optimised, but this is happening later in the series. As such the changes look alright, they should not change behaviour. Reviewed-by: Andre Przywara Cheers, Andre > > Signed-off-by: Mark Rutland > Acked-by: Marc Zyngier > Cc: Akos Denke > Cc: Andre Przywara > Cc: Luca Fancellu > --- > arch/aarch32/boot.S | 55 ++++++++++++++++++++++++++++----------------- > 1 file changed, 34 insertions(+), 21 deletions(-) > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > index 4d16c9c..cf83e55 100644 > --- a/arch/aarch32/boot.S > +++ b/arch/aarch32/boot.S > @@ -31,7 +31,28 @@ > * PSCI is not supported when entered in this mode. > */ > ASM_FUNC(_start) > - /* Stack initialisation */ > + mrs r0, cpsr > + and r0, #PSR_MODE_MASK > + cmp r0, #PSR_SVC > + beq reset_at_svc > + cmp r0, #PSR_HYP > + beq reset_at_hyp > + > + /* Booting at other modes is not supported */ > + b . > + > +reset_at_svc: > + /* > + * When entered in Secure SVC mode we must switch to monitor mode to > + * configure SCR.NS. Switch to monitor mode ASAP to simplify later > + * code. > + */ > + adr lr, reset_at_mon > + ldr r0, =(PSR_A | PSR_I | PSR_F | PSR_MON) > + msr spsr, r0 > + movs pc, lr > + > +reset_at_mon: > cpuid r0, r1 > bl find_logical_id > cmp r0, #MPIDR_INVALID > @@ -39,36 +60,28 @@ ASM_FUNC(_start) > > bl setup_stack > > - mrs r0, cpsr > - and r0, #PSR_MODE_MASK > - > - cmp r0, #PSR_HYP > - bne _switch_monitor > + bl cpu_init_bootwrapper > > - mov r0, #1 > - ldr r1, =flag_no_el3 > - str r0, [r1] > + bl cpu_init_secure_pl1 > > - bl cpu_init_bootwrapper > + bl gic_secure_init > > b start_bootmethod > > -_switch_monitor: > - adr lr, _monitor > - ldr r0, =(PSR_A | PSR_I | PSR_F | PSR_MON) > - msr spsr, r0 > - movs pc, lr > +reset_at_hyp: > + cpuid r0, r1 > + bl find_logical_id > + cmp r0, #MPIDR_INVALID > + beq err_invalid_id > > -_monitor: > - /* Move the stack to Monitor mode*/ > - mrs sp, sp_svc > + bl setup_stack > > - bl cpu_init_secure_pl1 > + mov r0, #1 > + ldr r1, =flag_no_el3 > + str r0, [r1] > > bl cpu_init_bootwrapper > > - bl gic_secure_init > - > b start_bootmethod > > err_invalid_id: