From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12EE4C52D7C for ; Mon, 19 Aug 2024 17:45:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=97ZDEpRLm6V1a9eQNeIquShaqwROfi2t4EPil2s5yiE=; b=FiN/zuc+kDJMD8LWoKwWPh0Oxk qS1UniSIpFlb6myraBo8nYQMmIkpyZdPDTaCddcvopZA4CusP3RCfEWUuqTkXyus+yK+ZPG3o09B8 BDkBhQZSGLMTy/IhSishE0y/YezHB44gVVqfUiU84u44CYmmoeilCySlFRfVRqweUY/EXJYaUJj97 M/mqr5A+1xxa2qyJ/YePF2ZFVUO1x69zPWtOYs+VF3oKI5vqwN0fdAFAozVPz4sRrbUxXWEJj+lbi ruilkASpxwsWPB1vN2eyPVHRPB4SZUZYQ+XQ4HkDBbOLVLJQGkKXNfTTi77TBbq6V2t/2q2HcM6U2 vKiaOZ7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sg6Qv-00000002RLP-3zeb; Mon, 19 Aug 2024 17:44:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sg64s-00000002OA1-2hvs for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2024 17:21:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8A3D339; Mon, 19 Aug 2024 10:22:23 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EC09B3F58B; Mon, 19 Aug 2024 10:21:56 -0700 (PDT) Date: Mon, 19 Aug 2024 18:21:54 +0100 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, luca.fancellu@arm.com, maz@kernel.org Subject: Re: [BOOT-WRAPPER v2 05/10] aarch32: Implement cpu_init_arch() Message-ID: <20240819182154.0f9789ea@donnerap.manchester.arm.com> In-Reply-To: <20240812101555.3558589-6-mark.rutland@arm.com> References: <20240812101555.3558589-1-mark.rutland@arm.com> <20240812101555.3558589-6-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240819_102158_762591_02F01B59 X-CRM114-Status: GOOD ( 19.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 12 Aug 2024 11:15:50 +0100 Mark Rutland wrote: > When the boot-wrapper is entered at EL2/Hyp it does not initialise > CNTFRQ, and in future it may need to initialize other CPU state > regardless of the exeption level it was entered at. > > Use a common cpu_init_arch() function to initialize CPU state regardless > of the exception level the boot-wrapper was entered at. For clarity > cpu_init_secure_pl1() is renamed to cpu_init_monitor(), which better > matches PSR_MON and will allow for the addition of cppu_init_hyp() and > cpu_init_svc() in future. > > Signed-off-by: Mark Rutland > Acked-by: Marc Zyngier > Cc: Akos Denke > Cc: Andre Przywara > Cc: Luca Fancellu Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/aarch32/boot.S | 4 +++- > arch/aarch32/init.c | 12 +++++++++--- > 2 files changed, 12 insertions(+), 4 deletions(-) > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > index cf83e55..f21f89a 100644 > --- a/arch/aarch32/boot.S > +++ b/arch/aarch32/boot.S > @@ -62,7 +62,7 @@ reset_at_mon: > > bl cpu_init_bootwrapper > > - bl cpu_init_secure_pl1 > + bl cpu_init_arch > > bl gic_secure_init > > @@ -82,6 +82,8 @@ reset_at_hyp: > > bl cpu_init_bootwrapper > > + bl cpu_init_arch > + > b start_bootmethod > > err_invalid_id: > diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c > index e25f0c7..35da37c 100644 > --- a/arch/aarch32/init.c > +++ b/arch/aarch32/init.c > @@ -29,7 +29,7 @@ void announce_arch(void) > print_string("\r\n"); > } > > -void cpu_init_secure_pl1(void) > +static void cpu_init_monitor(void) > { > unsigned long scr = SCR_NS | SCR_HCE; > unsigned long nsacr = NSACR_CP10 | NSACR_CP11; > @@ -37,8 +37,6 @@ void cpu_init_secure_pl1(void) > mcr(SCR, scr); > > mcr(NSACR, nsacr); > - > - mcr(CNTFRQ, COUNTER_FREQ); > } > > #ifdef PSCI > @@ -55,3 +53,11 @@ bool cpu_init_psci_arch(void) > return true; > } > #endif > + > +void cpu_init_arch(void) > +{ > + if (read_cpsr_mode() == PSR_MON) > + cpu_init_monitor(); > + > + mcr(CNTFRQ, COUNTER_FREQ); > +}