From: Conor Dooley <conor@kernel.org>
To: Lorenzo Bianconi <lorenzo@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sean Wang <sean.wang@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
upstream@airoha.com, benjamin.larsson@genexis.eu,
ansuelsmth@gmail.com
Subject: Re: [PATCH v2 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller
Date: Thu, 22 Aug 2024 17:06:44 +0100 [thread overview]
Message-ID: <20240822-taste-deceptive-03d0ad56ae2e@spud> (raw)
In-Reply-To: <20240822-en7581-pinctrl-v2-1-ba1559173a7f@kernel.org>
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On Thu, Aug 22, 2024 at 11:40:52AM +0200, Lorenzo Bianconi wrote:
> Introduce device-tree binding documentation for Airoha EN7581 pinctrl
> controller.
>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> + reg:
> + items:
> + - description: IOMUX base address
> + - description: LED IOMUX base address
> + - description: GPIO flash mode base address
> + - description: GPIO flash mode extended base address
> + - description: IO pin configuration base address
> + - description: PCIE reset open-drain base address
> + - description: GPIO bank0 register base address
> + - description: GPIO bank0 second control register base address
> + - description: GPIO bank1 second control register base address
> + - description: GPIO bank1 register base address
> + pinctrl@1fa20214 {
> + compatible = "airoha,en7581-pinctrl";
> + reg = <0x0 0x1fa20214 0x0 0x30>,
> + <0x0 0x1fa2027c 0x0 0x8>,
> + <0x0 0x1fbf0234 0x0 0x4>,
> + <0x0 0x1fbf0268 0x0 0x4>,
> + <0x0 0x1fa2001c 0x0 0x50>,
> + <0x0 0x1fa2018c 0x0 0x4>,
> + <0x0 0x1fbf0200 0x0 0x18>,
> + <0x0 0x1fbf0220 0x0 0x4>,
> + <0x0 0x1fbf0260 0x0 0x8>,
> + <0x0 0x1fbf0270 0x0 0x28>;
> + reg-names = "iomux", "led-iomux",
> + "gpio-flash-mode", "gpio-flash-mode-ext",
> + "ioconf", "pcie-rst-od",
> + "gpio-bank0", "gpio-ctrl1",
> + "gpio-ctrl2", "gpio-bank1";
before looking at v1:
I would really like to see an explanation for why this is a correct
model of the hardware as part of the commit message. To me this screams
syscon/MFD and instead of describing this as a child of a syscon and
using regmap to access it you're doing whatever this is...
after looking at v1:
AFAICT the PWM driver does not currently exist in mainline, so I am now
doubly of the opinion that this needs to be an MFD and a wee bit annoyed
that you didn't include any rationale in your cover letter or w/e for
not going with an MFD given there was discussion on the topic in v1.
Thanks,
Conor.
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next prev parent reply other threads:[~2024-08-22 16:14 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-22 9:40 [PATCH v2 0/2] Add pinctrl support to EN7581 SoC Lorenzo Bianconi
2024-08-22 9:40 ` [PATCH v2 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller Lorenzo Bianconi
2024-08-22 16:06 ` Conor Dooley [this message]
2024-08-22 19:02 ` Lorenzo Bianconi
2024-08-22 20:50 ` Benjamin Larsson
2024-08-23 16:14 ` Conor Dooley
2024-08-23 15:08 ` Christian Marangi
2024-08-23 21:17 ` Lorenzo Bianconi
2024-08-26 17:07 ` Conor Dooley
2024-08-27 7:38 ` Benjamin Larsson
2024-08-27 8:46 ` Lorenzo Bianconi
2024-08-27 14:35 ` Rob Herring
2024-08-27 18:29 ` Christian Marangi
2024-08-29 6:20 ` Krzysztof Kozlowski
2024-08-30 8:50 ` Christian Marangi
2024-08-30 10:28 ` Krzysztof Kozlowski
2024-08-30 10:55 ` Lorenzo Bianconi
2024-08-30 11:01 ` Conor Dooley
2024-08-30 11:03 ` Krzysztof Kozlowski
2024-08-22 9:40 ` [PATCH v2 2/2] pinctrl: airoha: Add support for EN7581 SoC Lorenzo Bianconi
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