From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71F37C5320E for ; Thu, 22 Aug 2024 22:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=htvVIX0pnx0JEoMwnegb60abnR/7WPR/X1zhLq3rlsY=; b=Mw64oBH+6Oj44YxPyguNY+aN8r ovnWcY5RjmbvHi8EVnzaxqLjCs0zcY2DHl3cJNYs1MOliax/wiwdyT5EpY2sfb0IUPqHG/tk+oQPE o94AvJqcZXhDNYytoM7TWgTyZ5b8vLufII3n6YuzWuSv0itLnIIoKABN0pS4ZlwKVAXC2NIqQK8Jc s2NX30YVCAspnsWiQ6OQ972dWPJHmptgLDbaFowiQOY5XvY0uP0IQ8gVJ4RA/D03GJGeYEggLqUiG la/Fwo26Cco+QCNzfXdj7WyKhBsFfFIEcz+B5Ja09aYwwIgfP0MrOmAJfPt8qxbY6AM6/TD349DPx 24stUWSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1shGSL-0000000EUFa-1UmP; Thu, 22 Aug 2024 22:39:01 +0000 Received: from mgamail.intel.com ([198.175.65.10]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1shGRa-0000000EU7S-2yf3 for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 22:38:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724366294; x=1755902294; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=R5+tyKdhLqm7bUYRqH8VIN30gUI0eUJDNaHQgyQlJwk=; b=EAmMGXCRERkeBarww3UNmIxTF0Hk16kmqOgKFNwq4cmMawSs/BSOnCIe TqVLLiLpRnPk/0v4K1dXhuDFjNNHwYLtF6hYrO0MxpBGN1V3EKM6Lak6p JkAsObavN/Lw2TQ78WwMQ3QoZnvJja1gSKEj1eiTueSIjLsaYLqM6oUrj K2V5xF7HvYGe/UPNLfMu7aHtcdnlaTa6sZA/mWxy7xo/kVO1IGnsBgYFo AuAjMrgneIf6mcm5M7yPqk+UohWEsm36DPPsvIhJ9xCbOIEPYi5cZAuD3 ZloYK8LXgSsupx8bkTd2xpW3UYSLqZePgvy2R7cUj1GE/XlY/sUYv2aCt Q==; X-CSE-ConnectionGUID: 7VwWm5sGRFWFqmoyZsP5IQ== X-CSE-MsgGUID: GchoTsoCREWiMmhCaJWZmQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="40277858" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="40277858" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 15:38:09 -0700 X-CSE-ConnectionGUID: 3UGFgZGARuWZkTU3DA5QOA== X-CSE-MsgGUID: 3CP1Z0QwRmeZPHvmWHc21w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="66430604" Received: from lkp-server01.sh.intel.com (HELO 9a732dc145d3) ([10.239.97.150]) by orviesa003.jf.intel.com with ESMTP; 22 Aug 2024 15:38:05 -0700 Received: from kbuild by 9a732dc145d3 with local (Exim 4.96) (envelope-from ) id 1shGRP-000DFY-2a; Thu, 22 Aug 2024 22:38:03 +0000 Date: Fri, 23 Aug 2024 06:37:32 +0800 From: kernel test robot To: Bibek Kumar Patro , robdclark@gmail.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, jsnitsel@redhat.com, robh@kernel.org, krzysztof.kozlowski@linaro.org, quic_c_gdjako@quicinc.com, dmitry.baryshkov@linaro.org, konrad.dybcio@linaro.org Cc: oe-kbuild-all@lists.linux.dev, iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bibek Kumar Patro Subject: Re: [PATCH v14 6/6] iommu/arm-smmu: add support for PRR bit setup Message-ID: <202408230612.1DU9cuSx-lkp@intel.com> References: <20240816174259.2056829-7-quic_bibekkum@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240816174259.2056829-7-quic_bibekkum@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_153814_824585_0FD59318 X-CRM114-Status: GOOD ( 12.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Bibek, kernel test robot noticed the following build warnings: [auto build test WARNING on joro-iommu/next] [also build test WARNING on linus/master v6.11-rc4 next-20240822] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Bibek-Kumar-Patro/iommu-arm-smmu-re-enable-context-caching-in-smmu-reset-operation/20240817-014609 base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next patch link: https://lore.kernel.org/r/20240816174259.2056829-7-quic_bibekkum%40quicinc.com patch subject: [PATCH v14 6/6] iommu/arm-smmu: add support for PRR bit setup config: arm-randconfig-r071-20240823 (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 14.1.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202408230612.1DU9cuSx-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from include/linux/scatterlist.h:9, from include/linux/iommu.h:10, from include/linux/io-pgtable.h:6, from include/linux/adreno-smmu-priv.h:9, from drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:7: drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c: In function 'qcom_adreno_smmu_set_prr_addr': >> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:266:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 266 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); | ^ arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed' 282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) | ^ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:269:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 269 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); | ^ arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed' 282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) | ^ vim +266 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c 256 257 static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr) 258 { 259 struct arm_smmu_domain *smmu_domain = (void *)cookie; 260 struct arm_smmu_device *smmu = smmu_domain->smmu; 261 const struct device_node *np = smmu->dev->of_node; 262 263 if (of_device_is_compatible(np, "qcom,smmu-500") && 264 of_device_is_compatible(np, "qcom,adreno-smmu")) { 265 writel_relaxed(lower_32_bits(page_addr), > 266 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); 267 268 writel_relaxed(upper_32_bits(page_addr), 269 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); 270 } 271 } 272 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki