From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EC9BC52D7C for ; Fri, 23 Aug 2024 12:03:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5W5a9tBJVxD9ib8IoeBQmitGCrIXws63Y/5j6IDVMgY=; b=TtAMkteasmuRizU4+5R/y/GPvr Ib+bdBy6zDwbGrrM47q7fGXcPHMMxowGGmW45u17+wwnPWMgA2BusXvdl+Nuwiri3EAHPUI+03ddr 3CaVGkeMRziukWELoobO972i5wy3C1kgvZCCQ7wXq4mbBaDlY2PgHZz+s+g7/emgCYdYZgqynh67i qGCWQ0YiJMdlULTX5zkQ52FzGsh7f7BaDXNxBmgthLhcLrsNR5Sz8vS9xwsVxIq7SQJUUyvdNCUGx xBH1s55xHvZZ33zmk8NoxfAcBPPYcCGzVUMSB+EmQRb8Yrr5Zj8ULVqMy7LjY1Bx6ZuVdk8Q83OTv q2tZ/d1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1shT0h-0000000Gd3w-2b6W; Fri, 23 Aug 2024 12:03:19 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1shSz0-0000000GcdX-2fhU for linux-arm-kernel@lists.infradead.org; Fri, 23 Aug 2024 12:01:36 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id DD964612B9; Fri, 23 Aug 2024 12:01:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26884C32786; Fri, 23 Aug 2024 12:01:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724414493; bh=wCDjsiaVM23FswwrpZF+vofY8hLvHBg1Qf65C0i55/w=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kAOUd7o5ZSWsgRiIkefOVPc7igvB9hM0GPOp8lGbIjVF054xNepLxqg6xoEnHnXd3 hAvRhO10+/NLCjPzQzJdSlye42yVywNirXANb9BOl72sbIHTcg/y6YeQUGDb3TYEI/ mlo7yNc9NT1GDZS1ar3AAFqtCPNjMue8RP5j7aM/tmcaP9breK1tEqKirYxa6mrsmI sZ+P4QqTR3Mb+2N84hLnWUCaDoIkZ2LG/sOsAjLz61oL51AXc3Lsdy2XAl/IM2/MXy iFbN/5qFvNWSHIrzw9yJjYb8OnJH1M0I6jhvxdcqf4axBzpm3xtzR2U5x7jLBvqJhn e6T+jLmZCaobQ== Date: Fri, 23 Aug 2024 13:01:28 +0100 From: Will Deacon To: Peter Collingbourne Cc: Catalin Marinas , Marc Zyngier , linux-arm-kernel@lists.infradead.org, Yichao Yu , Robert O'Callahan , Keno Fischer Subject: Re: [PATCH v2] arm64: Implement prctl(PR_{G,S}ET_TSC) Message-ID: <20240823120122.GB32020@willie-the-truck> References: <20240517212553.3597611-1-pcc@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240517212553.3597611-1-pcc@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240823_050134_877578_48B4338D X-CRM114-Status: GOOD ( 21.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 17, 2024 at 02:25:51PM -0700, Peter Collingbourne wrote: > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index 4ae31b7af6c31..1a2ae7830c179 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -43,6 +43,7 @@ > #include > > #include > +#include > #include > #include > #include > @@ -472,27 +473,49 @@ static void entry_task_switch(struct task_struct *next) > } > > /* > - * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. > - * Ensure access is disabled when switching to a 32bit task, ensure > - * access is enabled when switching to a 64bit task. > + * Handle sysreg updates for ARM erratum 1418040 which affects the 32bit view of > + * CNTVCT, various other errata which require trapping all CNTVCT{,_EL0} > + * accesses and prctl(PR_SET_TSC). Ensure access is disabled iff a workaround is > + * required or PR_TSC_SIGSEGV is set. > */ > -static void erratum_1418040_thread_switch(struct task_struct *next) > +static void update_cntkctl_el1(struct task_struct *next) > { > - if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) || > - !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) > - return; > + struct thread_info *ti = task_thread_info(next); > > - if (is_compat_thread(task_thread_info(next))) > + if (test_ti_thread_flag(ti, TIF_TSC_SIGSEGV) || > + has_erratum_handler(read_cntvct_el0) || > + (IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) && > + this_cpu_has_cap(ARM64_WORKAROUND_1418040) && > + is_compat_thread(ti))) > sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0); > else > sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN); > } > > -static void erratum_1418040_new_exec(void) > +static void cntkctl_thread_switch(struct task_struct *prev, > + struct task_struct *next) > +{ > + if ((read_ti_thread_flags(task_thread_info(prev)) & > + (_TIF_32BIT | _TIF_TSC_SIGSEGV)) != > + (read_ti_thread_flags(task_thread_info(next)) & > + (_TIF_32BIT | _TIF_TSC_SIGSEGV))) > + update_cntkctl_el1(next); > +} > + > +static int do_set_tsc_mode(unsigned int val) > { > + if (val == PR_TSC_SIGSEGV) > + set_thread_flag(TIF_TSC_SIGSEGV); > + else if (val == PR_TSC_ENABLE) > + clear_thread_flag(TIF_TSC_SIGSEGV); > + else > + return -EINVAL; Aren't we in trouble if we get preempted at this point? The flag is out-of-sync with the register, so I worry that we could fail to set the controls correctly for the next task. Will