From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CE36C54731 for ; Tue, 27 Aug 2024 16:51:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=H61RTNSwPn6hbjTILH5pfaAhvrgWxkBBLX+Xq9POdmI=; b=No6vgtiaf6zr2djUU2i6WAqAyr UDhIc3h0eASwM0jWMOcDIzQDEQrpSNjJmKQsyeCQxY8J4vpAqra/O26f40XIUTKgArmfhukAXJ5mQ nBV1zrwhPBqigRh54JCqMHkRnwBnbEF+SbJejak4XFaMvLi5CAvZgYeGeosfj2SWGGj8koRahuES+ F3H4ydRGNuKGId/sfbow53u9Zkp8NaTkA28JQTc+8xKJ2U1K95lLEbSx97aYKXFlPi0nAKLZvapRP c7wH/EODt6RXxMMp0c6XMChQ4ctXdzJGbJQjFPlj6HCOkz/bR3wMmgtQFoUOa6X0yUpnp2MRGmmTC LR/Z4sTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sizPT-0000000C910-1gEN; Tue, 27 Aug 2024 16:51:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sizJK-0000000C7bG-1CqM for linux-arm-kernel@lists.infradead.org; Tue, 27 Aug 2024 16:44:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F04C3DA7; Tue, 27 Aug 2024 09:45:15 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A2E143F762; Tue, 27 Aug 2024 09:44:47 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Will Deacon , Mark Rutland , Suzuki K Poulose , Mike Leach , James Clark , John Garry , Namhyung Kim , Ian Rogers , Adrian Hunter , "Liang, Kan" , Jonathan Cameron , Yicong Yang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-perf-users@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 7/9] perf arm-spe: Save per CPU information in metadata Date: Tue, 27 Aug 2024 17:44:15 +0100 Message-Id: <20240827164417.3309560-8-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240827164417.3309560-1-leo.yan@arm.com> References: <20240827164417.3309560-1-leo.yan@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240827_094450_430147_114083EA X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An Arm SPE event can include all CPUs or just a subset of CPUs in a system. Instead of storing the Arm SPE event parameters in a single metadata entry, save the Arm SPE information on a per-CPU basis. This approach aligns with how Arm SPE traces are recorded per CPU, making it easier to match metadata with trace data. Signed-off-by: Leo Yan --- tools/perf/arch/arm64/util/arm-spe.c | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index f8126283dad2..d0cff3ac7c1f 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -73,14 +73,74 @@ arm_spe_info_priv_size(struct auxtrace_record *itr __maybe_unused, return size; } +static int arm_spe_save_cpu_header(struct auxtrace_record *itr, + struct perf_cpu cpu, __u64 data[]) +{ + struct arm_spe_recording *sper = + container_of(itr, struct arm_spe_recording, itr); + struct perf_pmu *pmu = NULL; + struct perf_pmu tmp_pmu; + char cpu_id_str[16]; + char *cpuid = NULL; + u64 val; + int i; + + snprintf(cpu_id_str, sizeof(cpu_id_str), "%d", cpu.cpu); + tmp_pmu.cpus = perf_cpu_map__new(cpu_id_str); + if (!tmp_pmu.cpus) + return -ENOMEM; + + /* Read CPU MIDR */ + cpuid = perf_pmu__getcpuid(&tmp_pmu); + if (!cpuid) + return -ENOMEM; + val = strtol(cpuid, NULL, 16); + perf_cpu_map__put(tmp_pmu.cpus); + + data[ARM_SPE_CPU] = cpu.cpu; + data[ARM_SPE_CPU_MIDR] = val; + + /* Find the associate Arm SPE PMU for the CPU */ + for (i = 0; i < sper->nr_pmu; i++) { + if (perf_cpu_map__has(sper->pmu[i]->cpus, cpu)) { + pmu = sper->pmu[i]; + break; + } + } + + if (!pmu) { + /* No Arm SPE PMU is found */ + data[ARM_SPE_CPU_PMU_TYPE] = ULLONG_MAX; + data[ARM_SPE_CAP_MIN_IVAL] = 0; + data[ARM_SPE_CAP_LDS] = 0; + } else { + data[ARM_SPE_CPU_PMU_TYPE] = pmu->type; + + if (perf_pmu__scan_file(pmu, "caps/min_interval", "%lu", &val) != 1) + val = 0; + data[ARM_SPE_CAP_MIN_IVAL] = val; + + if (perf_pmu__scan_file(pmu, "caps/lds", "%lu", &val) != 1) + val = 0; + data[ARM_SPE_CAP_LDS] = val; + } + + return ARM_SPE_PER_CPU_PRIV_MAX; +} + static int arm_spe_info_fill(struct auxtrace_record *itr, struct perf_session *session, struct perf_record_auxtrace_info *auxtrace_info, size_t priv_size) { + int i, ret; + size_t offset; struct arm_spe_recording *sper = container_of(itr, struct arm_spe_recording, itr); struct perf_pmu *arm_spe_pmu = sper->pmu[0]; + struct perf_cpu_map *cpu_map = arm_spe_find_cpus(session->evlist); + struct perf_cpu cpu; + __u64 *data; if (priv_size != arm_spe_info_priv_size(itr, session->evlist)) return -EINVAL; @@ -90,7 +150,20 @@ static int arm_spe_info_fill(struct auxtrace_record *itr, auxtrace_info->type = PERF_AUXTRACE_ARM_SPE; auxtrace_info->priv[ARM_SPE_PMU_TYPE] = arm_spe_pmu->type; + auxtrace_info->priv[ARM_SPE_HEADER_VERSION] = ARM_SPE_HEADER_CURRENT_VERSION; + auxtrace_info->priv[ARM_SPE_CPU_NUM] = perf_cpu_map__nr(cpu_map); + + offset = ARM_SPE_CPU_NUM + 1; + perf_cpu_map__for_each_cpu(cpu, i, cpu_map) { + assert(offset < priv_size); + data = &auxtrace_info->priv[offset]; + ret = arm_spe_save_cpu_header(itr, cpu, data); + if (ret < 0) + return ret; + offset += ret; + } + perf_cpu_map__put(cpu_map); return 0; } -- 2.34.1