From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55EEAC54FAA for ; Wed, 28 Aug 2024 13:17:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:CC:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Hlxr3I00Om3Pz366GTjoP2TIgKieVNsjhGzKw3SeBuM=; b=pc6KxU9vQcYlNAVNR0H58AMorD Xs0+nVdrn38eftvcgyEJmEECCMytYPkI5+22IS6/7I4OuOy1s1XFO8ijdzI5HlUuyqYEHFfiAffJJ 1V55xeAVwqD/AB51OuqI4XIg1c9+IaFKJqTClgrmR1z4mB6aapgObW4++DquylSk0rYO38/znb596 bPIp/4/iTtTDeHrm5ljdvWzCYoEZEu2Mic02FmhJ99b1z/Ele9CiHnX7modwV62PIEgOo2COk3J2u VR6gSs+6TvYpMLRgkaH0q2yjX5kv5YfKZtEUYo9OjZQeGqNBCynnuPVKsetKpM46bGfNZIXDfaio8 f4bn+9xA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjIXm-0000000FUjQ-1X3S; Wed, 28 Aug 2024 13:17:02 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjIWu-0000000FUYX-2iK7 for linux-arm-kernel@lists.infradead.org; Wed, 28 Aug 2024 13:16:11 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47SDG15g012939; Wed, 28 Aug 2024 08:16:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724850961; bh=Hlxr3I00Om3Pz366GTjoP2TIgKieVNsjhGzKw3SeBuM=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=FEG8DemBzjHLo4dKVJ8U3LZn8eJgh83F6N4v9h6L3EYajos+k0eqCcizxNOtBCu3/ sJPpBPr79asrwPYQpybv5i5fypBs3W8nmEhLqBuXScadB+nHJhHDt1Kl94XaWYLbp4 BcRraFMHmkLuKOLX3w5VTbnxPVAnyhZalTIOvQww= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47SDG1tj128781 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2024 08:16:01 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 28 Aug 2024 08:16:01 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 28 Aug 2024 08:16:01 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47SDG1a2002345; Wed, 28 Aug 2024 08:16:01 -0500 Date: Wed, 28 Aug 2024 08:16:01 -0500 From: Nishanth Menon To: Bryan Brattlof CC: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , Subject: Re: [PATCH v3 1/4] arm64: dts: ti: k3-am62a: add opp frequencies Message-ID: <20240828131601.6sxvnwpcsb36tz4m@eloquent> References: <20240826-opp-v3-0-0934f8309e13@ti.com> <20240826-opp-v3-1-0934f8309e13@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240826-opp-v3-1-0934f8309e13@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240828_061608_973853_59BD9AF2 X-CRM114-Status: GOOD ( 21.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12:22-20240826, Bryan Brattlof wrote: > One power management technique available to the Cortex-A53s is their > ability to dynamically scale their frequency across the device's > Operating Performance Points (OPP) > > The OPPs available for the Cortex-A53s on the AM62Ax can vary based on > the silicon variant used. The SoC variant is encoded into the > WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit > to only OPP entries the variant supports. A table of all these variants > can be found in it's data sheet[0] for the AM62Ax family. > > Add the OPP table into the SoC's fdti file along with the syscon node to > describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect > the SoC variant. > > [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf > > Signed-off-by: Bryan Brattlof > --- > arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++ > arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++++++++++ > 2 files changed, 56 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi > index f5ac101a04dfa..0b1dd5390cd3f 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi > @@ -17,6 +17,11 @@ chipid: chipid@14 { > reg = <0x14 0x4>; > }; > > + opp_efuse_table: syscon@18 { > + compatible = "ti,am62-opp-efuse-table", "syscon"; > + reg = <0x18 0x4>; Does this really work?? https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpufreq/ti-cpufreq.c#n309 efuse_offset is 0x0 -> OK.. BUT, .rev_offset = 0x0014 from a syscon which is one register wide??? Seems like you have been sidetracked by: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpufreq/ti-cpufreq.c#n384 bug to read some omap register offset? This is probably not getting exposed due to the syscon bug that I just fixed: https://lore.kernel.org/r/20240828121008.3066002-1-nm@ti.com I just have to NAK this series while you folks figure out how to do this properly. > + }; > + > cpsw_mac_syscon: ethernet-mac-syscon@200 { > compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; > reg = <0x200 0x8>; > diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi > index f86a23404e6dd..6c99221beb6bd 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi > @@ -48,6 +48,8 @@ cpu0: cpu@0 { > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&L2_0>; > + operating-points-v2 = <&a53_opp_table>; > + clocks = <&k3_clks 135 0>; > }; > > cpu1: cpu@1 { > @@ -62,6 +64,8 @@ cpu1: cpu@1 { > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&L2_0>; > + operating-points-v2 = <&a53_opp_table>; > + clocks = <&k3_clks 136 0>; > }; > > cpu2: cpu@2 { > @@ -76,6 +80,8 @@ cpu2: cpu@2 { > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&L2_0>; > + operating-points-v2 = <&a53_opp_table>; > + clocks = <&k3_clks 137 0>; > }; > > cpu3: cpu@3 { > @@ -90,6 +96,51 @@ cpu3: cpu@3 { > d-cache-line-size = <64>; > d-cache-sets = <128>; > next-level-cache = <&L2_0>; > + operating-points-v2 = <&a53_opp_table>; > + clocks = <&k3_clks 138 0>; > + }; > + }; > + > + a53_opp_table: opp-table { > + compatible = "operating-points-v2-ti-cpu"; > + opp-shared; > + syscon = <&opp_efuse_table>; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-supported-hw = <0x01 0x0007>; > + clock-latency-ns = <6000000>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + opp-supported-hw = <0x01 0x0007>; > + clock-latency-ns = <6000000>; > + }; > + > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-supported-hw = <0x01 0x0007>; > + clock-latency-ns = <6000000>; > + }; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-supported-hw = <0x01 0x0007>; > + clock-latency-ns = <6000000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-supported-hw = <0x01 0x0006>; > + clock-latency-ns = <6000000>; > + }; > + > + opp-1250000000 { > + opp-hz = /bits/ 64 <1250000000>; > + opp-supported-hw = <0x01 0x0004>; > + clock-latency-ns = <6000000>; > + opp-suspend; > }; > }; > > > -- > 2.46.0 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D