From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2638ECA0ED3 for ; Mon, 2 Sep 2024 20:46:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=XbUFZ5Dl5LlXk5jCd3rykzsOmOThc48mEy7pDKhI9Bc=; b=uu3igxXrp0SBX3 z5rbyM1Cikd3U9W9JOdbakwCFPLtLFCdB+h9ZgfM30TR59eKphrrsJQJ0WrWRlDMTtoBhXSfGS888 +ji0TwZVwbWC4gVMPUSBSdZKibpPacvc6tSN8BMngfAoTyRPcJi+8KXC4yUpCL4rGVPZsDJZUK0Vb pYgmG5ms/JqewS2eWceITcVFTlQWjnS95R9Odc/6+c8tHImq4qxP36qqhUIppRVOKeYsfBP16M8Mg vIgJC0t/AKGjt1PG881sVJqA+zSg6KzKJb5bStxy2OOGxUc55cIOypyX4K1gXjIDkYaMt8obOp8Ei 3Rvvfiy8Z46cKn1a1lvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slDwV-0000000FWcR-3rwy; Mon, 02 Sep 2024 20:46:31 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slDvb-0000000FWVf-2mYh; Mon, 02 Sep 2024 20:45:37 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 791DBA400A2; Mon, 2 Sep 2024 20:45:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F298DC4CEC2; Mon, 2 Sep 2024 20:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725309934; bh=Ff/z3qhnWcm7zLGLAOapgZII/W5Vo0cU9a5nmORcnu4=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=X7E6mmhvnLiRwEX8jOwv9uaNA7WFssCE4DwyDFFIqhRALpLTadMvXSgSxOK412WuC IQ8Mdjbfbsh4/3PamCXI5Tugrkp9HLlzt/3k1/0NENDWrmiarECR3Y0IZAMPZc/JYI y2yy0JjUGpMykY3+UBJEQGJdDl94KsWTHi8cAYlkVRWiCchcjgOKh2Y+t9A6S9n8ka B5KlsH3A2uZz3NufegrCENlEZeE3j6LgngOZmu4rbvm09/NcYjUTowRAd5krNGWZ1X KyM8Iu5aOy88ON4GhGIhMFjKp/vkM6h/LeB9JHzP98tp8hrSEdgSsHN8yLQhsTaVej 5lfKgzpA7aPXg== Date: Mon, 2 Sep 2024 15:45:32 -0500 From: Bjorn Helgaas To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v6 10/13] PCI: brcmstb: Refactor for chips with many regular inbound windows Message-ID: <20240902204532.GA227089@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240815225731.40276-11-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_134535_793846_A2C7E940 X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 15, 2024 at 06:57:23PM -0400, Jim Quinlan wrote: > Provide support for new chips with multiple inbound windows while > keeping the legacy support for the older chips. > > In existing chips there are three inbound windows with fixed purposes: the > first was for mapping SoC internal registers, the second was for memory, > and the third was for memory but with the endian swapped. Typically, only > one window was used. > > Complicating the inbound window usage was the fact that the PCIe HW would > do a baroque internal mapping of system memory, and concatenate the regions > of multiple memory controllers. > > Newer chips such as the 7712 and Cable Modem SOCs take a step forward and > drop the internal mapping while providing for multiple inbound windows. > This works in concert with the dma-ranges property, where each provided > range becomes an inbound window. Krzysztof, can you touch this up on your branch to s/SOCs/SoCs/ to match other usage above, and ... > + * The HW registers (and PCIe) use order-1 numbering for BARs. As > + * such, we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. Rewrap this to fit in 80 columns like (most of) the rest of the file instead of 83? I don't think we gain anything by being wider here.