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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20552a5f4b8sm47398815ad.52.2024.09.03.07.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 07:46:15 -0700 (PDT) Date: Tue, 3 Sep 2024 23:46:13 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Jim Quinlan Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Rob Herring , Philipp Zabel , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Message-ID: <20240903144613.GC1403301@rocinante> References: <20240815225731.40276-6-james.quinlan@broadcom.com> <20240902191827.GA224376@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240903_074617_720304_CEA32324 X-CRM114-Status: GOOD ( 14.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, [...] > > > static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) > > > { > > > - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > > - u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; > > > + if (val) > > > + reset_control_assert(pcie->bridge_reset); > > > + else > > > + reset_control_deassert(pcie->bridge_reset); > > > > > > - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > - tmp = (tmp & ~mask) | ((val << shift) & mask); > > > - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > + if (!pcie->bridge_reset) { > > > + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > > + u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; > > > + > > > + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > + tmp = (tmp & ~mask) | ((val << shift) & mask); > > > + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > > > + } > > > > This pattern looks goofy: > > > > reset_control_assert(pcie->bridge_reset); > > if (!pcie->bridge_reset) { > > ... > > > > If we're going to test pcie->bridge_reset at all, it should be first > > so it's obvious what's going on and the reader doesn't have to go > > verify that reset_control_assert() ignores and returns success for a > > NULL pointer: > > > > if (pcie->bridge_reset) { > > if (val) > > reset_control_assert(pcie->bridge_reset); > > else > > reset_control_deassert(pcie->bridge_reset); > > > > return; > > } > > > > u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; > > ... > > > Will do. [...] You will do what? If you don't mind me asking. Krzysztof