From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2D09CD5BDF for ; Thu, 5 Sep 2024 16:38:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=IsKDti/pXvfClCThh3ZAeO0QOdGD2En2tuBBL4ZSH8E=; b=TfL11BjBoZ107P OAd2aAvk7OIx+Amook9tgCsSzTAyce5zVM9U65TZi9oPBnua1cDUHGUhoVviy+8AGSdqZJwGQQA1i JkqxX1I/S19ZHf43r7YAfZhHTV522RSsgsJIbM7Xue+3DCyO5ODD8MVaeQ265Bh5yqzLTLFpUKjXR 9Jzz1kCiwin7DzNxsKca8XlRPug223osaY5BBKP81pM6ctHN26oFxHUHaOzUmgznlq5qBcsnS4Up9 J6zdxnKSmN8zWPwqDihEnlB6hY+Mz47eTAzZZUKFacoioGylwUfmxKd3CBiqAXLsHj6qAQs12fCM6 C8VotzK94WT/Ys+bNrNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smFV2-000000099sa-2Ly1; Thu, 05 Sep 2024 16:38:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1smFU5-000000099mQ-1It4 for linux-arm-kernel@lists.infradead.org; Thu, 05 Sep 2024 16:37:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 22AD95C57E0; Thu, 5 Sep 2024 16:37:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4488C4CEC3; Thu, 5 Sep 2024 16:37:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725554244; bh=E7v7Z0HlMLoNmX+DSerGozz5C0bXNePfRQsND3aKEqk=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=UNI+4NZTyYpjBLGk5ZuvOV4qi1M+tlz0PfnqWy8pTqeIU0VTy1gIiTpaOHpkNovXE 3+1QqpFgnxK3Eay0HqpTkRRoRuZSMfF20tR1LMNQ7ES73dlg8x23plJ1iSnsXov7H7 zVVQi/kzgmXTNgi3QJMiVrYBKXydwXdCtGEy5HFakbNp1RjzBdy+i+w62R7otsiFRD TndtoXjYe2EsL4X2JRLYnYdvcd3CnHH86KOB2Xo0vFjFrSYvDHcmrdfta10Jwlf9Kg lH6VZxc6frknBuBWoCC/C5WF77asi7Kv2F6zfiFg1koyJQyCNgIPR9w0FTZAInhpw2 LiB5ZRbUJ7NcA== Date: Thu, 5 Sep 2024 11:37:21 -0500 From: Bjorn Helgaas To: Jan Kiszka Cc: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas Subject: Re: [PATCH v4 2/7] dt-bindings: PCI: ti,am65: Extend for use with PVU Message-ID: <20240905163721.GA390911@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <28d31a14fe9cc1867f023ebaddd6074459d15e40.1725444016.git.jan.kiszka@siemens.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240905_093725_412073_CBA58BA2 X-CRM114-Status: GOOD ( 13.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 04, 2024 at 12:00:11PM +0200, Jan Kiszka wrote: > From: Jan Kiszka > > The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices > to specific regions of host memory. Add the optional property > "memory-regions" to point to such regions of memory when PVU is used. > > Since the PVU deals with system physical addresses, utilizing the PVU > with PCIe devices also requires setting up the VMAP registers to map the > Requester ID of the PCIe device to the CBA Virtual ID, which in turn is > mapped to the system physical address. Hence, describe the VMAP > registers which are optionally unless the PVU shall used for PCIe. s/optionally/optional/ s/shall used/should be/ ? (Not sure that's the sense you intend)