From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 655CFEB64CF for ; Sat, 7 Sep 2024 18:57:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Y+DqUV6xHhzoWQTUKXQgP+sEpzYCJ1yLrBuPR1ay+6w=; b=fCAggyvRGY0Az8W2WsVI0/QY0X mFF6cWsYWb6lfI9NLB/I2VcuVF2imSqrjFYFKfOgmy1HKgBUdu7nzKJT1apXqslbCQkQkfR+Y/N+K ttjIq4YujmFo5VDrcJjGcaC8qTqOrwGj2rva8JNrmD1mr83jWj43zsEqEovxzDLdQWUrB+8YPUcCm s8khDYGSOwjapLz2Ei3+a54xCqDf884WCjkiw62x6e8Uk/sDfCDK41YyDFA+WDiwt0b9sNVYd62kE kP5c6kAS+T+5P/9Z48jSXCndcOYSiHGLxWanSHppoJi0KMyivux3aFh6BNwNyyVOk3F5CrIGc5ZUp fxgQEDew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sn0d0-0000000FV5k-3cKA; Sat, 07 Sep 2024 18:57:47 +0000 Received: from mgamail.intel.com ([198.175.65.10]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sn0Xq-0000000FUQe-3OG4; Sat, 07 Sep 2024 18:52:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725735147; x=1757271147; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=7kXAAak41bb4OA0mgBW08er5hKbpTDTK5zGHmAxffbE=; b=Xrd0LXqeOPHtrmCc9XAOn6GazyB3zvz+ojR66rMuybr9p0DVfh4I1TBR hroUluPjOabNg2BMsZEhCcB4Fr9fTowyslzOHlQhjPuVLsUQubacob6qc Rc1hOQDZFfDVY6dqKDRYnNAZLN1hV2VHczUoySFglQOIeYnzEciWZFY47 JLamFo5OyqvSST43lNsmQHmFrHNrOsbWqkAiG97auf27/fJKUmWOymdlH lcpcFPmtC28AvbLk2taNpG+muYyTL0daXy+02ZwzjXnDQGVeuWqbbljVI 9MIqIEm+9Pvx2jZmxPxIFgzuVCOwgdSnr+o9DZ8vYCl4LOa/mBu51K7bw g==; X-CSE-ConnectionGUID: mbSBUocdSmqnfwiVAFevAg== X-CSE-MsgGUID: 6zZCRqdNSGa3dUmjF4nVJA== X-IronPort-AV: E=McAfee;i="6700,10204,11188"; a="41951155" X-IronPort-AV: E=Sophos;i="6.10,210,1719903600"; d="scan'208";a="41951155" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2024 11:52:23 -0700 X-CSE-ConnectionGUID: DKht4rykTp25WAWqy2CtFw== X-CSE-MsgGUID: l7NNmD5fRdWILsvA1D185Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,210,1719903600"; d="scan'208";a="66048902" Received: from lkp-server01.sh.intel.com (HELO 9c6b1c7d3b50) ([10.239.97.150]) by orviesa010.jf.intel.com with ESMTP; 07 Sep 2024 11:52:20 -0700 Received: from kbuild by 9c6b1c7d3b50 with local (Exim 4.96) (envelope-from ) id 1sn0Xh-000Crn-2r; Sat, 07 Sep 2024 18:52:17 +0000 Date: Sun, 8 Sep 2024 02:51:38 +0800 From: kernel test robot To: Riyan Dhiman , jim2101024@gmail.com, nsaenz@kernel.org, lorian.fainelli@broadcom.com, bcm-kernel-feedback-list@broadcom.com, bhelgaas@google.com Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Riyan Dhiman Subject: Re: [PATCH next] PCI: brmstb: Fix type mismatch for num_inbound_wins in brcm_pcie_setup() Message-ID: <202409080202.tevgFgI7-lkp@intel.com> References: <20240904161953.46790-2-riyandhiman14@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240904161953.46790-2-riyandhiman14@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240907_115226_984214_8AA22879 X-CRM114-Status: GOOD ( 17.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Riyan, kernel test robot noticed the following build errors: [auto build test ERROR on next-20240904] url: https://github.com/intel-lab-lkp/linux/commits/Riyan-Dhiman/PCI-brmstb-Fix-type-mismatch-for-num_inbound_wins-in-brcm_pcie_setup/20240905-002339 base: next-20240904 patch link: https://lore.kernel.org/r/20240904161953.46790-2-riyandhiman14%40gmail.com patch subject: [PATCH next] PCI: brmstb: Fix type mismatch for num_inbound_wins in brcm_pcie_setup() config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240908/202409080202.tevgFgI7-lkp@intel.com/config) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240908/202409080202.tevgFgI7-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202409080202.tevgFgI7-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/pci/controller/pcie-brcmstb.c:1033:21: error: expected ';' at end of declaration 1033 | u8 num_out_wins = 0 | ^ | ; 1 error generated. Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX Depends on [n]: MAILBOX [=y] && (ARCH_OMAP2PLUS || ARCH_K3) Selected by [y]: - TI_K3_M4_REMOTEPROC [=y] && REMOTEPROC [=y] && (ARCH_K3 || COMPILE_TEST [=y]) vim +1033 drivers/pci/controller/pcie-brcmstb.c 1025 1026 static int brcm_pcie_setup(struct brcm_pcie *pcie) 1027 { 1028 struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; 1029 void __iomem *base = pcie->base; 1030 struct pci_host_bridge *bridge; 1031 struct resource_entry *entry; 1032 u32 tmp, burst, aspm_support; > 1033 u8 num_out_wins = 0 1034 int num_inbound_wins = 0; 1035 int memc, ret; 1036 1037 /* Reset the bridge */ 1038 ret = pcie->bridge_sw_init_set(pcie, 1); 1039 if (ret) 1040 return ret; 1041 1042 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ 1043 if (pcie->soc_base == BCM2711) { 1044 ret = pcie->perst_set(pcie, 1); 1045 if (ret) { 1046 pcie->bridge_sw_init_set(pcie, 0); 1047 return ret; 1048 } 1049 } 1050 1051 usleep_range(100, 200); 1052 1053 /* Take the bridge out of reset */ 1054 ret = pcie->bridge_sw_init_set(pcie, 0); 1055 if (ret) 1056 return ret; 1057 1058 tmp = readl(base + HARD_DEBUG(pcie)); 1059 if (is_bmips(pcie)) 1060 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 1061 else 1062 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 1063 writel(tmp, base + HARD_DEBUG(pcie)); 1064 /* Wait for SerDes to be stable */ 1065 usleep_range(100, 200); 1066 1067 /* 1068 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it 1069 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it 1070 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. 1071 */ 1072 if (is_bmips(pcie)) 1073 burst = 0x1; /* 256 bytes */ 1074 else if (pcie->soc_base == BCM2711) 1075 burst = 0x0; /* 128 bytes */ 1076 else if (pcie->soc_base == BCM7278) 1077 burst = 0x3; /* 512 bytes */ 1078 else 1079 burst = 0x2; /* 512 bytes */ 1080 1081 /* 1082 * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN, 1083 * RCB_MPS_MODE, RCB_64B_MODE 1084 */ 1085 tmp = readl(base + PCIE_MISC_MISC_CTRL); 1086 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); 1087 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); 1088 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); 1089 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK); 1090 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); 1091 writel(tmp, base + PCIE_MISC_MISC_CTRL); 1092 1093 num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins); 1094 if (num_inbound_wins < 0) 1095 return num_inbound_wins; 1096 1097 set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); 1098 1099 if (!brcm_pcie_rc_mode(pcie)) { 1100 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); 1101 return -EINVAL; 1102 } 1103 1104 tmp = readl(base + PCIE_MISC_MISC_CTRL); 1105 for (memc = 0; memc < pcie->num_memc; memc++) { 1106 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; 1107 1108 if (memc == 0) 1109 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); 1110 else if (memc == 1) 1111 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); 1112 else if (memc == 2) 1113 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2)); 1114 } 1115 writel(tmp, base + PCIE_MISC_MISC_CTRL); 1116 1117 /* 1118 * We ideally want the MSI target address to be located in the 32bit 1119 * addressable memory area. Some devices might depend on it. This is 1120 * possible either when the inbound window is located above the lower 1121 * 4GB or when the inbound area is smaller than 4GB (taking into 1122 * account the rounding-up we're forced to perform). 1123 */ 1124 if (inbound_wins[2].pci_offset >= SZ_4G || 1125 (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) 1126 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; 1127 else 1128 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; 1129 1130 1131 /* Don't advertise L0s capability if 'aspm-no-l0s' */ 1132 aspm_support = PCIE_LINK_STATE_L1; 1133 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) 1134 aspm_support |= PCIE_LINK_STATE_L0S; 1135 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 1136 u32p_replace_bits(&tmp, aspm_support, 1137 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); 1138 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 1139 1140 /* 1141 * For config space accesses on the RC, show the right class for 1142 * a PCIe-PCIe bridge (the default setting is to be EP mode). 1143 */ 1144 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); 1145 u32p_replace_bits(&tmp, 0x060400, 1146 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); 1147 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); 1148 1149 bridge = pci_host_bridge_from_priv(pcie); 1150 resource_list_for_each_entry(entry, &bridge->windows) { 1151 struct resource *res = entry->res; 1152 1153 if (resource_type(res) != IORESOURCE_MEM) 1154 continue; 1155 1156 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) { 1157 dev_err(pcie->dev, "too many outbound wins\n"); 1158 return -EINVAL; 1159 } 1160 1161 if (is_bmips(pcie)) { 1162 u64 start = res->start; 1163 unsigned int j, nwins = resource_size(res) / SZ_128M; 1164 1165 /* bmips PCIe outbound windows have a 128MB max size */ 1166 if (nwins > BRCM_NUM_PCIE_OUT_WINS) 1167 nwins = BRCM_NUM_PCIE_OUT_WINS; 1168 for (j = 0; j < nwins; j++, start += SZ_128M) 1169 brcm_pcie_set_outbound_win(pcie, j, start, 1170 start - entry->offset, 1171 SZ_128M); 1172 break; 1173 } 1174 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, 1175 res->start - entry->offset, 1176 resource_size(res)); 1177 num_out_wins++; 1178 } 1179 1180 /* PCIe->SCB endian mode for inbound window */ 1181 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 1182 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, 1183 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); 1184 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 1185 1186 return 0; 1187 } 1188 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki