From: Bjorn Helgaas <helgaas@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Cyril Brulebois" <kibi@debian.org>,
"Stanimir Varbanov" <svarbanov@suse.de>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
"Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available
Date: Tue, 10 Sep 2024 12:59:27 -0500 [thread overview]
Message-ID: <20240910175927.GA590299@bhelgaas> (raw)
In-Reply-To: <CA+-6iNxfmeBhHK57pUGtJEbBCuhEi8TQCVFPxPbAutkpJVwksA@mail.gmail.com>
On Tue, Sep 10, 2024 at 01:30:41PM -0400, Jim Quinlan wrote:
> On Tue, Sep 3, 2024 at 10:26 AM Jim Quinlan <james.quinlan@broadcom.com> wrote:
> > On Mon, Sep 2, 2024 at 3:18 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > On Thu, Aug 15, 2024 at 06:57:18PM -0400, Jim Quinlan wrote:
> > > > The 7712 SOC has a bridge reset which can be described in the device tree.
> > > > Use it if present. Otherwise, continue to use the legacy method to reset
> > > > the bridge.
> > >
> > > > static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
> > > > {
> > > > - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
> > > > - u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
> > > > + if (val)
> > > > + reset_control_assert(pcie->bridge_reset);
> > > > + else
> > > > + reset_control_deassert(pcie->bridge_reset);
> > > >
> > > > - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > > > - tmp = (tmp & ~mask) | ((val << shift) & mask);
> > > > - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > > > + if (!pcie->bridge_reset) {
> > > > + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
> > > > + u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
> > > > +
> > > > + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > > > + tmp = (tmp & ~mask) | ((val << shift) & mask);
> > > > + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > > > + }
> > >
> > > This pattern looks goofy:
> > >
> > > reset_control_assert(pcie->bridge_reset);
> > > if (!pcie->bridge_reset) {
> > > ...
> > >
> > > If we're going to test pcie->bridge_reset at all, it should be first
> > > so it's obvious what's going on and the reader doesn't have to go
> > > verify that reset_control_assert() ignores and returns success for a
> > > NULL pointer:
> > >
> > > if (pcie->bridge_reset) {
> > > if (val)
> > > reset_control_assert(pcie->bridge_reset);
> > > else
> > > reset_control_deassert(pcie->bridge_reset);
> > >
> > > return;
> > > }
> > >
> > > u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
> > > ...
> > >
> > Will do.
>
> Hi Bjorn,
>
> It is not clear to me if you want a new series -- which would be V7 --
> or you are okay with the current series V6. If the latter, someone
> sent in a fixup commit which must be included.
> Please advise.
Krzysztof amended this on the branch. Take a look here and verify
that it makes sense to you:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/tree/drivers/pci/controller/pcie-brcmstb.c?h=controller/brcmstb#n752
If that looks right to you, no need to post a new v7.
I think Krzysztof also integrated an "int num_inbound_wins" fix; is
that the one you mean? If I'm thinking of the right one, you can
check that at:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/tree/drivers/pci/controller/pcie-brcmstb.c?h=controller/brcmstb#n1034
> > > Krzysztof, can you amend this on the branch?
> > >
> > > It will also make the eventual return checking and error message
> > > simpler because we won't have to initialize "ret" first, and we can
> > > "return 0" directly for the legacy case.
> > >
> > > Bjorn
next prev parent reply other threads:[~2024-09-10 18:00 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-15 22:57 [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 01/13] dt-bindings: PCI: Change brcmstb maintainer and cleanup Jim Quinlan
2024-08-16 6:52 ` Krzysztof Kozlowski
2024-08-16 15:49 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 02/13] dt-bindings: PCI: Use maxItems for reset controllers Jim Quinlan
2024-08-16 6:52 ` Krzysztof Kozlowski
2024-08-16 15:49 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 03/13] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 04/13] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-16 7:02 ` Manivannan Sadhasivam
2024-08-16 15:50 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-16 7:07 ` Manivannan Sadhasivam
2024-08-16 15:51 ` Florian Fainelli
2024-08-17 17:41 ` Stanimir Varbanov
2024-08-19 18:09 ` Jim Quinlan
2024-08-19 19:39 ` Stanimir Varbanov
2024-08-19 21:49 ` Jim Quinlan
2024-08-20 23:42 ` Stanimir Varbanov
2024-08-21 14:48 ` Jim Quinlan
2024-08-26 10:42 ` Stanimir Varbanov
2024-08-26 14:17 ` Jim Quinlan
2024-08-27 12:27 ` Stanimir Varbanov
2024-08-27 15:01 ` Jim Quinlan
2024-09-01 18:04 ` Krzysztof Wilczyński
2024-08-19 19:07 ` Florian Fainelli
2024-08-20 23:38 ` Stanimir Varbanov
2024-08-21 14:32 ` Jim Quinlan
2024-09-02 19:18 ` Bjorn Helgaas
2024-09-03 14:26 ` Jim Quinlan
2024-09-03 14:46 ` Krzysztof Wilczyński
2024-09-03 17:17 ` Bjorn Helgaas
2024-09-03 17:27 ` Krzysztof Wilczyński
2024-09-10 17:30 ` Jim Quinlan
2024-09-10 17:59 ` Bjorn Helgaas [this message]
2024-09-10 19:08 ` Krzysztof Wilczyński
2024-09-12 18:21 ` Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 06/13] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-16 7:08 ` Manivannan Sadhasivam
2024-08-16 15:51 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-09-02 19:46 ` Bjorn Helgaas
2024-09-03 17:45 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 08/13] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 09/13] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 10/13] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-16 7:11 ` Manivannan Sadhasivam
2024-08-16 15:57 ` Florian Fainelli
2024-08-17 16:45 ` Stanimir Varbanov
2024-09-02 20:45 ` Bjorn Helgaas
2024-08-15 22:57 ` [PATCH v6 11/13] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-16 7:14 ` Manivannan Sadhasivam
2024-08-15 22:57 ` [PATCH v6 12/13] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-16 7:17 ` Manivannan Sadhasivam
2024-08-16 15:51 ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 13/13] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-08-16 7:18 ` [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Manivannan Sadhasivam
2024-08-19 17:44 ` Jim Quinlan
2024-08-19 17:48 ` Florian Fainelli
2024-09-01 18:01 ` Krzysztof Wilczyński
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