From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 648AAEE49B7 for ; Wed, 11 Sep 2024 14:25:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=jEWu4rQnv3XMMAYMXFMAQQpLZ5latbBgX2lfeSHIV4Q=; b=0KN294PJlUq5tb Ten2KwuhmYWZ7wzodziLVK1jWu9dKT1yQkju2F29XFemw4RamdOGuX2Oi6wqFb4kCENdQEKxu4I8g 7p8m/NnZuvOKmJOnM+n0E+TC6ZY1D2rNP80VxEsDO5cuvqg4DQPFGIEVWP6km7LTK8Mjykhuljo1B CongP//xowjABd5uJifd8H+o+UeOA+9biuE/OhCv3CEKSmXYGd4Kl1s2+jIZwc5XCfvWZOcpzoc3L NnIxGH0Tg+mqHVTO+0xmIzX1QIzcWzvbF47Ct0i4eAxV1dhv3Tk4oojPKrinPhT+oNmSXpJDIJK2E H0t2NGF51djbo6c69lOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1soOHF-00000009tE4-0xnj; Wed, 11 Sep 2024 14:25:01 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1soO0D-00000009puR-3AMF for linux-arm-kernel@lists.infradead.org; Wed, 11 Sep 2024 14:07:27 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 483DB5C04B2; Wed, 11 Sep 2024 14:07:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AF78C4CEC0; Wed, 11 Sep 2024 14:07:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726063644; bh=r0VvpXAuRXJx3vp8kOdxd9EfYvbZyCGak9YTxgXyHb8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Ui2yWa6X7iHBcYX32/ca4LD22AvNygh2Ug4YOmwLYA9yyXx6mvGowmxulmtdIU2HZ W+eIT5oLdMpjIRTHHDNABHENAX4LrY3RvFufefCYRfDH8UKXZ0JmeI3PodOXZ4fu+r QIWBke5DZvVffSmhdVEaUwJmdixtmqDoRNoeWAiPv4ZgtS8AG/GjkL/sgWWoXLWBep foHnfwi4hoHXJOgofT1LDz+ndLl3HX4N/RRQW15jECNO8X/8vPLvxU+tFh+/Ac7MgK 2oJU9c8wORLWW0N7a/mm88UM2faha4DMEe2cuF3WTLsD4OSUlCsaM4rVX3pZijbx3R c/iR8ZWcJNT/A== Date: Wed, 11 Sep 2024 09:07:21 -0500 From: Bjorn Helgaas To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Qianqiang Liu Subject: Re: [PATCH v8 11/11] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Message-ID: <20240911140721.GA630378@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240729-pci2_upstream-v8-11-b68ee5ef2b4d@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240911_070725_885851_8D068D1C X-CRM114-Status: GOOD ( 17.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [+cc Qianqiang] On Mon, Jul 29, 2024 at 04:18:18PM -0400, Frank Li wrote: > From: Richard Zhu > > Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While > the controller resembles that of iMX8MP, the PHY differs significantly. > Notably, there's a distinction between PCI bus addresses and CPU addresses. > > Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver > need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus > address conversion according to "ranges" property. > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > +{ > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > + struct dw_pcie_rp *pp = &pcie->pp; > + struct resource_entry *entry; > + unsigned int offset; > + > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > + return cpu_addr; > + > + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > + offset = entry->offset; > + return (cpu_addr - offset); > +} I'm sure that with enough effort, we could prove "entry" cannot be NULL here, but I'm not sure I want to spend the effort, and we're going to end up with more patches like this: https://lore.kernel.org/r/20240911125055.58555-1-qianqiang.liu@163.com I propose this minor change: entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); if (!entry) return cpu_addr; return cpu_addr - entry->offset; I still think we should get rid of the .cpu_addr_fixup() callback if possible. But that's a discussion for another day. Bjorn