From: Frank Li <Frank.Li@nxp.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Abraham I" <kishon@kernel.org>,
"Saravana Kannan" <saravanak@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Jesper Nilsson" <jesper.nilsson@axis.com>,
"Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Frank Li" <Frank.Li@nxp.com>
Subject: [PATCH 5/9] PCI: dwc: ep: Replace phys_base and addr_size with range
Date: Thu, 19 Sep 2024 18:03:05 -0400 [thread overview]
Message-ID: <20240919-pcie_ep_range-v1-5-b3e9d62780b7@nxp.com> (raw)
In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com>
The CPU address and PCI address are the same in most system. But in some
systems such as i.MX8QXP, they are different. Previously, we used the
cpu_addr_fixup() hook function to handle address translation. However, the
device tree can use the common 'ranges' property to indicate how CPU and
PCI addresses are translated.
Replace the fields 'phys_base' and 'addr_size' in struct dw_pcie_ep with
struct of_pci_range 'range'. The of_pci_range already includes cpu_addr
and size information. Prepare to add 'ranges' support.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index f8e7283dacd47..f93d3c7a980c8 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -104,7 +104,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
case DW_PCIE_RC_TYPE:
return cpu_addr - pp->cfg0_base;
case DW_PCIE_EP_TYPE:
- return cpu_addr - ep->phys_base;
+ return cpu_addr - ep->range.cpu_addr;
default:
dev_err(pci->dev, "UNKNOWN device type\n");
}
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 43ba5c6738df1..feac1a435f764 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -872,8 +872,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (!res)
return -EINVAL;
- ep->phys_base = res->start;
- ep->addr_size = resource_size(res);
+ ep->range.cpu_addr = ep->range.pci_addr = res->start;
+ ep->range.size = resource_size(res);
if (ep->ops->pre_init)
ep->ops->pre_init(ep);
@@ -891,7 +891,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
- ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
+ ret = pci_epc_mem_init(epc, ep->range.cpu_addr, ep->range.size,
ep->page_size);
if (ret < 0) {
dev_err(dev, "Failed to initialize address space\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 347ab74ac35aa..59109a32b2afc 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -19,6 +19,7 @@
#include <linux/gpio/consumer.h>
#include <linux/irq.h>
#include <linux/msi.h>
+#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/reset.h>
@@ -409,8 +410,7 @@ struct dw_pcie_ep {
struct pci_epc *epc;
struct list_head func_list;
const struct dw_pcie_ep_ops *ops;
- phys_addr_t phys_base;
- size_t addr_size;
+ struct of_pci_range range;
size_t page_size;
u8 bar_to_atu[PCI_STD_NUM_BARS];
phys_addr_t *outbound_addr;
--
2.34.1
next prev parent reply other threads:[~2024-09-19 22:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 22:03 [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Frank Li
2024-09-19 22:03 ` [PATCH 1/9] dt-bindings: PCI: pci-ep: Document 'ranges' property Frank Li
2024-09-19 22:03 ` [PATCH 2/9] of: address: Add argument 'name' for of_node_is_pcie() Frank Li
2024-09-19 22:03 ` [PATCH 3/9] of: address: Add device type pci-ep Frank Li
2024-09-19 22:03 ` [PATCH 4/9] dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present Frank Li
2024-09-19 22:03 ` Frank Li [this message]
2024-09-19 22:03 ` [PATCH 6/9] PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing Frank Li
2024-09-19 22:03 ` [PATCH 7/9] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
2024-09-19 22:03 ` [PATCH 8/9] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() Frank Li
2024-09-19 22:03 ` [PATCH 9/9] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
2024-09-21 14:43 ` [PATCH 0/9] PCI-EP: Add 'ranges' support for PCI endpoint devices Rob Herring
2024-09-21 19:18 ` Frank Li
2024-09-23 16:14 ` Frank Li
2024-09-23 19:02 ` Frank Li
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