[PATCH 0/5] Enable Mali GPU on MediaTek Genio 700 EVK

[PATCH 0/5] Enable Mali GPU on MediaTek Genio 700 EVK

[Pablo Sun]

This series is based on linux-next, tag: next-20240920

Update efuse and clock settings for mt8188, and enable the GPU
on mt8390-genio-700-evk.dts. The panfrost driver probed with dmesg:

panfrost 13000000.gpu: clock rate = 390000000
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7,
	 issues: 00000003,80000400
panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000
         Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x10005 l2_present=0x1
[drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0

Pablo Sun (5):
  arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power
    domain
  clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of
    mfg_core_tmp
  nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning
  arm64: dts: mediatek: mt8188: Add efuse for GPU speed binning
  arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

 arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 11 +++++++--
 .../dts/mediatek/mt8390-genio-700-evk.dts     | 24 +++++++++++++++++++
 drivers/clk/mediatek/clk-mt8188-topckgen.c    |  7 ++++--
 drivers/nvmem/mtk-efuse.c                     |  5 ++++
 4 files changed, 43 insertions(+), 4 deletions(-)

-- 
2.45.2

[PATCH 1/5] arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain

[Pablo Sun]

The clock index "CLK_APMIXED_MFGPLL" belongs to the "apmixedsys" provider,
so fix the index.

In addition, add a "mfg1" label so following commits could set
domain-supply for MFG1 power domain.

Fixes: b8369604050b ("UPSTREAM: arm64: dts: mediatek: mt8188: Add support for SoC power domains")
Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index cd27966d2e3c..02a5bb4dbd1f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -956,9 +956,9 @@ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
 					#size-cells = <0>;
 					#power-domain-cells = <1>;
 
-					power-domain@MT8188_POWER_DOMAIN_MFG1 {
+					mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
 						reg = <MT8188_POWER_DOMAIN_MFG1>;
-						clocks = <&topckgen CLK_APMIXED_MFGPLL>,
+						clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
 							 <&topckgen CLK_TOP_MFG_CORE_TMP>;
 						clock-names = "mfg", "alt";
 						mediatek,infracfg = <&infracfg_ao>;
-- 
2.45.2

[PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp

[Pablo Sun]

Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated
mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when
setting mfgpll clock rate.

If we keep the univpll parents from mfg_core_tmp, when setting
GPU frequency to 390000000, the common clock framework would switch
the parent to univpll, instead of setting mfgpll to 390000000:

    mfgpll                            0        0        0   949999756
    univpll                           2        2        0  2340000000
       univpll_d6                     1        1        0   390000000
          top_mfg_core_tmp            1        1        0   390000000
             mfg_ck_fast_ref          1        1        0   390000000
                mfgcfg_bg3d           1        1        0   390000000

This results in failures when subsequent devfreq operations need to
switch to other frequencies. So remove univpll from the parent list.

This solution is taken from commit 72d38ed720e9 ("clk: mediatek:
clk-mt8195-topckgen: Drop univplls from mfg mux parents")

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8188-topckgen.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
index 2ccc8a1c98f9..74ee692ac613 100644
--- a/drivers/clk/mediatek/clk-mt8188-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
@@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = {
 	"univpll_d3"
 };
 
+/*
+ * MFG can be also parented to "univpll_d6" and "univpll_d7":
+ * these have been removed from the parents list to let us
+ * achieve GPU DVFS without any special clock handlers.
+ */
 static const char * const mfg_core_tmp_parents[] = {
 	"clk26m",
 	"mainpll_d5_d2",
-	"univpll_d6",
-	"univpll_d7"
 };
 
 static const char * const camtg_parents[] = {
-- 
2.45.2

[PATCH 3/5] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning

[Pablo Sun]

Similar to mt8186, the efuse data for mt8188's GPU speed binning
requires post-process to convert the bit field format expected
by the OPP table.

Since mt8188 efuse is not compatible to mt8186, add a new compatible
entry for mt8188 and enable postprocess.

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
 drivers/nvmem/mtk-efuse.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
index 9caf04667341..4984145025bb 100644
--- a/drivers/nvmem/mtk-efuse.c
+++ b/drivers/nvmem/mtk-efuse.c
@@ -105,6 +105,10 @@ static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
 	.uses_post_processing = true,
 };
 
+static const struct mtk_efuse_pdata mtk_mt8188_efuse_pdata = {
+	.uses_post_processing = true,
+};
+
 static const struct mtk_efuse_pdata mtk_efuse_pdata = {
 	.uses_post_processing = false,
 };
@@ -112,6 +116,7 @@ static const struct mtk_efuse_pdata mtk_efuse_pdata = {
 static const struct of_device_id mtk_efuse_of_match[] = {
 	{ .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
 	{ .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
+	{ .compatible = "mediatek,mt8188-efuse", .data = &mtk_mt8188_efuse_pdata },
 	{ .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
 	{/* sentinel */},
 };
-- 
2.45.2

[PATCH 4/5] arm64: dts: mediatek: mt8188: Add efuse for GPU speed binning

[Pablo Sun]

The OPP table of mt8188 GPU contains duplicated frequencies
for different speed bins.

In order to support OPP table, we need to provide the speed bin info
in the efuse data so the GPU driver could properly set the
supported hardware speed bin.

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 02a5bb4dbd1f..129edaf33704 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1752,6 +1752,11 @@ efuse: efuse@11f20000 {
 			lvts_efuse_data1: lvts1-calib@1ac {
 				reg = <0x1ac 0x40>;
 			};
+
+			gpu_speedbin: gpu-speedbin@580 {
+				reg = <0x581 0x1>;
+				bits = <0 3>;
+			};
 		};
 
 		gpu: gpu@13000000 {
@@ -1763,6 +1768,8 @@ gpu: gpu@13000000 {
 				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
 				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "job", "mmu", "gpu";
+			nvmem-cells = <&gpu_speedbin>;
+			nvmem-cell-names = "speed-bin";
 			operating-points-v2 = <&gpu_opp_table>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
 					<&spm MT8188_POWER_DOMAIN_MFG3>,
-- 
2.45.2

[PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

[Pablo Sun]

Configure GPU regulator supplies and enable GPU for GENIO 700 EVK.

The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and
"DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by
mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by
mt6359_vsram_others_ldo_reg.

According to section 5.2 "Recommended Operating Conditions" in
MT8390 IoT Application Processor Datasheet v1.9, The recommended
operating voltage ranges are:

- DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V
- DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V

In this commit, we set DVDD_SRAM_GPU to typical 0.85V. It is possbile
to couple it to the DVDD_GPU in future patches.

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
 .../dts/mediatek/mt8390-genio-700-evk.dts     | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
index 1474bef7e754..a1d6f4cd4e5f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
@@ -190,6 +190,11 @@ usb_p2_vbus: regulator-10 {
 	};
 };
 
+&gpu {
+	mali-supply = <&mt6359_vproc2_buck_reg>;
+	status = "okay";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
@@ -253,6 +258,14 @@ &i2c6 {
 	status = "okay";
 };
 
+&mfg0 {
+	domain-supply = <&mt6359_vproc2_buck_reg>;
+};
+
+&mfg1 {
+	domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
 &mmc0 {
 	status = "okay";
 	pinctrl-names = "default", "state_uhs";
@@ -314,6 +327,11 @@ &mt6359_vpa_buck_reg {
 	regulator-max-microvolt = <3100000>;
 };
 
+&mt6359_vproc2_buck_reg {
+	regulator-min-microvolt = <550000>;
+	regulator-max-microvolt = <860000>;
+};
+
 &mt6359_vpu_buck_reg {
 	regulator-always-on;
 };
@@ -326,6 +344,12 @@ &mt6359_vsim1_ldo_reg {
 	regulator-enable-ramp-delay = <480>;
 };
 
+/* for GPU SRAM */
+&mt6359_vsram_others_ldo_reg {
+	regulator-min-microvolt = <850000>;
+	regulator-max-microvolt = <850000>;
+};
+
 &mt6359_vufs_ldo_reg {
 	regulator-always-on;
 };
-- 
2.45.2

[PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp

[Amit Singh Tomar]

Hi,

> Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated
> mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when
> setting mfgpll clock rate.
> 
> If we keep the univpll parents from mfg_core_tmp, when setting
> GPU frequency to 390000000, the common clock framework would switch
> the parent to univpll, instead of setting mfgpll to 390000000:
> 
>       mfgpll                            0        0        0   949999756
>       univpll                           2        2        0  2340000000
>          univpll_d6                     1        1        0   390000000
>             top_mfg_core_tmp            1        1        0   390000000
>                mfg_ck_fast_ref          1        1        0   390000000
>                   mfgcfg_bg3d           1        1        0   390000000
> 
> This results in failures when subsequent devfreq operations need to
> switch to other frequencies. So remove univpll from the parent list.
> 
> This solution is taken from commit 72d38ed720e9 ("clk: mediatek:
> clk-mt8195-topckgen: Drop univplls from mfg mux parents")
> 
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
> ---
>    drivers/clk/mediatek/clk-mt8188-topckgen.c | 7 +++++--
>    1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> index 2ccc8a1c98f9..74ee692ac613 100644
> --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c
> +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = {
>    	"univpll_d3"
>    };
>    
> +/*
> + * MFG can be also parented to "univpll_d6" and "univpll_d7":
> + * these have been removed from the parents list to let us
> + * achieve GPU DVFS without any special clock handlers.
> + */
>    static const char * const mfg_core_tmp_parents[] = {
>    	"clk26m",
>    	"mainpll_d5_d2",
nit: Comma at the end of mainpll_d5_d2 is unnecessary.
> -	"univpll_d6",
> -	"univpll_d7"
>    };
>    
>    static const char * const camtg_parents[] = {
> -- 
> 2.45.2
> 
> 

Re: [PATCH 3/5] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning

[AngeloGioacchino Del Regno]

Il 20/09/24 15:41, Pablo Sun ha scritto:
> Similar to mt8186, the efuse data for mt8188's GPU speed binning
> requires post-process to convert the bit field format expected
> by the OPP table.
> 
> Since mt8188 efuse is not compatible to mt8186, add a new compatible
> entry for mt8188 and enable postprocess.
> 
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
> ---
>   drivers/nvmem/mtk-efuse.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> index 9caf04667341..4984145025bb 100644
> --- a/drivers/nvmem/mtk-efuse.c
> +++ b/drivers/nvmem/mtk-efuse.c
> @@ -105,6 +105,10 @@ static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
>   	.uses_post_processing = true,
>   };
>   
> +static const struct mtk_efuse_pdata mtk_mt8188_efuse_pdata = {
> +	.uses_post_processing = true,
> +};
> +
>   static const struct mtk_efuse_pdata mtk_efuse_pdata = {
>   	.uses_post_processing = false,
>   };
> @@ -112,6 +116,7 @@ static const struct mtk_efuse_pdata mtk_efuse_pdata = {
>   static const struct of_device_id mtk_efuse_of_match[] = {
>   	{ .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
>   	{ .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
> +	{ .compatible = "mediatek,mt8188-efuse", .data = &mtk_mt8188_efuse_pdata },

Please reuse mtk_mt8186_efuse_pdata. There's no need to add a duplicate.

{ .compatible = "mediatek,mt8188-efuse", .data = &mtk_mt8186_efuse_pdata },

Cheers,
Angelo

>   	{ .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
>   	{/* sentinel */},
>   };

Re: [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp

[AngeloGioacchino Del Regno]

Il 20/09/24 15:41, Pablo Sun ha scritto:
> Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated
> mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when
> setting mfgpll clock rate.
> 
> If we keep the univpll parents from mfg_core_tmp, when setting
> GPU frequency to 390000000, the common clock framework would switch
> the parent to univpll, instead of setting mfgpll to 390000000:
> 
>      mfgpll                            0        0        0   949999756
>      univpll                           2        2        0  2340000000
>         univpll_d6                     1        1        0   390000000
>            top_mfg_core_tmp            1        1        0   390000000
>               mfg_ck_fast_ref          1        1        0   390000000
>                  mfgcfg_bg3d           1        1        0   390000000
> 
> This results in failures when subsequent devfreq operations need to
> switch to other frequencies. So remove univpll from the parent list.
> 
> This solution is taken from commit 72d38ed720e9 ("clk: mediatek:
> clk-mt8195-topckgen: Drop univplls from mfg mux parents")
> 
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 4/5] arm64: dts: mediatek: mt8188: Add efuse for GPU speed binning

[AngeloGioacchino Del Regno]

Il 20/09/24 15:41, Pablo Sun ha scritto:
> The OPP table of mt8188 GPU contains duplicated frequencies
> for different speed bins.
> 
> In order to support OPP table, we need to provide the speed bin info
> in the efuse data so the GPU driver could properly set the
> supported hardware speed bin.
> 
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 1/5] arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain

[AngeloGioacchino Del Regno]

Il 20/09/24 15:41, Pablo Sun ha scritto:
> The clock index "CLK_APMIXED_MFGPLL" belongs to the "apmixedsys" provider,
> so fix the index.
> 
> In addition, add a "mfg1" label so following commits could set
> domain-supply for MFG1 power domain.
> 
> Fixes: b8369604050b ("UPSTREAM: arm64: dts: mediatek: mt8188: Add support for SoC power domains")
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

[AngeloGioacchino Del Regno]

Il 20/09/24 15:41, Pablo Sun ha scritto:
> Configure GPU regulator supplies and enable GPU for GENIO 700 EVK.
> 
> The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and
> "DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by
> mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by
> mt6359_vsram_others_ldo_reg.
> 
> According to section 5.2 "Recommended Operating Conditions" in
> MT8390 IoT Application Processor Datasheet v1.9, The recommended
> operating voltage ranges are:
> 
> - DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V
> - DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V
> 
> In this commit, we set DVDD_SRAM_GPU to typical 0.85V. It is possbile
> to couple it to the DVDD_GPU in future patches.
> 
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>

Is there any real difference between MT8390 and MT8188 in terms of the GPU OPPs?

I see that on MT8188, frequencies up to 880MHz want a DVDD_SRAM_GPU of 0.750V,
then 0.775/0.762/0.750 (bin1-4/5/6) on 915MHz, and 0.800/0.775/0.750 (bin1-4/5/6)
on 950MHz.

Those never call for 0.850V...! So is MT8188 (Chromebooks) wrong, or is MT8390
different in that?

Cheers,
Angelo

> ---
>   .../dts/mediatek/mt8390-genio-700-evk.dts     | 24 +++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> index 1474bef7e754..a1d6f4cd4e5f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> @@ -190,6 +190,11 @@ usb_p2_vbus: regulator-10 {
>   	};
>   };
>   
> +&gpu {
> +	mali-supply = <&mt6359_vproc2_buck_reg>;
> +	status = "okay";
> +};
> +
>   &i2c0 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&i2c0_pins>;
> @@ -253,6 +258,14 @@ &i2c6 {
>   	status = "okay";
>   };
>   
> +&mfg0 {
> +	domain-supply = <&mt6359_vproc2_buck_reg>;
> +};
> +
> +&mfg1 {
> +	domain-supply = <&mt6359_vsram_others_ldo_reg>;
> +};
> +
>   &mmc0 {
>   	status = "okay";
>   	pinctrl-names = "default", "state_uhs";
> @@ -314,6 +327,11 @@ &mt6359_vpa_buck_reg {
>   	regulator-max-microvolt = <3100000>;
>   };
>   
> +&mt6359_vproc2_buck_reg {
> +	regulator-min-microvolt = <550000>;
> +	regulator-max-microvolt = <860000>;
> +};
> +
>   &mt6359_vpu_buck_reg {
>   	regulator-always-on;
>   };
> @@ -326,6 +344,12 @@ &mt6359_vsim1_ldo_reg {
>   	regulator-enable-ramp-delay = <480>;
>   };
>   
> +/* for GPU SRAM */
> +&mt6359_vsram_others_ldo_reg {
> +	regulator-min-microvolt = <850000>;
> +	regulator-max-microvolt = <850000>;
> +};
> +
>   &mt6359_vufs_ldo_reg {
>   	regulator-always-on;
>   };

Re: [PATCH 3/5] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning

[Pablo Sun]

Hi Angelo,

On 9/23/24 16:37, AngeloGioacchino Del Regno wrote:
[snipped]
> 
> Please reuse mtk_mt8186_efuse_pdata. There's no need to add a duplicate.
> 
> { .compatible = "mediatek,mt8188-efuse", .data = &mtk_mt8186_efuse_pdata },

Thanks, will fix in v2.

Best regards,
Pablo

Re: [PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

[Pablo Sun]

Hi Angelo,

On 9/23/24 16:45, AngeloGioacchino Del Regno wrote:
[snipped]
> 
> Is there any real difference between MT8390 and MT8188 in terms of the 
> GPU OPPs?
> 
> I see that on MT8188, frequencies up to 880MHz want a DVDD_SRAM_GPU of 
> 0.750V,
> then 0.775/0.762/0.750 (bin1-4/5/6) on 915MHz, and 0.800/0.775/0.750 
> (bin1-4/5/6)
> on 950MHz.
> 
> Those never call for 0.850V...! So is MT8188 (Chromebooks) wrong, or is 
> MT8390
> different in that?

To the best of my knowledge, MT8390 and MT8188 has identical GPU
subsystem. Thus, the OPP table should have no difference.

To be specific, I list the link to the OPP table of Genio 700 EVK
(MT8390) in reference in [1]. It should match the setting in Chromebook
kernel branches.

The "typical" voltage in the datasheet is the voltage that would work
for all frequency settings. As long as it is smaller than the maximum
operating voltage, setting voltages higher than the ones specified in
the OPP table does not damage the hardware.

But this 0.85V setting is indeed not optimal. We should follow the
voltages described in the OPP table, if we want power savings.

I also considered model the regulator setting with 
'regulator-coupled-with' and 'regulator-coupled-max-spread', but I am 
not entirely sure how to describe the relation that "DVDD_GPU_SRAM 
should follow DVDD_GPU
if and only if DVDD_GPU is higher than 0.75V" - should I simply
set min-voltage to 0.75V and set 'regulator-coupled-with' ?

[1]: 
https://gitlab.com/mediatek/aiot/rity/meta-mediatek-bsp/-/blob/kirkstone/recipes-kernel/dtbo/mt8390/gpu-mali.dts

Many thanks,
Pablo

Re: [PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

[AngeloGioacchino Del Regno]

Il 23/09/24 12:14, Pablo Sun ha scritto:
> Hi Angelo,
> 
> On 9/23/24 16:45, AngeloGioacchino Del Regno wrote:
> [snipped]
>>
>> Is there any real difference between MT8390 and MT8188 in terms of the GPU OPPs?
>>
>> I see that on MT8188, frequencies up to 880MHz want a DVDD_SRAM_GPU of 0.750V,
>> then 0.775/0.762/0.750 (bin1-4/5/6) on 915MHz, and 0.800/0.775/0.750 (bin1-4/5/6)
>> on 950MHz.
>>
>> Those never call for 0.850V...! So is MT8188 (Chromebooks) wrong, or is MT8390
>> different in that?
> 
> To the best of my knowledge, MT8390 and MT8188 has identical GPU
> subsystem. Thus, the OPP table should have no difference.
> 
> To be specific, I list the link to the OPP table of Genio 700 EVK
> (MT8390) in reference in [1]. It should match the setting in Chromebook
> kernel branches.
> 
> The "typical" voltage in the datasheet is the voltage that would work
> for all frequency settings. As long as it is smaller than the maximum
> operating voltage, setting voltages higher than the ones specified in
> the OPP table does not damage the hardware.
> 
> But this 0.85V setting is indeed not optimal. We should follow the
> voltages described in the OPP table, if we want power savings.
> 
> I also considered model the regulator setting with 'regulator-coupled-with' and 
> 'regulator-coupled-max-spread', but I am not entirely sure how to describe the 
> relation that "DVDD_GPU_SRAM should follow DVDD_GPU
> if and only if DVDD_GPU is higher than 0.75V" - should I simply
> set min-voltage to 0.75V and set 'regulator-coupled-with' ?
> 

VSRAM_GPU regulator:

	regulator-min-microvolt = <750000>;
	regulator-max-microvolt = <800000>;
	regulator-coupled-with = <&(vgpu regulator)>;
	regulator-coupled-max-spread = <1000>;

VGPU regulator:
	regulator-min-microvolt = <400000>;
	regulator-max-microvolt = <800000>;
	regulator-coupled-with = <&(vsram_gpu regulator)>;
	regulator-coupled-max-spread = <1000>;

Cheers,
Angelo

> [1]: 
> https://gitlab.com/mediatek/aiot/rity/meta-mediatek-bsp/-/blob/kirkstone/recipes-kernel/dtbo/mt8390/gpu-mali.dts
> 
> Many thanks,
> Pablo
>