From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD85ACF9C5B for ; Sat, 21 Sep 2024 22:00:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6P40lEGzpuAg68v07gDez/VBXWxeIzI2fP8ZKORVHoU=; b=3kXUEE7MdHVTN2Isz6uLKIz1Eo xcUynmpE/DTFdvnFAX6zq4IzNUaRF+kOmSMPsXrs1xXD98GNz6Upd2tvBqfPcc2SfFf0yYLwyPGZQ IL6/auvEQrrf6gwginA4S3jk6eYarppMbFCKeo5OLvE7PosoJM4PRtyd6YxRZPJmNlNy2g3Q5q6xL awPpoWPxU6LaEQZ9L9G0zwN+uSDaQ1l1aLrP9scl4NHx2B/lLXTZ9uTg11voWv9umCaSDrzZykuCX UG44OU40L3RNMFg5akpGUov2wtkLWluC2TJhYCR/F7w2Pqe2xF4azc9XMpU/YtIVP8q+lg2Bm9sDc 0b+ZpoLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1ss895-0000000EK3g-2ryN; Sat, 21 Sep 2024 22:00:03 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1ss87y-0000000EJyC-0Sqb for linux-arm-kernel@lists.infradead.org; Sat, 21 Sep 2024 21:58:55 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id C45345C0616; Sat, 21 Sep 2024 21:58:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E2A72C4CEC2; Sat, 21 Sep 2024 21:58:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726955932; bh=wQnkUU12VSm06ILvfTBbRbxP36O7/91g/m/IgntMonE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=s0DmlYqV45oJD/4eVPdrJQvxuV1xW5b/Hu1MyF5a0NeuxMK4qYUYFG349e98Oo2RP UK8nMImJfQ0Xv6TwsVmcAjKdtKsdTzqD1Yv0qolaVPbPvrnXoGMHr6fTyx0CtvcCxU XHWN0YaFM7qqzpd1ZMtHfy0kX2QqxTst27FQhC4E79ACBXSOlSmRG1FsMG+/yzsBgE oW5DjI3+CzNQKXd6boNLJVTzKmQhPc9N6pQ58Dbv4GDpMdYY0UAj1JTldb0vlmnNoL cbeex78SK/H/480bAMzFuOTKiUyciqhgpwhVriGkjZleb3V/l7d3M5OKVtbCjfPQ6F +Cf3dW+T6z+cQ== Date: Sat, 21 Sep 2024 22:58:46 +0100 From: Conor Dooley To: Krzysztof Kozlowski Cc: Andrei Stefanescu , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Greg Kroah-Hartman , "Rafael J. Wysocki" , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team Subject: Re: [PATCH v3 2/4] dt-bindings: gpio: add support for NXP S32G2/S32G3 SoCs Message-ID: <20240921-party-glass-bfb7099c7ded@spud> References: <20240919134732.2626144-1-andrei.stefanescu@oss.nxp.com> <20240919134732.2626144-3-andrei.stefanescu@oss.nxp.com> <20240920-reapply-amusement-a37cf13fd910@squawk> <16950e81-e0ef-4e7c-b0ef-4f56415dceed@oss.nxp.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zg46WeEvFbsnfi1R" Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240921_145854_308657_D7B0E872 X-CRM114-Status: GOOD ( 27.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --zg46WeEvFbsnfi1R Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 20, 2024 at 03:40:31PM +0200, Krzysztof Kozlowski wrote: > On 20/09/2024 15:33, Andrei Stefanescu wrote: > > Hi Conor, > >=20 > > Thank you for your review! > >=20 > > On 20/09/2024 15:46, Conor Dooley wrote: > >> On Thu, Sep 19, 2024 at 04:47:22PM +0300, Andrei Stefanescu wrote: > >>> Add support for the GPIO driver of the NXP S32G2/S32G3 SoCs. > >>> > >>> Signed-off-by: Phu Luu An > >>> Signed-off-by: Larisa Grigore > >>> Signed-off-by: Ghennadi Procopciuc > >>> Signed-off-by: Andrei Stefanescu > >>> --- > >>> .../bindings/gpio/nxp,s32g2-siul2-gpio.yaml | 107 ++++++++++++++++= ++ > >>> 1 file changed, 107 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/gpio/nxp,s32g2-= siul2-gpio.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-g= pio.yaml b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml > >>> new file mode 100644 > >>> index 000000000000..0548028e6745 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml > >>> @@ -0,0 +1,107 @@ > >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause > >>> +# Copyright 2024 NXP > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/gpio/nxp,s32g2-siul2-gpio.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: NXP S32G2 SIUL2 GPIO controller > >>> + > >>> +maintainers: > >>> + - Ghennadi Procopciuc > >>> + - Larisa Grigore > >>> + - Andrei Stefanescu > >>> + > >>> +description: > >>> + Support for the SIUL2 GPIOs found on the S32G2 and S32G3 > >>> + chips. It includes an IRQ controller for all pins which have > >>> + an EIRQ associated. > >>> + > >>> +properties: > >>> + compatible: > >>> + items: > >>> + - const: nxp,s32g2-siul2-gpio > >> > >> Commit message and binding description say s32g2 and s32g3, but there's > >> only a compatible here for g2. > >=20 > > Yes, the SIUL2 GPIO hardware is the same for both S32G2 and S32G3 SoCs.= I plan > > to reuse the same compatible when I add the SIUL2 GPIO device tree node= for > > the S32G3 boards. Would that be ok? >=20 > There are only few exceptions where re-using compatible is allowed. Was > S32G on them? Please consult existing practice/maintainers and past revie= ws. Pretty sure I had a similar conversation about another peripheral on these devices, and it was established that these are not different fusings etc, but rather are independent SoCs that reuse an IP core. Given that, I'd expect to see a fallback compatible used here, as is the norm. Cheers, Conor. --zg46WeEvFbsnfi1R Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZu9BlgAKCRB4tDGHoIJi 0jMrAP4gLeh/hHMeDpP27U1k8GIh6qhdRTMNkNBrqOuA7sMD7wD+IV4ia9MJzyQi YC4CgFsrVpAEIJomN1x8TVn0Dvo1AAQ= =2rsY -----END PGP SIGNATURE----- --zg46WeEvFbsnfi1R--