Re: [PATCH 2/8] dt-bindings: reset: Add reset ID definition for Rockchip RK3528

Krzysztof Kozlowski
2024-10-02T06:33:25Z

On Tue, Oct 01, 2024 at 04:23:56AM +0000, Yao Zi wrote:
> Similar to previous Rockchip generations, reset IDs for RK3528 SoC
> are register offsets.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> .../dt-bindings/reset/rockchip,rk3528-cru.h | 292 ++++++++++++++++++
> 1 file changed, 292 insertions(+)
> create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h
>
> diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h
> new file mode 100644
> index 000000000000..1f8c0d38bb88
> --- /dev/null
> +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h
> @@ -0,0 +1,292 @@
> +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */

Wrong license, run checkpatch.

Also, as Conor noted, this should eb squashed with device binding.

> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
> + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
> + * Author: Joseph Chen <chenjh@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
> +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
> +
> +// CRU_SOFTRST_CON03 (Offset: 0xA0C)
> +#define SRST_CORE0_PO 0x00000030
> +#define SRST_CORE1_PO 0x00000031
> +#define SRST_CORE2_PO 0x00000032
> +#define SRST_CORE3_PO 0x00000033
> +#define SRST_CORE0 0x00000034
> +#define SRST_CORE1 0x00000035
> +#define SRST_CORE2 0x00000036
> +#define SRST_CORE3 0x00000037
> +#define SRST_NL2 0x00000038
> +#define SRST_CORE_BIU 0x00000039
> +#define SRST_CORE_CRYPTO 0x0000003A
> +
> +// CRU_SOFTRST_CON05 (Offset: 0xA14)
> +#define SRST_P_DBG 0x0000005D
> +#define SRST_POT_DBG 0x0000005E
> +#define SRST_NT_DBG 0x0000005F

What are all these? Registers? Not a binding.

Binding constants are numerical values from 0, incremented by one,
serving as abstraction layer between DTS and driver.

None of these here are bindings.

Best regards,
Krzysztof