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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sx9Sk-0000000FjPh-3Sq1; Sat, 05 Oct 2024 18:25:06 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sx9RT-0000000FjE8-0I5A for linux-arm-kernel@lists.infradead.org; Sat, 05 Oct 2024 18:23:48 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 06EEA5C597F; Sat, 5 Oct 2024 18:23:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B44C8C4CEC2; Sat, 5 Oct 2024 18:23:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728152625; bh=kxzlIO1kgZa4eBIb9lr2I1n75J/YWBPfbw062Q50ilU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=OruGk6nXMjvr08V9VJT0HhwG3POlNYQCJIs/FElKG8lHmmovlkjs4IGFkTlQ1pTf9 qYSmBZlbrSsEsu0RGxYwV8iCaYYgryvHpE+oUR7pNCroNM1gbfVpnu7/KL+PoOlffw yoU3sejW5ci25DceAtepuQA95mEcizuucSq+qjyHITnsBearvHD3DXS1atGNbl7cZM 2JjzTbmObo72j3ON+0WY+UhTNRhxuAU3GSA6ZMKlkdzrylOjpGhsr8vu/4kZINox8o oSPud5kXSWI6OvZfK6A3usUSPZ8D25BtrqjOg/Sm5CQeQzdQwr3ZfqKapKiHkGULYo AJp2BgQ3iP+zA== Date: Sat, 5 Oct 2024 13:23:45 -0500 From: Rob Herring To: Sricharan R Cc: andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, catalin.marinas@arm.com, p.zabel@pengutronix.de, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_varada@quicinc.com Subject: Re: [PATCH V3 2/7] dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding Message-ID: <20241005182345.GA482031-robh@kernel.org> References: <20241004102342.2414317-1-quic_srichara@quicinc.com> <20241004102342.2414317-3-quic_srichara@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241004102342.2414317-3-quic_srichara@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241005_112347_215294_78C6DD23 X-CRM114-Status: GOOD ( 14.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 04, 2024 at 03:53:37PM +0530, Sricharan R wrote: > From: Sricharan Ramabadhran > > Add binding for the Qualcomm IPQ5424 Global Clock Controller > > Signed-off-by: Sricharan Ramabadhran > --- > [V3] Added only new clocks for IPQ5424 and ordered for both > IPQ5332 and IPQ5424 based on min/max items > > .../bindings/clock/qcom,ipq5332-gcc.yaml | 40 ++- > include/dt-bindings/clock/qcom,ipq5424-gcc.h | 156 +++++++++ > include/dt-bindings/reset/qcom,ipq5424-gcc.h | 310 ++++++++++++++++++ > 3 files changed, 499 insertions(+), 7 deletions(-) > create mode 100644 include/dt-bindings/clock/qcom,ipq5424-gcc.h > create mode 100644 include/dt-bindings/reset/qcom,ipq5424-gcc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > index 9193de681de2..1b6d64385116 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > @@ -4,30 +4,34 @@ > $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Qualcomm Global Clock & Reset Controller on IPQ5332 > +title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424 > > maintainers: > - Bjorn Andersson > > description: | > Qualcomm global clock control module provides the clocks, resets and power > - domains on IPQ5332. > + domains on IPQ5332 and IPQ5424. > > - See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h > - > -allOf: > - - $ref: qcom,gcc.yaml# > + See also:: > + include/dt-bindings/clock/qcom,gcc-ipq5332.h > + include/dt-bindings/clock/qcom,gcc-ipq5424.h > > properties: > compatible: > - const: qcom,ipq5332-gcc > + enum: > + - qcom,ipq5332-gcc > + - qcom,ipq5424-gcc > > clocks: > + minItems: 5 > items: > - description: Board XO clock source > - description: Sleep clock source > - description: PCIE 2lane PHY pipe clock source > - description: PCIE 2lane x1 PHY pipe clock source (For second lane) > + - description: PCIE 2-lane PHY2 pipe clock source > + - description: PCIE 2-lane PHY3 pipe clock source > - description: USB PCIE wrapper pipe clock source New clocks go on the end of the list. Otherwise, it is an ABI break (or the descriptions are wrong in one case). Rob