* [PATCH v15 0/3] Add ASPEED AST2600 I2Cv2 controller driver
@ 2024-10-07 3:52 Ryan Chen
2024-10-07 3:52 ` [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Ryan Chen
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Ryan Chen @ 2024-10-07 3:52 UTC (permalink / raw)
To: brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt, conor+dt,
andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
ryan_chen
This series add AST2600 i2cv2 new register set driver. The i2cv2 driver
is new register set that have new clock divider option for more flexiable
generation. And also have separate i2c controller and target register
set for control, patch #2 is i2c controller driver only, patch #3 is add
i2c target mode driver.
The legacy register layout is mix controller/target register control
together. The following is add more detail description about new register
layout. And new feature set add for register.
-Add new clock divider option for more flexible and accurate clock rate
generation -Add tCKHighMin timing to guarantee SCL high pulse width.
-Add support dual pool buffer mode, split 32 bytes pool buffer of each
device into 2 x 16 bytes for Tx and Rx individually.
-Increase DMA buffer size to 4096 bytes and support byte alignment.
-Re-define the base address of BUS1 ~ BUS16 and Pool buffer.
-Re-define registers for separating controller and target mode control.
-Support 4 individual DMA buffers for controller Tx and Rx,
target Tx and Rx.
And following is new register set for package transfer sequence.
-New Master operation mode:
S -> Aw -> P
S -> Aw -> TxD -> P
S -> Ar -> RxD -> P
S -> Aw -> RxD -> Sr -> Ar -> TxD -> P
-Bus SDA lock auto-release capability for new controller DMA command mode.
-Bus auto timeout for new controller/target DMA mode.
The following is two versus register layout.
Old:
{I2CD00}: Function Control Register
{I2CD04}: Clock and AC Timing Control Register
{I2CD08}: Clock and AC Timing Control Register
{I2CD0C}: Interrupt Control Register
{I2CD10}: Interrupt Status Register
{I2CD14}: Command/Status Register
{I2CD18}: Slave Device Address Register
{I2CD1C}: Pool Buffer Control Register
{I2CD20}: Transmit/Receive Byte Buffer Register
{I2CD24}: DMA Mode Buffer Address Register
{I2CD28}: DMA Transfer Length Register
{I2CD2C}: Original DMA Mode Buffer Address Setting
{I2CD30}: Original DMA Transfer Length Setting and Final Status
New Register mode
{I2CC00}: Master/Slave Function Control Register
{I2CC04}: Master/Slave Clock and AC Timing Control Register
{I2CC08}: Master/Slave Transmit/Receive Byte Buffer Register
{I2CC0C}: Master/Slave Pool Buffer Control Register
{I2CM10}: Master Interrupt Control Register
{I2CM14}: Master Interrupt Status Register
{I2CM18}: Master Command/Status Register
{I2CM1C}: Master DMA Buffer Length Register
{I2CS20}: Slave~ Interrupt Control Register
{I2CS24}: Slave~ Interrupt Status Register
{I2CS28}: Slave~ Command/Status Register
{I2CS2C}: Slave~ DMA Buffer Length Register
{I2CM30}: Master DMA Mode Tx Buffer Base Address
{I2CM34}: Master DMA Mode Rx Buffer Base Address
{I2CS38}: Slave~ DMA Mode Tx Buffer Base Address
{I2CS3C}: Slave~ DMA Mode Rx Buffer Base Address
{I2CS40}: Slave Device Address Register
{I2CM48}: Master DMA Length Status Register
{I2CS4C}: Slave DMA Length Status Register
{I2CC50}: Current DMA Operating Address Status
{I2CC54}: Current DMA Operating Length Status
aspeed,global-regs:
This global register is needed, global register is setting for
new clock divide control, and new register set control.
ASPEED SOC chip is server product, i2c bus may have fingerprint
connect to another board. And also support hotplug.
The following is board-specific design example.
Board A Board B
------------------------- ------------------------
|i2c bus#1(controller/target)<=fingerprint=>i2c bus#x (controller/target)|
|i2c bus#2(controller)-> tmp i2c device | | |
|i2c bus#3(controller)-> adc i2c device | | |
------------------------- ------------------------
i2c-scl-clk-low-timeout-us:
For example I2C controller as slave mode, and suddenly disconnected.
Slave state machine will keep waiting for controller clock in for rx/tx
transmit. So it need timeout setting to enable timeout unlock controller
state. And in another side. In Master side also need avoid suddenly
slave miss(un-plug), Master will timeout and release the SDA/SCL.
aspeed,enable-dma:
For example The bus#1 have trunk data needed for transfer,
it can enable bus dma mode transfer, it can reduce cpu utilized.
Others bus bus#2/3 use defautl buffer mode.
v15:
-i2c-ast2600.c
-add include unaligned.h
-rename all master -> controller, slave -> target.
-keep multi-master to align property.
-remove no used element in ast2600_i2c_bus.
v14:
-aspeed,i2c.yaml
-v13 change people reviewed-by tag, v14 fixed to original people tag,
modify to Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-struct ast2600_i2c_bus layout optimal.
-ast2600_select_i2c_clock refine.
-ast2600_i2c_recover_bus overridden fix.
-dma_mapping_error() returned error code shadowed modify.
-buffer register in a 4-byte aligned simplified
-remove smbus alert
v13:
-separate i2c master and slave driver to be two patchs.
-modify include header list, add bits.h include. remove of*.h
-modify (((x) >> 24) & GENMASK(5, 0)) to (((x) & GENMASK(29, 24)) >> 24)
-modify ast2600_select_i2c_clock function implement.
-modify ast2600_i2c_recover_bus function u32 claim to
u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
v12:
-aspeed,i2c.yaml
-add Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-i2c-ast2600.c
-update include by alphabetical order
-make just a one TAB and put the last two lines on the single one
-remove no used timing_table structre
-remove enum explicit assinment
-rewritten to avoid this and using loop in ast2600_select_i2c_clock
-use GENMASK for most 0xffff
-remove too many parentheses
-use str_read_write replace read write string
-remove redundant blank line after ast2600_i2c_bus_of_table
-fix wrong multi-line style of the comment
-use macro for i2c standard speeds
-remove useless noise dev_info
v11:
-aspeed,i2c.yaml
-no change, the same with v10.
-i2c-ast2600.c
-modify alert_enable from int -> boolean.
-modify dbg string recovery -> recover.
-remove no need to init 0.
-remove new line after break.
-remove unneeded empty line.
-modify dma_alloc_coherent to dmam_alloc_coherent
-modify probe nomem return dev_err_probe
-modify i2c_add_adapter to devm_i2c_adapter
-modify checkpatch: Alignment should match open parenthesis
-modify checkpatch: braces {} should be used on all arms of this statement
-modify checkpatch: Unbalanced braces around else statement
v10:
-aspeed,i2c.yaml
-move unevaluatedProperties after allOf.
-remove extra one blank line.
-i2c-ast2600.c
-no change, the same with v8.
v9:
-aspeed,i2c.yaml
-backoff to v7.
-no fix typo in maintainer's name and email. this would be another patch.
-no remove address-cells, size-cells, this would be another patch.
-use aspeed,enable-dma property instead of aspeed,xfer-mode selection.
-fix allOf and else false properties for aspeed,ast2600-i2cv2.
-i2c-ast2600.c
-no change, the same with v8
v8:
-aspeed,i2c.yaml
-modify commit message.
-Fix typo in maintainer's name and email.
-remove address-cells, size-cells.
-i2c-ast2600.c
-move "i2c timeout counter" comment description before property_read.
-remove redundant code "return ret" in probe end.
v7:
-aspeed,i2c.yaml
-Update ASPEED I2C maintainers email.
-use aspeed,enable-dma property instead of aspeed,xfer-mode selection.
-fix allOf and else false properties for aspeed,ast2600-i2cv2.
-i2c-ast2600.c
-remove aspeed,xfer-mode instead of aspeed,enable-dma mode. buffer mode
is default.
-remove aspeed,timeout instead of i2c-scl-clk-low-timeout-us for
timeout setting.
v6:
-remove aspeed,i2cv2.yaml, merge to aspeed,i2c.yaml -add support for
i2cv2 properites.
-i2c-ast2600.c
-fix ast2600_i2c_remove ordering.
-remove ast2600_i2c_probe goto labels, and add dev_err_probe -remove
redundant deb_dbg debug message.
-rename gr_regmap -> global_regs
v5:
-remove ast2600-i2c-global.yaml, i2c-ast2600-global.c.
-i2c-ast2600.c
-remove legacy clock divide, all go for new clock divide.
-remove duplicated read isr.
-remove no used driver match
-fix probe return for each labels return.
-global use mfd driver, driver use phandle to regmap read/write.
-rename aspeed,i2c-ast2600.yaml to aspeed,i2cv2.yaml -remove bus-frequency.
-add required aspeed,gr
-add timeout, byte-mode, buff-mode properites.
v4:
-fix i2c-ast2600.c driver buffer mode use single buffer conflit in
master slave mode both enable.
-fix kmemleak issue when use dma mode.
-fix typo aspeed,i2c-ast2600.yaml compatible is "aspeed,ast2600-i2c"
-fix typo aspeed,i2c-ast2600.ymal to aspeed,i2c-ast2600.yaml
v3:
-fix i2c global clock divide default value.
-remove i2c slave no used dev_dbg info.
v2:
-add i2c global ymal file commit.
-rename file name from new to ast2600.
aspeed-i2c-new-global.c -> i2c-ast2600-global.c
aspeed-i2c-new-global.h -> i2c-ast2600-global.h
i2c-new-aspeed.c -> i2c-ast2600.c
-rename all driver function name to ast2600.
Ryan Chen (3):
dt-bindings: i2c: aspeed: support for AST2600-i2cv2
i2c: aspeed: support AST2600 i2c new register mode driver
i2c: aspeed: support AST2600 i2c new register target mode driver
.../devicetree/bindings/i2c/aspeed,i2c.yaml | 51 +-
drivers/i2c/busses/Kconfig | 11 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-ast2600.c | 1553 +++++++++++++++++
4 files changed, 1613 insertions(+), 3 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-ast2600.c
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2
2024-10-07 3:52 [PATCH v15 0/3] Add ASPEED AST2600 I2Cv2 controller driver Ryan Chen
@ 2024-10-07 3:52 ` Ryan Chen
2025-02-21 8:25 ` Ryan Chen
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
2024-10-07 3:52 ` [PATCH v15 3/3] i2c: aspeed: support AST2600 i2c new register target " Ryan Chen
2 siblings, 1 reply; 15+ messages in thread
From: Ryan Chen @ 2024-10-07 3:52 UTC (permalink / raw)
To: brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt, conor+dt,
andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
ryan_chen
Cc: Krzysztof Kozlowski
Add ast2600-i2cv2 compatible and aspeed,global-regs, aspeed,enable-dma
and description for ast2600-i2cv2.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/i2c/aspeed,i2c.yaml | 51 +++++++++++++++++--
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
index 6df27b47b922..6c16fc76c978 100644
--- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
@@ -9,9 +9,6 @@ title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs
maintainers:
- Rayn Chen <rayn_chen@aspeedtech.com>
-allOf:
- - $ref: /schemas/i2c/i2c-controller.yaml#
-
properties:
compatible:
enum:
@@ -49,12 +46,50 @@ properties:
description:
states that there is another master active on this bus
+ aspeed,enable-dma:
+ type: boolean
+ description: |
+ I2C bus enable dma mode transfer.
+
+ ASPEED ast2600 platform equipped with 16 I2C controllers that share a
+ single DMA engine. DTS files can specify the data transfer mode to/from
+ the device, either DMA or programmed I/O. However, hardware limitations
+ may require a DTS to manually allocate which controller can use DMA mode.
+ The "aspeed,enable-dma" property allows control of this.
+
+ In cases where one the hardware design results in a specific
+ controller handling a larger amount of data, a DTS would likely
+ enable DMA mode for that one controller.
+
+ aspeed,global-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of i2c global register node.
+
required:
- reg
- compatible
- clocks
- resets
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2600-i2cv2
+
+ then:
+ properties:
+ reg:
+ minItems: 2
+ required:
+ - aspeed,global-regs
+ else:
+ properties:
+ aspeed,global-regs: false
+ aspeed,enable-dma: false
+
unevaluatedProperties: false
examples:
@@ -71,3 +106,13 @@ examples:
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c1: i2c@80 {
+ compatible = "aspeed,ast2600-i2cv2";
+ reg = <0x80 0x80>, <0xc00 0x20>;
+ aspeed,global-regs = <&i2c_global>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-10-07 3:52 [PATCH v15 0/3] Add ASPEED AST2600 I2Cv2 controller driver Ryan Chen
2024-10-07 3:52 ` [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Ryan Chen
@ 2024-10-07 3:52 ` Ryan Chen
2024-11-11 11:00 ` Naresh Solanki
` (2 more replies)
2024-10-07 3:52 ` [PATCH v15 3/3] i2c: aspeed: support AST2600 i2c new register target " Ryan Chen
2 siblings, 3 replies; 15+ messages in thread
From: Ryan Chen @ 2024-10-07 3:52 UTC (permalink / raw)
To: brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt, conor+dt,
andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
ryan_chen
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode. The new register mode have separate register
set to control i2c controller and target. This patch is for i2c
controller mode driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/i2c/busses/Kconfig | 11 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-ast2600.c | 1032 ++++++++++++++++++++++++++++++
3 files changed, 1044 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-ast2600.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a22f9125322a..abfb027350d4 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -410,6 +410,17 @@ config I2C_ALTERA
This driver can also be built as a module. If so, the module
will be called i2c-altera.
+config I2C_AST2600
+ tristate "Aspeed I2C v2 Controller"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ select I2C_SMBUS
+ help
+ If you say yes to this option, support will be included for the
+ Aspeed I2C controller with new register set.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-ast2600.
+
config I2C_ASPEED
tristate "Aspeed I2C Controller"
depends on ARCH_ASPEED || COMPILE_TEST
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 78d0561339e5..5665b60b1566 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o
obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
+obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
obj-$(CONFIG_I2C_AT91) += i2c-at91.o
i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2600.c
new file mode 100644
index 000000000000..17ba0ee77c27
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ast2600.c
@@ -0,0 +1,1032 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ASPEED AST2600 new register set I2C controller driver
+ *
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <asm/unaligned.h>
+#include <linux/array_size.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/i2c-smbus.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/minmax.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/string_helpers.h>
+
+#define AST2600_I2CG_ISR 0x00
+#define AST2600_I2CG_SLAVE_ISR 0x04
+#define AST2600_I2CG_OWNER 0x08
+#define AST2600_I2CG_CTRL 0x0C
+#define AST2600_I2CG_CLK_DIV_CTRL 0x10
+
+#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
+#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
+#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
+#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
+#define AST2600_GLOBAL_INIT \
+ (AST2600_I2CG_CTRL_NEW_REG | AST2600_I2CG_CTRL_NEW_CLK_DIV)
+/*
+ * APB clk : 100Mhz
+ * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
+ * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6)
+ * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
+ * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
+ * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
+ * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
+ * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
+ * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
+ * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
+ * 0x12 : 400Khz : 10Mhz : 1.6us
+ * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
+ * 0x08 : 1Mhz : 20Mhz : 0.8us
+ */
+#define I2CCG_DIV_CTRL 0xC6411208
+
+/* 0x00 : I2CC Controller/Target Function Control Register */
+#define AST2600_I2CC_FUN_CTRL 0x00
+#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
+#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
+#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0)) << 18)
+#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
+#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
+#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
+#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
+#define AST2600_I2CC_MSB_STS BIT(9)
+#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
+#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
+#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
+/* reserver 5 : 2 */
+#define AST2600_I2CC_SLAVE_EN BIT(1)
+#define AST2600_I2CC_MASTER_EN BIT(0)
+
+/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
+#define AST2600_I2CC_AC_TIMING 0x04
+#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0)) << 24)
+#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0)) << 20)
+#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
+#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
+#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
+#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1, 0)) << 8)
+#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
+
+/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
+#define AST2600_I2CC_STS_AND_BUFF 0x08
+#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
+#define AST2600_I2CC_SDA_OE BIT(28)
+#define AST2600_I2CC_SDA_O BIT(27)
+#define AST2600_I2CC_SCL_OE BIT(26)
+#define AST2600_I2CC_SCL_O BIT(25)
+
+#define AST2600_I2CC_SCL_LINE_STS BIT(18)
+#define AST2600_I2CC_SDA_LINE_STS BIT(17)
+#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
+
+#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) & GENMASK(7, 0))
+
+/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
+#define AST2600_I2CC_BUFF_CTRL 0x0C
+#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29, 24)) >> 24)
+#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 16) | BIT(0))
+#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 8) | BIT(0))
+#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12, 8)) >> 8) + 1)
+
+/* 0x10 : I2CM Controller Interrupt Control Register */
+#define AST2600_I2CM_IER 0x10
+/* 0x14 : I2CM Controller Interrupt Status Register : WC */
+#define AST2600_I2CM_ISR 0x14
+
+#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
+#define AST2600_I2CM_PKT_ERROR BIT(17)
+#define AST2600_I2CM_PKT_DONE BIT(16)
+
+#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
+#define AST2600_I2CM_SDA_DL_TO BIT(14)
+#define AST2600_I2CM_BUS_RECOVER BIT(13)
+#define AST2600_I2CM_SMBUS_ALT BIT(12)
+
+#define AST2600_I2CM_SCL_LOW_TO BIT(6)
+#define AST2600_I2CM_ABNORMAL BIT(5)
+#define AST2600_I2CM_NORMAL_STOP BIT(4)
+#define AST2600_I2CM_ARBIT_LOSS BIT(3)
+#define AST2600_I2CM_RX_DONE BIT(2)
+#define AST2600_I2CM_TX_NAK BIT(1)
+#define AST2600_I2CM_TX_ACK BIT(0)
+
+/* 0x18 : I2CM Controller Command/Status Register */
+#define AST2600_I2CM_CMD_STS 0x18
+#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0)) << 24)
+#define AST2600_I2CM_PKT_EN BIT(16)
+#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
+#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
+#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
+#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
+#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
+
+#define AST2600_I2CM_RX_DMA_EN BIT(9)
+#define AST2600_I2CM_TX_DMA_EN BIT(8)
+/* Command Bit */
+#define AST2600_I2CM_RX_BUFF_EN BIT(7)
+#define AST2600_I2CM_TX_BUFF_EN BIT(6)
+#define AST2600_I2CM_STOP_CMD BIT(5)
+#define AST2600_I2CM_RX_CMD_LAST BIT(4)
+#define AST2600_I2CM_RX_CMD BIT(3)
+
+#define AST2600_I2CM_TX_CMD BIT(1)
+#define AST2600_I2CM_START_CMD BIT(0)
+
+/* 0x1C : I2CM Controller DMA Transfer Length Register */
+#define AST2600_I2CM_DMA_LEN 0x1C
+/* Tx Rx support length 1 ~ 4096 */
+#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0)) << 16) | BIT(31))
+#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0)) | BIT(15))
+
+/* 0x20 : I2CS Target Interrupt Control Register */
+#define AST2600_I2CS_IER 0x20
+/* 0x24 : I2CS Target Interrupt Status Register */
+#define AST2600_I2CS_ISR 0x24
+
+#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
+#define AST2600_I2CS_SLAVE_PENDING BIT(29)
+
+#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
+#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
+
+#define AST2600_I2CS_ADDR3_NAK BIT(22)
+#define AST2600_I2CS_ADDR2_NAK BIT(21)
+#define AST2600_I2CS_ADDR1_NAK BIT(20)
+
+#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
+#define AST2600_I2CS_PKT_ERROR BIT(17)
+#define AST2600_I2CS_PKT_DONE BIT(16)
+#define AST2600_I2CS_INACTIVE_TO BIT(15)
+
+#define AST2600_I2CS_SLAVE_MATCH BIT(7)
+#define AST2600_I2CS_ABNOR_STOP BIT(5)
+#define AST2600_I2CS_STOP BIT(4)
+#define AST2600_I2CS_RX_DONE_NAK BIT(3)
+#define AST2600_I2CS_RX_DONE BIT(2)
+#define AST2600_I2CS_TX_NAK BIT(1)
+#define AST2600_I2CS_TX_ACK BIT(0)
+
+/* 0x28 : I2CS Target CMD/Status Register */
+#define AST2600_I2CS_CMD_STS 0x28
+#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
+#define AST2600_I2CS_PKT_MODE_EN BIT(16)
+#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
+#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
+
+#define AST2600_I2CS_ALT_EN BIT(10)
+#define AST2600_I2CS_RX_DMA_EN BIT(9)
+#define AST2600_I2CS_TX_DMA_EN BIT(8)
+#define AST2600_I2CS_RX_BUFF_EN BIT(7)
+#define AST2600_I2CS_TX_BUFF_EN BIT(6)
+#define AST2600_I2CS_RX_CMD_LAST BIT(4)
+
+#define AST2600_I2CS_TX_CMD BIT(2)
+
+#define AST2600_I2CS_DMA_LEN 0x2C
+#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0)) << 16) | BIT(31))
+#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0)) | BIT(15))
+
+/* I2CM Controller DMA Tx Buffer Register */
+#define AST2600_I2CM_TX_DMA 0x30
+/* I2CM Controller DMA Rx Buffer Register */
+#define AST2600_I2CM_RX_DMA 0x34
+/* I2CS Target DMA Tx Buffer Register */
+#define AST2600_I2CS_TX_DMA 0x38
+/* I2CS Target DMA Rx Buffer Register */
+#define AST2600_I2CS_RX_DMA 0x3C
+
+#define AST2600_I2CS_ADDR_CTRL 0x40
+
+#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
+#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
+#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
+
+#define AST2600_I2CM_DMA_LEN_STS 0x48
+#define AST2600_I2CS_DMA_LEN_STS 0x4C
+
+#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
+#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28, 16)) >> 16)
+
+/* 0x40 : Target Device Address Register */
+#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
+#define AST2600_I2CS_ADDR3(x) ((x) << 16)
+#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
+#define AST2600_I2CS_ADDR2(x) ((x) << 8)
+#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
+#define AST2600_I2CS_ADDR1(x) (x)
+
+#define I2C_TARGET_MSG_BUF_SIZE 256
+
+#define AST2600_I2C_DMA_SIZE 4096
+
+#define CONTROLLER_TRIGGER_LAST_STOP (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
+#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL | AST2600_I2CS_PKT_MODE_EN)
+
+#define AST_I2C_TIMEOUT_CLK 0x2
+
+enum xfer_mode {
+ BYTE_MODE,
+ BUFF_MODE,
+ DMA_MODE,
+};
+
+struct ast2600_i2c_bus {
+ struct i2c_adapter adap;
+ struct device *dev;
+ void __iomem *reg_base;
+ struct regmap *global_regs;
+ struct reset_control *rst;
+ struct clk *clk;
+ struct i2c_timings timing_info;
+ struct completion cmd_complete;
+ struct i2c_msg *msgs;
+ u8 *controller_dma_safe_buf;
+ dma_addr_t controller_dma_addr;
+ u32 apb_clk;
+ u32 timeout;
+ int irq;
+ int cmd_err;
+ int msgs_index;
+ int msgs_count;
+ int controller_xfer_cnt;
+ size_t buf_index;
+ size_t buf_size;
+ enum xfer_mode mode;
+ bool multi_master;
+ /* Buffer mode */
+ void __iomem *buf_base;
+ struct i2c_smbus_alert_setup alert_data;
+};
+
+static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
+{
+ unsigned long base_clk[16];
+ int baseclk_idx = 0;
+ int divisor = 0;
+ u32 clk_div_reg;
+ u32 scl_low;
+ u32 scl_high;
+ u32 data;
+
+ regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, &clk_div_reg);
+
+ for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
+ if (i == 0)
+ base_clk[i] = i2c_bus->apb_clk;
+ else if (i < 5)
+ base_clk[i] = (i2c_bus->apb_clk * 2) /
+ (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
+ else
+ base_clk[i] = base_clk[4] >> (i - 5);
+
+ if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
+ baseclk_idx = i;
+ divisor = DIV_ROUND_UP(base_clk[i], i2c_bus->timing_info.bus_freq_hz);
+ break;
+ }
+ }
+ baseclk_idx = min(baseclk_idx, 15);
+ divisor = min(divisor, 32);
+ scl_low = min(divisor * 9 / 16 - 1, 15);
+ scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
+ data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
+ if (i2c_bus->timeout) {
+ data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
+ data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
+ }
+
+ return data;
+}
+
+static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus)
+{
+ u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ int ret = 0;
+ u32 ctrl;
+ int r;
+
+ dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n", i2c_bus->adap.nr, state);
+
+ ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ /* Disable controller */
+ writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
+ i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) | AST2600_I2CC_MASTER_EN,
+ i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ reinit_completion(&i2c_bus->cmd_complete);
+ i2c_bus->cmd_err = 0;
+
+ /* Check 0x14's SDA and SCL status */
+ state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state & AST2600_I2CC_SCL_LINE_STS)) {
+ writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+ r = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
+ if (r == 0) {
+ dev_dbg(i2c_bus->dev, "recovery timed out\n");
+ writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ return -ETIMEDOUT;
+ } else if (i2c_bus->cmd_err) {
+ dev_dbg(i2c_bus->dev, "recovery error\n");
+ ret = -EPROTO;
+ }
+ }
+
+ /* Recovery done */
+ state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ if (state & AST2600_I2CC_BUS_BUSY_STS) {
+ dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
+ ret = -EPROTO;
+ }
+
+ /* restore original controller setting */
+ writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ return ret;
+}
+
+static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ int xfer_len;
+ int ret;
+
+ cmd |= AST2600_I2CM_PKT_EN;
+ xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
+ if (xfer_len > AST2600_I2C_DMA_SIZE)
+ xfer_len = AST2600_I2C_DMA_SIZE;
+ else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= AST2600_I2CM_STOP_CMD;
+
+ if (cmd & AST2600_I2CM_START_CMD) {
+ cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
+ i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
+ if (!i2c_bus->controller_dma_safe_buf)
+ return -ENOMEM;
+ i2c_bus->controller_dma_addr =
+ dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
+ msg->len, DMA_TO_DEVICE);
+ ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
+ if (ret) {
+ i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
+ i2c_bus->controller_dma_safe_buf = NULL;
+ return ret;
+ }
+ }
+
+ if (xfer_len) {
+ cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
+ writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
+ i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
+ writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
+ i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
+ }
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ u32 wbuf_dword;
+ int xfer_len;
+ int i;
+
+ cmd |= AST2600_I2CM_PKT_EN;
+ xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
+ if (xfer_len > i2c_bus->buf_size)
+ xfer_len = i2c_bus->buf_size;
+ else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= AST2600_I2CM_STOP_CMD;
+
+ if (cmd & AST2600_I2CM_START_CMD)
+ cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
+
+ if (xfer_len) {
+ cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
+ /*
+ * The controller's buffer register supports dword writes only.
+ * Therefore, write dwords to the buffer register in a 4-byte aligned,
+ * and write the remaining unaligned data at the end.
+ */
+ for (i = 0; i < xfer_len; i += 4) {
+ int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
+
+ switch (min(xfer_len - i, 4) % 4) {
+ case 1:
+ wbuf_dword = msg->buf[xfer_cnt];
+ break;
+ case 2:
+ wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
+ break;
+ case 3:
+ wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
+ break;
+ default:
+ wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
+ break;
+ }
+ writel(wbuf_dword, i2c_bus->buf_base + i);
+ }
+ writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ }
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ int xfer_len;
+
+ xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
+
+ cmd |= AST2600_I2CM_PKT_EN;
+
+ if (cmd & AST2600_I2CM_START_CMD)
+ cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
+
+ if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
+ ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
+ cmd |= AST2600_I2CM_STOP_CMD;
+
+ if (xfer_len) {
+ cmd |= AST2600_I2CM_TX_CMD;
+ writel(msg->buf[i2c_bus->controller_xfer_cnt],
+ i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ }
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ int xfer_len;
+ u32 cmd;
+ int ret;
+
+ cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
+ AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
+
+ if (msg->flags & I2C_M_RECV_LEN) {
+ xfer_len = 1;
+ } else if (msg->len > AST2600_I2C_DMA_SIZE) {
+ xfer_len = AST2600_I2C_DMA_SIZE;
+ } else {
+ xfer_len = msg->len;
+ if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+ writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
+ i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
+ if (!i2c_bus->controller_dma_safe_buf)
+ return -ENOMEM;
+ i2c_bus->controller_dma_addr =
+ dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
+ msg->len, DMA_FROM_DEVICE);
+ ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
+ if (ret) {
+ i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
+ i2c_bus->controller_dma_safe_buf = NULL;
+ return ret;
+ }
+ writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ int xfer_len;
+ u32 cmd;
+
+ cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
+ AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
+
+ if (msg->flags & I2C_M_RECV_LEN) {
+ dev_dbg(i2c_bus->dev, "smbus read\n");
+ xfer_len = 1;
+ } else if (msg->len > i2c_bus->buf_size) {
+ xfer_len = i2c_bus->buf_size;
+ } else {
+ xfer_len = msg->len;
+ if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+ writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ u32 cmd;
+
+ cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
+ AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
+
+ if (msg->flags & I2C_M_RECV_LEN) {
+ dev_dbg(i2c_bus->dev, "smbus read\n");
+ } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
+ if (msg->len == 1)
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+
+ return 0;
+}
+
+static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+
+ /* send start */
+ dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
+ i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
+ msg->len, str_plural(msg->len),
+ msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
+
+ i2c_bus->controller_xfer_cnt = 0;
+ i2c_bus->buf_index = 0;
+
+ if (msg->flags & I2C_M_RD) {
+ if (i2c_bus->mode == DMA_MODE)
+ return ast2600_i2c_setup_dma_rx(i2c_bus);
+ else if (i2c_bus->mode == BUFF_MODE)
+ return ast2600_i2c_setup_buff_rx(i2c_bus);
+ else
+ return ast2600_i2c_setup_byte_rx(i2c_bus);
+ } else {
+ if (i2c_bus->mode == DMA_MODE)
+ return ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
+ else if (i2c_bus->mode == BUFF_MODE)
+ return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD, i2c_bus);
+ else
+ return ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
+ }
+}
+
+static int ast2600_i2c_irq_err_to_errno(u32 irq_status)
+{
+ if (irq_status & AST2600_I2CM_ARBIT_LOSS)
+ return -EAGAIN;
+ if (irq_status & (AST2600_I2CM_SDA_DL_TO | AST2600_I2CM_SCL_LOW_TO))
+ return -EBUSY;
+ if (irq_status & (AST2600_I2CM_ABNORMAL))
+ return -EPROTO;
+
+ return 0;
+}
+
+static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
+{
+ struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
+ u32 cmd = AST2600_I2CM_PKT_EN;
+ int xfer_len;
+ int i;
+
+ sts &= ~AST2600_I2CM_PKT_DONE;
+ writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
+ switch (sts) {
+ case AST2600_I2CM_PKT_ERROR:
+ i2c_bus->cmd_err = -EAGAIN;
+ complete(&i2c_bus->cmd_complete);
+ break;
+ case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for issue */
+ fallthrough;
+ case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK | AST2600_I2CM_NORMAL_STOP:
+ i2c_bus->cmd_err = -ENXIO;
+ complete(&i2c_bus->cmd_complete);
+ break;
+ case AST2600_I2CM_NORMAL_STOP:
+ /* write 0 byte only have stop isr */
+ i2c_bus->msgs_index++;
+ if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
+ if (ast2600_i2c_do_start(i2c_bus)) {
+ i2c_bus->cmd_err = -ENOMEM;
+ complete(&i2c_bus->cmd_complete);
+ }
+ } else {
+ i2c_bus->cmd_err = i2c_bus->msgs_index;
+ complete(&i2c_bus->cmd_complete);
+ }
+ break;
+ case AST2600_I2CM_TX_ACK:
+ case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
+ if (i2c_bus->mode == DMA_MODE)
+ xfer_len = AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CM_DMA_LEN_STS));
+ else if (i2c_bus->mode == BUFF_MODE)
+ xfer_len = AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ else
+ xfer_len = 1;
+
+ i2c_bus->controller_xfer_cnt += xfer_len;
+
+ if (i2c_bus->controller_xfer_cnt == msg->len) {
+ if (i2c_bus->mode == DMA_MODE) {
+ dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
+ msg->len, DMA_TO_DEVICE);
+ i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
+ msg, true);
+ i2c_bus->controller_dma_safe_buf = NULL;
+ }
+ i2c_bus->msgs_index++;
+ if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
+ i2c_bus->cmd_err = i2c_bus->msgs_index;
+ complete(&i2c_bus->cmd_complete);
+ } else {
+ if (ast2600_i2c_do_start(i2c_bus)) {
+ i2c_bus->cmd_err = -ENOMEM;
+ complete(&i2c_bus->cmd_complete);
+ }
+ }
+ } else {
+ if (i2c_bus->mode == DMA_MODE)
+ ast2600_i2c_setup_dma_tx(0, i2c_bus);
+ else if (i2c_bus->mode == BUFF_MODE)
+ ast2600_i2c_setup_buff_tx(0, i2c_bus);
+ else
+ ast2600_i2c_setup_byte_tx(0, i2c_bus);
+ }
+ break;
+ case AST2600_I2CM_RX_DONE:
+ case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
+ /* do next rx */
+ if (i2c_bus->mode == DMA_MODE) {
+ xfer_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CM_DMA_LEN_STS));
+ } else if (i2c_bus->mode == BUFF_MODE) {
+ xfer_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < xfer_len; i++)
+ msg->buf[i2c_bus->controller_xfer_cnt + i] =
+ readb(i2c_bus->buf_base + 0x10 + i);
+ } else {
+ xfer_len = 1;
+ msg->buf[i2c_bus->controller_xfer_cnt] =
+ AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
+ AST2600_I2CC_STS_AND_BUFF));
+ }
+
+ if (msg->flags & I2C_M_RECV_LEN) {
+ msg->len = min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
+ msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
+ msg->flags &= ~I2C_M_RECV_LEN;
+ }
+ i2c_bus->controller_xfer_cnt += xfer_len;
+
+ if (i2c_bus->controller_xfer_cnt == msg->len) {
+ if (i2c_bus->mode == DMA_MODE) {
+ dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
+ msg->len, DMA_FROM_DEVICE);
+ i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
+ msg, true);
+ i2c_bus->controller_dma_safe_buf = NULL;
+ }
+
+ i2c_bus->msgs_index++;
+ if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
+ i2c_bus->cmd_err = i2c_bus->msgs_index;
+ complete(&i2c_bus->cmd_complete);
+ } else {
+ if (ast2600_i2c_do_start(i2c_bus)) {
+ i2c_bus->cmd_err = -ENOMEM;
+ complete(&i2c_bus->cmd_complete);
+ }
+ }
+ } else {
+ /* next rx */
+ cmd |= AST2600_I2CM_RX_CMD;
+ if (i2c_bus->mode == DMA_MODE) {
+ cmd |= AST2600_I2CM_RX_DMA_EN;
+ xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
+ if (xfer_len > AST2600_I2C_DMA_SIZE) {
+ xfer_len = AST2600_I2C_DMA_SIZE;
+ } else {
+ if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+ writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
+ i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
+ writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
+ i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
+ } else if (i2c_bus->mode == BUFF_MODE) {
+ cmd |= AST2600_I2CM_RX_BUFF_EN;
+ xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
+ if (xfer_len > i2c_bus->buf_size) {
+ xfer_len = i2c_bus->buf_size;
+ } else {
+ if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+ writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ } else {
+ if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
+ ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
+ cmd |= CONTROLLER_TRIGGER_LAST_STOP;
+ }
+ }
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+ }
+ break;
+ default:
+ dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
+ break;
+ }
+}
+
+static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus *i2c_bus)
+{
+ u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
+ u32 ctrl;
+
+ sts &= ~AST2600_I2CM_SMBUS_ALT;
+
+ if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
+ writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base + AST2600_I2CM_ISR);
+ ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ i2c_bus->cmd_err = -EPROTO;
+ complete(&i2c_bus->cmd_complete);
+ return 1;
+ }
+
+ if (AST2600_I2CM_BUS_RECOVER & sts) {
+ writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base + AST2600_I2CM_ISR);
+ i2c_bus->cmd_err = 0;
+ complete(&i2c_bus->cmd_complete);
+ return 1;
+ }
+
+ i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
+ if (i2c_bus->cmd_err) {
+ writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
+ complete(&i2c_bus->cmd_complete);
+ return 1;
+ }
+
+ if (AST2600_I2CM_PKT_DONE & sts) {
+ ast2600_i2c_controller_package_irq(i2c_bus, sts);
+ return 1;
+ }
+
+ return 0;
+}
+
+static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id)
+{
+ struct ast2600_i2c_bus *i2c_bus = dev_id;
+
+ return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
+}
+
+static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+ struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
+ unsigned long timeout;
+ int ret;
+
+ if (!i2c_bus->multi_master &&
+ (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_BUS_BUSY_STS)) {
+ ret = ast2600_i2c_recover_bus(i2c_bus);
+ if (ret)
+ return ret;
+ }
+
+ i2c_bus->cmd_err = 0;
+ i2c_bus->msgs = msgs;
+ i2c_bus->msgs_index = 0;
+ i2c_bus->msgs_count = num;
+ reinit_completion(&i2c_bus->cmd_complete);
+ ret = ast2600_i2c_do_start(i2c_bus);
+ if (ret)
+ goto controller_out;
+ timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
+ if (timeout == 0) {
+ u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
+ readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
+ readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+ writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ if (i2c_bus->multi_master &&
+ (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
+ AST2600_I2CC_BUS_BUSY_STS))
+ ast2600_i2c_recover_bus(i2c_bus);
+
+ ret = -ETIMEDOUT;
+ } else {
+ ret = i2c_bus->cmd_err;
+ }
+
+ dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr, i2c_bus->cmd_err);
+
+controller_out:
+ if (i2c_bus->mode == DMA_MODE) {
+ kfree(i2c_bus->controller_dma_safe_buf);
+ i2c_bus->controller_dma_safe_buf = NULL;
+ }
+
+ return ret;
+}
+
+static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus)
+{
+ struct platform_device *pdev = to_platform_device(i2c_bus->dev);
+ u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE | AST2600_I2CC_MASTER_EN;
+
+ /* I2C Reset */
+ writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ i2c_bus->multi_master = device_property_read_bool(&pdev->dev, "multi-master");
+ if (!i2c_bus->multi_master)
+ fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
+
+ /* Enable Controller Mode */
+ writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ /* disable target address */
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
+
+ /* Set AC Timing */
+ writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base + AST2600_I2CC_AC_TIMING);
+
+ /* Clear Interrupt */
+ writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR);
+}
+
+static u32 ast2600_i2c_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static const struct i2c_algorithm i2c_ast2600_algorithm = {
+ .xfer = ast2600_i2c_controller_xfer,
+ .functionality = ast2600_i2c_functionality,
+};
+
+static int ast2600_i2c_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ast2600_i2c_bus *i2c_bus;
+ struct resource *res;
+ u32 global_ctrl;
+ int ret;
+
+ i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
+ if (!i2c_bus)
+ return -ENOMEM;
+
+ i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(i2c_bus->reg_base))
+ return PTR_ERR(i2c_bus->reg_base);
+
+ i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(i2c_bus->rst))
+ return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset ctrl\n");
+
+ reset_control_deassert(i2c_bus->rst);
+
+ i2c_bus->global_regs =
+ syscon_regmap_lookup_by_phandle(dev_of_node(dev), "aspeed,global-regs");
+ if (IS_ERR(i2c_bus->global_regs))
+ return PTR_ERR(i2c_bus->global_regs);
+
+ regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
+ if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
+ regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL, AST2600_GLOBAL_INIT);
+ regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, I2CCG_DIV_CTRL);
+ }
+
+ i2c_bus->dev = dev;
+ i2c_bus->mode = BUFF_MODE;
+
+ if (device_property_read_bool(dev, "aspeed,enable-dma"))
+ i2c_bus->mode = DMA_MODE;
+
+ if (i2c_bus->mode == BUFF_MODE) {
+ i2c_bus->buf_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+ if (IS_ERR(i2c_bus->buf_base))
+ i2c_bus->mode = BYTE_MODE;
+ else
+ i2c_bus->buf_size = resource_size(res) / 2;
+ }
+
+ /*
+ * i2c timeout counter: use base clk4 1Mhz,
+ * per unit: 1/(1000/4096) = 4096us
+ */
+ ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us", &i2c_bus->timeout);
+ if (!ret)
+ i2c_bus->timeout /= 4096;
+
+ init_completion(&i2c_bus->cmd_complete);
+
+ i2c_bus->irq = platform_get_irq(pdev, 0);
+ if (i2c_bus->irq < 0)
+ return i2c_bus->irq;
+
+ platform_set_drvdata(pdev, i2c_bus);
+
+ i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
+ if (IS_ERR(i2c_bus->clk))
+ return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't get clock\n");
+
+ i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
+
+ i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
+
+ /* Initialize the I2C adapter */
+ i2c_bus->adap.owner = THIS_MODULE;
+ i2c_bus->adap.algo = &i2c_ast2600_algorithm;
+ i2c_bus->adap.retries = 0;
+ i2c_bus->adap.dev.parent = i2c_bus->dev;
+ device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
+ i2c_bus->adap.algo_data = i2c_bus;
+ strscpy(i2c_bus->adap.name, pdev->name);
+ i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
+
+ ast2600_i2c_init(i2c_bus);
+
+ ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
+ dev_name(dev), i2c_bus);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Unable to request irq %d\n", i2c_bus->irq);
+
+ writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
+ i2c_bus->reg_base + AST2600_I2CM_IER);
+
+ ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void ast2600_i2c_remove(struct platform_device *pdev)
+{
+ struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
+
+ /* Disable everything. */
+ writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ writel(0, i2c_bus->reg_base + AST2600_I2CM_IER);
+}
+
+static const struct of_device_id ast2600_i2c_bus_of_table[] = {
+ {
+ .compatible = "aspeed,ast2600-i2cv2",
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
+
+static struct platform_driver ast2600_i2c_bus_driver = {
+ .probe = ast2600_i2c_probe,
+ .remove = ast2600_i2c_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = ast2600_i2c_bus_of_table,
+ },
+};
+
+module_platform_driver(ast2600_i2c_bus_driver);
+
+MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
+MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v15 3/3] i2c: aspeed: support AST2600 i2c new register target mode driver
2024-10-07 3:52 [PATCH v15 0/3] Add ASPEED AST2600 I2Cv2 controller driver Ryan Chen
2024-10-07 3:52 ` [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Ryan Chen
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
@ 2024-10-07 3:52 ` Ryan Chen
2 siblings, 0 replies; 15+ messages in thread
From: Ryan Chen @ 2024-10-07 3:52 UTC (permalink / raw)
To: brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt, conor+dt,
andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
ryan_chen
This patch is for i2c new register target mode driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/i2c/busses/i2c-ast2600.c | 561 +++++++++++++++++++++++++++++--
1 file changed, 541 insertions(+), 20 deletions(-)
diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2600.c
index 17ba0ee77c27..6e9fcb1ebade 100644
--- a/drivers/i2c/busses/i2c-ast2600.c
+++ b/drivers/i2c/busses/i2c-ast2600.c
@@ -255,7 +255,7 @@ struct ast2600_i2c_bus {
struct i2c_timings timing_info;
struct completion cmd_complete;
struct i2c_msg *msgs;
- u8 *controller_dma_safe_buf;
+ u8 *dma_safe_buf;
dma_addr_t controller_dma_addr;
u32 apb_clk;
u32 timeout;
@@ -271,6 +271,13 @@ struct ast2600_i2c_bus {
/* Buffer mode */
void __iomem *buf_base;
struct i2c_smbus_alert_setup alert_data;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ /* target structure */
+ int target_operate;
+ unsigned char *target_dma_buf;
+ dma_addr_t target_dma_addr;
+ struct i2c_client *target;
+#endif
};
static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
@@ -361,6 +368,388 @@ static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus)
return ret;
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+static void ast2600_i2c_target_packet_dma_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
+{
+ int target_rx_len = 0;
+ u32 cmd = 0;
+ u8 value;
+ int i;
+
+ sts &= ~(AST2600_I2CS_SLAVE_PENDING);
+ /* Handle i2c target timeout condition */
+ if (AST2600_I2CS_INACTIVE_TO & sts) {
+ cmd = TARGET_TRIGGER_CMD;
+ cmd |= AST2600_I2CS_RX_DMA_EN;
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ return;
+ }
+
+ sts &= ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR);
+
+ switch (sts) {
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+ target_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CS_DMA_LEN_STS));
+ for (i = 0; i < target_rx_len; i++) {
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED,
+ &i2c_bus->target_dma_buf[i]);
+ }
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE_NAK |
+ AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA |
+ AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_RX_DONE_NAK | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_STOP:
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ if (sts & AST2600_I2CS_SLAVE_MATCH)
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+
+ target_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CS_DMA_LEN_STS));
+ for (i = 0; i < target_rx_len; i++) {
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED,
+ &i2c_bus->target_dma_buf[i]);
+ }
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ if (sts & AST2600_I2CS_STOP)
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+ break;
+
+ /* it is Mw data Mr coming -> it need send tx */
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+ /* it should be repeat start read */
+ if (sts & AST2600_I2CS_SLAVE_MATCH)
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+
+ target_rx_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CS_DMA_LEN_STS));
+ for (i = 0; i < target_rx_len; i++) {
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED,
+ &i2c_bus->target_dma_buf[i]);
+ }
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_REQUESTED,
+ &i2c_bus->target_dma_buf[0]);
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+ writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_TX_DMA:
+ /* First Start read */
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_REQUESTED,
+ &i2c_bus->target_dma_buf[0]);
+ writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+ break;
+ case AST2600_I2CS_WAIT_TX_DMA:
+ /* it should be next start read */
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_PROCESSED,
+ &i2c_bus->target_dma_buf[0]);
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+ writel(AST2600_I2CS_SET_TX_DMA_LEN(1),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN;
+ break;
+ case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP:
+ /* it just tx complete */
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS);
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN;
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+ cmd = 0;
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+ break;
+ case AST2600_I2CS_STOP:
+ cmd = 0;
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ break;
+ default:
+ dev_dbg(i2c_bus->dev, "unhandled target isr case %x, sts %x\n", sts,
+ readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+ break;
+ }
+
+ if (cmd)
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR);
+ readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+}
+
+static void ast2600_i2c_target_packet_buff_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
+{
+ int target_rx_len = 0;
+ u32 cmd = 0;
+ u8 value;
+ int i;
+
+ /* due to controller target is common buffer, need force the master stop not issue */
+ if (readl(i2c_bus->reg_base + AST2600_I2CM_CMD_STS) & GENMASK(15, 0)) {
+ writel(0, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
+ i2c_bus->cmd_err = -EBUSY;
+ writel(0, i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ complete(&i2c_bus->cmd_complete);
+ }
+
+ /* Handle i2c target timeout condition */
+ if (AST2600_I2CS_INACTIVE_TO & sts) {
+ writel(TARGET_TRIGGER_CMD, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ i2c_bus->target_operate = 0;
+ return;
+ }
+
+ sts &= ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR);
+
+ if (sts & AST2600_I2CS_SLAVE_MATCH)
+ i2c_bus->target_operate = 1;
+
+ switch (sts) {
+ case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_WAIT_RX_DMA |
+ AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_SLAVE_PENDING |
+ AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ case AST2600_I2CS_SLAVE_PENDING |
+ AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ fallthrough;
+ case AST2600_I2CS_SLAVE_PENDING |
+ AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+ case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+ case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+ cmd = TARGET_TRIGGER_CMD;
+ if (sts & AST2600_I2CS_RX_DONE) {
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ }
+ if (readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS) & AST2600_I2CS_RX_BUFF_EN)
+ cmd = 0;
+ else
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_BUFF_EN;
+
+ writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ break;
+ case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_RX_DONE:
+ cmd = TARGET_TRIGGER_CMD;
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ cmd |= AST2600_I2CS_RX_BUFF_EN;
+ writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ break;
+ case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_WAIT_RX_DMA |
+ AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ cmd = TARGET_TRIGGER_CMD;
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ cmd |= AST2600_I2CS_RX_BUFF_EN;
+ writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ break;
+ case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ cmd = TARGET_TRIGGER_CMD;
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ /* workaround for avoid next start with len != 0 */
+ writel(BIT(0), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ break;
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP:
+ cmd = TARGET_TRIGGER_CMD;
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ /* workaround for avoid next start with len != 0 */
+ writel(BIT(0), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ break;
+ case AST2600_I2CS_WAIT_TX_DMA | AST2600_I2CS_SLAVE_MATCH:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_REQUESTED, &value);
+ writeb(value, i2c_bus->buf_base);
+ writel(AST2600_I2CC_SET_TX_BUF_LEN(1),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_TX_BUFF_EN;
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_TX_DMA | AST2600_I2CS_RX_DONE:
+ case AST2600_I2CS_WAIT_TX_DMA | AST2600_I2CS_RX_DONE:
+ case AST2600_I2CS_WAIT_TX_DMA:
+ if (sts & AST2600_I2CS_SLAVE_MATCH)
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+
+ if (sts & AST2600_I2CS_RX_DONE) {
+ target_rx_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
+ AST2600_I2CC_BUFF_CTRL));
+ for (i = 0; i < target_rx_len; i++) {
+ value = readb(i2c_bus->buf_base + 0x10 + i);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &value);
+ }
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_REQUESTED, &value);
+ } else {
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_PROCESSED, &value);
+ }
+ writeb(value, i2c_bus->buf_base);
+ writel(AST2600_I2CC_SET_TX_BUF_LEN(1),
+ i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_TX_BUFF_EN;
+ break;
+ /* workaround : trigger the cmd twice to fix next state keep 1000000 */
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+ cmd = TARGET_TRIGGER_CMD | AST2600_I2CS_RX_BUFF_EN;
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ break;
+
+ case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP:
+ case AST2600_I2CS_STOP:
+ cmd = TARGET_TRIGGER_CMD;
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ break;
+ default:
+ dev_dbg(i2c_bus->dev, "unhandled target isr case %x, sts %x\n", sts,
+ readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
+ break;
+ }
+
+ if (cmd)
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR);
+ readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+
+ if ((sts & AST2600_I2CS_STOP) && !(sts & AST2600_I2CS_SLAVE_PENDING))
+ i2c_bus->target_operate = 0;
+}
+
+static void ast2600_i2c_target_byte_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
+{
+ u32 i2c_buff = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ u32 cmd = AST2600_I2CS_ACTIVE_ALL;
+ u8 byte_data;
+ u8 value;
+
+ switch (sts) {
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_REQUESTED, &value);
+ /* first address match is address */
+ byte_data = AST2600_I2CC_GET_RX_BUFF(i2c_buff);
+ break;
+ case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA:
+ byte_data = AST2600_I2CC_GET_RX_BUFF(i2c_buff);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_WRITE_RECEIVED, &byte_data);
+ break;
+ case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA:
+ cmd |= AST2600_I2CS_TX_CMD;
+ byte_data = AST2600_I2CC_GET_RX_BUFF(i2c_buff);
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_REQUESTED, &byte_data);
+ writel(byte_data, i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ break;
+ case AST2600_I2CS_TX_ACK | AST2600_I2CS_WAIT_TX_DMA:
+ cmd |= AST2600_I2CS_TX_CMD;
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_READ_PROCESSED, &byte_data);
+ writel(byte_data, i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
+ break;
+ case AST2600_I2CS_STOP:
+ case AST2600_I2CS_STOP | AST2600_I2CS_TX_NAK:
+ i2c_slave_event(i2c_bus->target, I2C_SLAVE_STOP, &value);
+ break;
+ default:
+ dev_dbg(i2c_bus->dev, "unhandled pkt isr %x\n", sts);
+ break;
+ }
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(sts, i2c_bus->reg_base + AST2600_I2CS_ISR);
+ readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+}
+
+static int ast2600_i2c_target_irq(struct ast2600_i2c_bus *i2c_bus)
+{
+ u32 ier = readl(i2c_bus->reg_base + AST2600_I2CS_IER);
+ u32 isr = readl(i2c_bus->reg_base + AST2600_I2CS_ISR);
+
+ if (!(isr & ier))
+ return 0;
+
+ /*
+ * Target interrupt coming after Master package done
+ * So need handle master first.
+ */
+ if (readl(i2c_bus->reg_base + AST2600_I2CM_ISR) & AST2600_I2CM_PKT_DONE)
+ return 0;
+
+ isr &= ~(AST2600_I2CS_ADDR_INDICATE_MASK);
+
+ if (AST2600_I2CS_ADDR1_NAK & isr)
+ isr &= ~AST2600_I2CS_ADDR1_NAK;
+
+ if (AST2600_I2CS_ADDR2_NAK & isr)
+ isr &= ~AST2600_I2CS_ADDR2_NAK;
+
+ if (AST2600_I2CS_ADDR3_NAK & isr)
+ isr &= ~AST2600_I2CS_ADDR3_NAK;
+
+ if (AST2600_I2CS_ADDR_MASK & isr)
+ isr &= ~AST2600_I2CS_ADDR_MASK;
+
+ if (AST2600_I2CS_PKT_DONE & isr) {
+ if (i2c_bus->mode == DMA_MODE)
+ ast2600_i2c_target_packet_dma_irq(i2c_bus, isr);
+ else
+ ast2600_i2c_target_packet_buff_irq(i2c_bus, isr);
+ } else {
+ ast2600_i2c_target_byte_irq(i2c_bus, isr);
+ }
+
+ return 1;
+}
+#endif
+
static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
{
struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
@@ -376,16 +765,16 @@ static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
if (cmd & AST2600_I2CM_START_CMD) {
cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
- i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
- if (!i2c_bus->controller_dma_safe_buf)
+ i2c_bus->dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
+ if (!i2c_bus->dma_safe_buf)
return -ENOMEM;
i2c_bus->controller_dma_addr =
- dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
+ dma_map_single(i2c_bus->dev, i2c_bus->dma_safe_buf,
msg->len, DMA_TO_DEVICE);
ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
if (ret) {
- i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
- i2c_bus->controller_dma_safe_buf = NULL;
+ i2c_put_dma_safe_msg_buf(i2c_bus->dma_safe_buf, msg, false);
+ i2c_bus->dma_safe_buf = NULL;
return ret;
}
}
@@ -502,16 +891,15 @@ static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
cmd |= CONTROLLER_TRIGGER_LAST_STOP;
}
writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
- i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
- if (!i2c_bus->controller_dma_safe_buf)
+ i2c_bus->dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
+ if (!i2c_bus->dma_safe_buf)
return -ENOMEM;
i2c_bus->controller_dma_addr =
- dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
- msg->len, DMA_FROM_DEVICE);
+ dma_map_single(i2c_bus->dev, i2c_bus->dma_safe_buf, msg->len, DMA_FROM_DEVICE);
ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
if (ret) {
- i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
- i2c_bus->controller_dma_safe_buf = NULL;
+ i2c_put_dma_safe_msg_buf(i2c_bus->dma_safe_buf, msg, false);
+ i2c_bus->dma_safe_buf = NULL;
return ret;
}
writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
@@ -659,9 +1047,8 @@ static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus,
if (i2c_bus->mode == DMA_MODE) {
dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
msg->len, DMA_TO_DEVICE);
- i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
- msg, true);
- i2c_bus->controller_dma_safe_buf = NULL;
+ i2c_put_dma_safe_msg_buf(i2c_bus->dma_safe_buf, msg, true);
+ i2c_bus->dma_safe_buf = NULL;
}
i2c_bus->msgs_index++;
if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
@@ -683,6 +1070,20 @@ static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus,
}
break;
case AST2600_I2CM_RX_DONE:
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ /*
+ * Workaround for controller/target package mode enable rx done stuck issue
+ * When master go for first read (RX_DONE), target mode will also effect
+ * Then controller will send nack, not operate anymore.
+ */
+ if (readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS) & AST2600_I2CS_PKT_MODE_EN) {
+ u32 target_cmd = readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ writel(target_cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ }
+ fallthrough;
+#endif
case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
/* do next rx */
if (i2c_bus->mode == DMA_MODE) {
@@ -712,9 +1113,8 @@ static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus,
if (i2c_bus->mode == DMA_MODE) {
dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
msg->len, DMA_FROM_DEVICE);
- i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
- msg, true);
- i2c_bus->controller_dma_safe_buf = NULL;
+ i2c_put_dma_safe_msg_buf(i2c_bus->dma_safe_buf, msg, true);
+ i2c_bus->dma_safe_buf = NULL;
}
i2c_bus->msgs_index++;
@@ -812,6 +1212,12 @@ static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id)
{
struct ast2600_i2c_bus *i2c_bus = dev_id;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) & AST2600_I2CC_SLAVE_EN) {
+ if (ast2600_i2c_target_irq(i2c_bus))
+ return IRQ_HANDLED;
+ }
+#endif
return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
}
@@ -828,12 +1234,30 @@ static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg
return ret;
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (i2c_bus->mode == BUFF_MODE) {
+ if (i2c_bus->target_operate)
+ return -EBUSY;
+ /* disable target isr */
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_IER);
+ if (readl(i2c_bus->reg_base + AST2600_I2CS_ISR) || i2c_bus->target_operate) {
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER);
+ return -EBUSY;
+ }
+ }
+#endif
+
i2c_bus->cmd_err = 0;
i2c_bus->msgs = msgs;
i2c_bus->msgs_index = 0;
i2c_bus->msgs_count = num;
reinit_completion(&i2c_bus->cmd_complete);
ret = ast2600_i2c_do_start(i2c_bus);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ /* avoid race condication target is wait and master wait 1st target operate */
+ if (i2c_bus->mode == BUFF_MODE)
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER);
+#endif
if (ret)
goto controller_out;
timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
@@ -845,7 +1269,26 @@ static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg
readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (ctrl & AST2600_I2CC_SLAVE_EN) {
+ u32 cmd = TARGET_TRIGGER_CMD;
+ if (i2c_bus->mode == DMA_MODE) {
+ cmd |= AST2600_I2CS_RX_DMA_EN;
+ writel(i2c_bus->target_dma_addr,
+ i2c_bus->reg_base + AST2600_I2CS_RX_DMA);
+ writel(i2c_bus->target_dma_addr,
+ i2c_bus->reg_base + AST2600_I2CS_TX_DMA);
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ } else if (i2c_bus->mode == BUFF_MODE) {
+ cmd = TARGET_TRIGGER_CMD;
+ } else {
+ cmd &= ~AST2600_I2CS_PKT_MODE_EN;
+ }
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ }
+#endif
if (i2c_bus->multi_master &&
(readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
AST2600_I2CC_BUS_BUSY_STS))
@@ -860,8 +1303,8 @@ static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg
controller_out:
if (i2c_bus->mode == DMA_MODE) {
- kfree(i2c_bus->controller_dma_safe_buf);
- i2c_bus->controller_dma_safe_buf = NULL;
+ kfree(i2c_bus->dma_safe_buf);
+ i2c_bus->dma_safe_buf = NULL;
}
return ret;
@@ -889,7 +1332,78 @@ static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus)
/* Clear Interrupt */
writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR);
+
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ /* for memory buffer initial */
+ if (i2c_bus->mode == DMA_MODE) {
+ i2c_bus->target_dma_buf =
+ dmam_alloc_coherent(i2c_bus->dev, I2C_TARGET_MSG_BUF_SIZE,
+ &i2c_bus->target_dma_addr, GFP_KERNEL);
+ if (!i2c_bus->target_dma_buf)
+ return;
+ }
+
+ writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CS_ISR);
+
+ if (i2c_bus->mode == BYTE_MODE)
+ writel(GENMASK(15, 0), i2c_bus->reg_base + AST2600_I2CS_IER);
+ else
+ writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER);
+#endif
+}
+
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+static int ast2600_i2c_reg_target(struct i2c_client *client)
+{
+ struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(client->adapter);
+ u32 cmd = TARGET_TRIGGER_CMD;
+
+ if (i2c_bus->target)
+ return -EINVAL;
+
+ dev_dbg(i2c_bus->dev, "target addr %x\n", client->addr);
+
+ writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
+ writel(AST2600_I2CC_SLAVE_EN | readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL),
+ i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+
+ /* trigger rx buffer */
+ if (i2c_bus->mode == DMA_MODE) {
+ cmd |= AST2600_I2CS_RX_DMA_EN;
+ writel(i2c_bus->target_dma_addr, i2c_bus->reg_base + AST2600_I2CS_RX_DMA);
+ writel(i2c_bus->target_dma_addr, i2c_bus->reg_base + AST2600_I2CS_TX_DMA);
+ writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_TARGET_MSG_BUF_SIZE),
+ i2c_bus->reg_base + AST2600_I2CS_DMA_LEN);
+ } else if (i2c_bus->mode == BUFF_MODE) {
+ cmd = TARGET_TRIGGER_CMD;
+ } else {
+ cmd &= ~AST2600_I2CS_PKT_MODE_EN;
+ }
+
+ writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS);
+ i2c_bus->target = client;
+ /* Set target addr. */
+ writel(client->addr | AST2600_I2CS_ADDR1_ENABLE,
+ i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
+
+ return 0;
+}
+
+static int ast2600_i2c_unreg_target(struct i2c_client *client)
+{
+ struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(client->adapter);
+
+ /* Turn off target mode. */
+ writel(~AST2600_I2CC_SLAVE_EN & readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL),
+ i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
+ writel(readl(i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL) & ~AST2600_I2CS_ADDR1_MASK,
+ i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
+
+ i2c_bus->target = NULL;
+
+ return 0;
}
+#endif
static u32 ast2600_i2c_functionality(struct i2c_adapter *adap)
{
@@ -899,6 +1413,10 @@ static u32 ast2600_i2c_functionality(struct i2c_adapter *adap)
static const struct i2c_algorithm i2c_ast2600_algorithm = {
.xfer = ast2600_i2c_controller_xfer,
.functionality = ast2600_i2c_functionality,
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ .reg_target = ast2600_i2c_reg_target,
+ .unreg_target = ast2600_i2c_unreg_target,
+#endif
};
static int ast2600_i2c_probe(struct platform_device *pdev)
@@ -934,6 +1452,9 @@ static int ast2600_i2c_probe(struct platform_device *pdev)
regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, I2CCG_DIV_CTRL);
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ i2c_bus->target_operate = 0;
+#endif
i2c_bus->dev = dev;
i2c_bus->mode = BUFF_MODE;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
@ 2024-11-11 11:00 ` Naresh Solanki
2024-11-12 7:00 ` Ryan Chen
2024-11-12 4:54 ` Yikai Tsai
2024-11-12 10:22 ` Philipp Zabel
2 siblings, 1 reply; 15+ messages in thread
From: Naresh Solanki @ 2024-11-11 11:00 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt,
conor+dt, andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
Hi Ryan,
I've tested the driver changes in my machine
based on "SOC: AST2600-A3".
I faced some issue testing the driver.
While the driver functions correctly in
Normal mode, I encountered issues when attempting
to run it in DMA and BUFF modes. Given the
instability in these modes, I suspect there may
be misconfigurations in my device tree setup.
Could you please provide a sample configuration for
the device tree that would ensure stable operation
of the driver in both DMA and BUFF modes?
Thank you for your support.
Regards,
Naresh
On 07-10-2024 09:22:34, Ryan Chen wrote:
> Add i2c new register mode driver to support AST2600 i2c
> new register mode. AST2600 i2c controller have legacy and
> new register mode. The new register mode have global register
> support 4 base clock for scl clock selection, and new clock
> divider mode. The new register mode have separate register
> set to control i2c controller and target. This patch is for i2c
> controller mode driver.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
> drivers/i2c/busses/Kconfig | 11 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-ast2600.c | 1032 ++++++++++++++++++++++++++++++
> 3 files changed, 1044 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-ast2600.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index a22f9125322a..abfb027350d4 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -410,6 +410,17 @@ config I2C_ALTERA
> This driver can also be built as a module. If so, the module
> will be called i2c-altera.
>
> +config I2C_AST2600
> + tristate "Aspeed I2C v2 Controller"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + select I2C_SMBUS
> + help
> + If you say yes to this option, support will be included for the
> + Aspeed I2C controller with new register set.
> +
> + This driver can also be built as a module. If so, the module
> + will be called i2c-ast2600.
> +
> config I2C_ASPEED
> tristate "Aspeed I2C Controller"
> depends on ARCH_ASPEED || COMPILE_TEST
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 78d0561339e5..5665b60b1566 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
> obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
> obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o
> obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
> +obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
> obj-$(CONFIG_I2C_AT91) += i2c-at91.o
> i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
> ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
> diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2600.c
> new file mode 100644
> index 000000000000..17ba0ee77c27
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-ast2600.c
> @@ -0,0 +1,1032 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * ASPEED AST2600 new register set I2C controller driver
> + *
> + * Copyright (C) ASPEED Technology Inc.
> + */
> +#include <asm/unaligned.h>
> +#include <linux/array_size.h>
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/i2c-smbus.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/minmax.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/string_helpers.h>
> +
> +#define AST2600_I2CG_ISR 0x00
> +#define AST2600_I2CG_SLAVE_ISR 0x04
> +#define AST2600_I2CG_OWNER 0x08
> +#define AST2600_I2CG_CTRL 0x0C
> +#define AST2600_I2CG_CLK_DIV_CTRL 0x10
> +
> +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
> +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
> +#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
> +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
> +#define AST2600_GLOBAL_INIT \
> + (AST2600_I2CG_CTRL_NEW_REG | AST2600_I2CG_CTRL_NEW_CLK_DIV)
> +/*
> + * APB clk : 100Mhz
> + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
> + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6)
> + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
> + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
> + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
> + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
> + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
> + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
> + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
> + * 0x12 : 400Khz : 10Mhz : 1.6us
> + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
> + * 0x08 : 1Mhz : 20Mhz : 0.8us
> + */
> +#define I2CCG_DIV_CTRL 0xC6411208
> +
> +/* 0x00 : I2CC Controller/Target Function Control Register */
> +#define AST2600_I2CC_FUN_CTRL 0x00
> +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
> +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
> +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0)) << 18)
> +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
> +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
> +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
> +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
> +#define AST2600_I2CC_MSB_STS BIT(9)
> +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
> +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
> +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
> +/* reserver 5 : 2 */
> +#define AST2600_I2CC_SLAVE_EN BIT(1)
> +#define AST2600_I2CC_MASTER_EN BIT(0)
> +
> +/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
> +#define AST2600_I2CC_AC_TIMING 0x04
> +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0)) << 24)
> +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0)) << 20)
> +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
> +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
> +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
> +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1, 0)) << 8)
> +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
> +
> +/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
> +#define AST2600_I2CC_STS_AND_BUFF 0x08
> +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
> +#define AST2600_I2CC_SDA_OE BIT(28)
> +#define AST2600_I2CC_SDA_O BIT(27)
> +#define AST2600_I2CC_SCL_OE BIT(26)
> +#define AST2600_I2CC_SCL_O BIT(25)
> +
> +#define AST2600_I2CC_SCL_LINE_STS BIT(18)
> +#define AST2600_I2CC_SDA_LINE_STS BIT(17)
> +#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
> +
> +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) & GENMASK(7, 0))
> +
> +/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
> +#define AST2600_I2CC_BUFF_CTRL 0x0C
> +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29, 24)) >> 24)
> +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 16) | BIT(0))
> +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 8) | BIT(0))
> +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12, 8)) >> 8) + 1)
> +
> +/* 0x10 : I2CM Controller Interrupt Control Register */
> +#define AST2600_I2CM_IER 0x10
> +/* 0x14 : I2CM Controller Interrupt Status Register : WC */
> +#define AST2600_I2CM_ISR 0x14
> +
> +#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
> +#define AST2600_I2CM_PKT_ERROR BIT(17)
> +#define AST2600_I2CM_PKT_DONE BIT(16)
> +
> +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
> +#define AST2600_I2CM_SDA_DL_TO BIT(14)
> +#define AST2600_I2CM_BUS_RECOVER BIT(13)
> +#define AST2600_I2CM_SMBUS_ALT BIT(12)
> +
> +#define AST2600_I2CM_SCL_LOW_TO BIT(6)
> +#define AST2600_I2CM_ABNORMAL BIT(5)
> +#define AST2600_I2CM_NORMAL_STOP BIT(4)
> +#define AST2600_I2CM_ARBIT_LOSS BIT(3)
> +#define AST2600_I2CM_RX_DONE BIT(2)
> +#define AST2600_I2CM_TX_NAK BIT(1)
> +#define AST2600_I2CM_TX_ACK BIT(0)
> +
> +/* 0x18 : I2CM Controller Command/Status Register */
> +#define AST2600_I2CM_CMD_STS 0x18
> +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0)) << 24)
> +#define AST2600_I2CM_PKT_EN BIT(16)
> +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
> +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
> +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
> +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
> +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
> +
> +#define AST2600_I2CM_RX_DMA_EN BIT(9)
> +#define AST2600_I2CM_TX_DMA_EN BIT(8)
> +/* Command Bit */
> +#define AST2600_I2CM_RX_BUFF_EN BIT(7)
> +#define AST2600_I2CM_TX_BUFF_EN BIT(6)
> +#define AST2600_I2CM_STOP_CMD BIT(5)
> +#define AST2600_I2CM_RX_CMD_LAST BIT(4)
> +#define AST2600_I2CM_RX_CMD BIT(3)
> +
> +#define AST2600_I2CM_TX_CMD BIT(1)
> +#define AST2600_I2CM_START_CMD BIT(0)
> +
> +/* 0x1C : I2CM Controller DMA Transfer Length Register */
> +#define AST2600_I2CM_DMA_LEN 0x1C
> +/* Tx Rx support length 1 ~ 4096 */
> +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0)) << 16) | BIT(31))
> +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0)) | BIT(15))
> +
> +/* 0x20 : I2CS Target Interrupt Control Register */
> +#define AST2600_I2CS_IER 0x20
> +/* 0x24 : I2CS Target Interrupt Status Register */
> +#define AST2600_I2CS_ISR 0x24
> +
> +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
> +#define AST2600_I2CS_SLAVE_PENDING BIT(29)
> +
> +#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
> +#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
> +
> +#define AST2600_I2CS_ADDR3_NAK BIT(22)
> +#define AST2600_I2CS_ADDR2_NAK BIT(21)
> +#define AST2600_I2CS_ADDR1_NAK BIT(20)
> +
> +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
> +#define AST2600_I2CS_PKT_ERROR BIT(17)
> +#define AST2600_I2CS_PKT_DONE BIT(16)
> +#define AST2600_I2CS_INACTIVE_TO BIT(15)
> +
> +#define AST2600_I2CS_SLAVE_MATCH BIT(7)
> +#define AST2600_I2CS_ABNOR_STOP BIT(5)
> +#define AST2600_I2CS_STOP BIT(4)
> +#define AST2600_I2CS_RX_DONE_NAK BIT(3)
> +#define AST2600_I2CS_RX_DONE BIT(2)
> +#define AST2600_I2CS_TX_NAK BIT(1)
> +#define AST2600_I2CS_TX_ACK BIT(0)
> +
> +/* 0x28 : I2CS Target CMD/Status Register */
> +#define AST2600_I2CS_CMD_STS 0x28
> +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
> +#define AST2600_I2CS_PKT_MODE_EN BIT(16)
> +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
> +#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
> +
> +#define AST2600_I2CS_ALT_EN BIT(10)
> +#define AST2600_I2CS_RX_DMA_EN BIT(9)
> +#define AST2600_I2CS_TX_DMA_EN BIT(8)
> +#define AST2600_I2CS_RX_BUFF_EN BIT(7)
> +#define AST2600_I2CS_TX_BUFF_EN BIT(6)
> +#define AST2600_I2CS_RX_CMD_LAST BIT(4)
> +
> +#define AST2600_I2CS_TX_CMD BIT(2)
> +
> +#define AST2600_I2CS_DMA_LEN 0x2C
> +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0)) << 16) | BIT(31))
> +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0)) | BIT(15))
> +
> +/* I2CM Controller DMA Tx Buffer Register */
> +#define AST2600_I2CM_TX_DMA 0x30
> +/* I2CM Controller DMA Rx Buffer Register */
> +#define AST2600_I2CM_RX_DMA 0x34
> +/* I2CS Target DMA Tx Buffer Register */
> +#define AST2600_I2CS_TX_DMA 0x38
> +/* I2CS Target DMA Rx Buffer Register */
> +#define AST2600_I2CS_RX_DMA 0x3C
> +
> +#define AST2600_I2CS_ADDR_CTRL 0x40
> +
> +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
> +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
> +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
> +
> +#define AST2600_I2CM_DMA_LEN_STS 0x48
> +#define AST2600_I2CS_DMA_LEN_STS 0x4C
> +
> +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
> +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28, 16)) >> 16)
> +
> +/* 0x40 : Target Device Address Register */
> +#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
> +#define AST2600_I2CS_ADDR3(x) ((x) << 16)
> +#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
> +#define AST2600_I2CS_ADDR2(x) ((x) << 8)
> +#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
> +#define AST2600_I2CS_ADDR1(x) (x)
> +
> +#define I2C_TARGET_MSG_BUF_SIZE 256
> +
> +#define AST2600_I2C_DMA_SIZE 4096
> +
> +#define CONTROLLER_TRIGGER_LAST_STOP (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
> +#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL | AST2600_I2CS_PKT_MODE_EN)
> +
> +#define AST_I2C_TIMEOUT_CLK 0x2
> +
> +enum xfer_mode {
> + BYTE_MODE,
> + BUFF_MODE,
> + DMA_MODE,
> +};
> +
> +struct ast2600_i2c_bus {
> + struct i2c_adapter adap;
> + struct device *dev;
> + void __iomem *reg_base;
> + struct regmap *global_regs;
> + struct reset_control *rst;
> + struct clk *clk;
> + struct i2c_timings timing_info;
> + struct completion cmd_complete;
> + struct i2c_msg *msgs;
> + u8 *controller_dma_safe_buf;
> + dma_addr_t controller_dma_addr;
> + u32 apb_clk;
> + u32 timeout;
> + int irq;
> + int cmd_err;
> + int msgs_index;
> + int msgs_count;
> + int controller_xfer_cnt;
> + size_t buf_index;
> + size_t buf_size;
> + enum xfer_mode mode;
> + bool multi_master;
> + /* Buffer mode */
> + void __iomem *buf_base;
> + struct i2c_smbus_alert_setup alert_data;
> +};
> +
> +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
> +{
> + unsigned long base_clk[16];
> + int baseclk_idx = 0;
> + int divisor = 0;
> + u32 clk_div_reg;
> + u32 scl_low;
> + u32 scl_high;
> + u32 data;
> +
> + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, &clk_div_reg);
> +
> + for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
> + if (i == 0)
> + base_clk[i] = i2c_bus->apb_clk;
> + else if (i < 5)
> + base_clk[i] = (i2c_bus->apb_clk * 2) /
> + (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
> + else
> + base_clk[i] = base_clk[4] >> (i - 5);
> +
> + if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
> + baseclk_idx = i;
> + divisor = DIV_ROUND_UP(base_clk[i], i2c_bus->timing_info.bus_freq_hz);
> + break;
> + }
> + }
> + baseclk_idx = min(baseclk_idx, 15);
> + divisor = min(divisor, 32);
> + scl_low = min(divisor * 9 / 16 - 1, 15);
> + scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
> + data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
> + if (i2c_bus->timeout) {
> + data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
> + data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
> + }
> +
> + return data;
> +}
> +
> +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus)
> +{
> + u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + int ret = 0;
> + u32 ctrl;
> + int r;
> +
> + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n", i2c_bus->adap.nr, state);
> +
> + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + /* Disable controller */
> + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
> + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) | AST2600_I2CC_MASTER_EN,
> + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + reinit_completion(&i2c_bus->cmd_complete);
> + i2c_bus->cmd_err = 0;
> +
> + /* Check 0x14's SDA and SCL status */
> + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state & AST2600_I2CC_SCL_LINE_STS)) {
> + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> + r = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
> + if (r == 0) {
> + dev_dbg(i2c_bus->dev, "recovery timed out\n");
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + return -ETIMEDOUT;
> + } else if (i2c_bus->cmd_err) {
> + dev_dbg(i2c_bus->dev, "recovery error\n");
> + ret = -EPROTO;
> + }
> + }
> +
> + /* Recovery done */
> + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + if (state & AST2600_I2CC_BUS_BUSY_STS) {
> + dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
> + ret = -EPROTO;
> + }
> +
> + /* restore original controller setting */
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + return ret;
> +}
> +
> +static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + int ret;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > AST2600_I2C_DMA_SIZE)
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (cmd & AST2600_I2CM_START_CMD) {
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
> + if (!i2c_bus->controller_dma_safe_buf)
> + return -ENOMEM;
> + i2c_bus->controller_dma_addr =
> + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> + msg->len, DMA_TO_DEVICE);
> + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> + if (ret) {
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + return ret;
> + }
> + }
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
> + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
> + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
> + i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 wbuf_dword;
> + int xfer_len;
> + int i;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > i2c_bus->buf_size)
> + xfer_len = i2c_bus->buf_size;
> + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (cmd & AST2600_I2CM_START_CMD)
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
> + /*
> + * The controller's buffer register supports dword writes only.
> + * Therefore, write dwords to the buffer register in a 4-byte aligned,
> + * and write the remaining unaligned data at the end.
> + */
> + for (i = 0; i < xfer_len; i += 4) {
> + int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
> +
> + switch (min(xfer_len - i, 4) % 4) {
> + case 1:
> + wbuf_dword = msg->buf[xfer_cnt];
> + break;
> + case 2:
> + wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
> + break;
> + case 3:
> + wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
> + break;
> + default:
> + wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
> + break;
> + }
> + writel(wbuf_dword, i2c_bus->buf_base + i);
> + }
> + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
> + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> +
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> +
> + if (cmd & AST2600_I2CM_START_CMD)
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> +
> + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> + ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_CMD;
> + writel(msg->buf[i2c_bus->controller_xfer_cnt],
> + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + u32 cmd;
> + int ret;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + xfer_len = 1;
> + } else if (msg->len > AST2600_I2C_DMA_SIZE) {
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + } else {
> + xfer_len = msg->len;
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
> + if (!i2c_bus->controller_dma_safe_buf)
> + return -ENOMEM;
> + i2c_bus->controller_dma_addr =
> + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> + msg->len, DMA_FROM_DEVICE);
> + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> + if (ret) {
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + return ret;
> + }
> + writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + u32 cmd;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + dev_dbg(i2c_bus->dev, "smbus read\n");
> + xfer_len = 1;
> + } else if (msg->len > i2c_bus->buf_size) {
> + xfer_len = i2c_bus->buf_size;
> + } else {
> + xfer_len = msg->len;
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 cmd;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + dev_dbg(i2c_bus->dev, "smbus read\n");
> + } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
> + if (msg->len == 1)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> +
> + /* send start */
> + dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
> + i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
> + msg->len, str_plural(msg->len),
> + msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
> +
> + i2c_bus->controller_xfer_cnt = 0;
> + i2c_bus->buf_index = 0;
> +
> + if (msg->flags & I2C_M_RD) {
> + if (i2c_bus->mode == DMA_MODE)
> + return ast2600_i2c_setup_dma_rx(i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + return ast2600_i2c_setup_buff_rx(i2c_bus);
> + else
> + return ast2600_i2c_setup_byte_rx(i2c_bus);
> + } else {
> + if (i2c_bus->mode == DMA_MODE)
> + return ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + else
> + return ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + }
> +}
> +
> +static int ast2600_i2c_irq_err_to_errno(u32 irq_status)
> +{
> + if (irq_status & AST2600_I2CM_ARBIT_LOSS)
> + return -EAGAIN;
> + if (irq_status & (AST2600_I2CM_SDA_DL_TO | AST2600_I2CM_SCL_LOW_TO))
> + return -EBUSY;
> + if (irq_status & (AST2600_I2CM_ABNORMAL))
> + return -EPROTO;
> +
> + return 0;
> +}
> +
> +static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 cmd = AST2600_I2CM_PKT_EN;
> + int xfer_len;
> + int i;
> +
> + sts &= ~AST2600_I2CM_PKT_DONE;
> + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + switch (sts) {
> + case AST2600_I2CM_PKT_ERROR:
> + i2c_bus->cmd_err = -EAGAIN;
> + complete(&i2c_bus->cmd_complete);
> + break;
> + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for issue */
> + fallthrough;
> + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK | AST2600_I2CM_NORMAL_STOP:
> + i2c_bus->cmd_err = -ENXIO;
> + complete(&i2c_bus->cmd_complete);
> + break;
> + case AST2600_I2CM_NORMAL_STOP:
> + /* write 0 byte only have stop isr */
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + } else {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + }
> + break;
> + case AST2600_I2CM_TX_ACK:
> + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
> + if (i2c_bus->mode == DMA_MODE)
> + xfer_len = AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CM_DMA_LEN_STS));
> + else if (i2c_bus->mode == BUFF_MODE)
> + xfer_len = AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CC_BUFF_CTRL));
> + else
> + xfer_len = 1;
> +
> + i2c_bus->controller_xfer_cnt += xfer_len;
> +
> + if (i2c_bus->controller_xfer_cnt == msg->len) {
> + if (i2c_bus->mode == DMA_MODE) {
> + dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
> + msg->len, DMA_TO_DEVICE);
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> + msg, true);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + } else {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + }
> + } else {
> + if (i2c_bus->mode == DMA_MODE)
> + ast2600_i2c_setup_dma_tx(0, i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + ast2600_i2c_setup_buff_tx(0, i2c_bus);
> + else
> + ast2600_i2c_setup_byte_tx(0, i2c_bus);
> + }
> + break;
> + case AST2600_I2CM_RX_DONE:
> + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
> + /* do next rx */
> + if (i2c_bus->mode == DMA_MODE) {
> + xfer_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CM_DMA_LEN_STS));
> + } else if (i2c_bus->mode == BUFF_MODE) {
> + xfer_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CC_BUFF_CTRL));
> + for (i = 0; i < xfer_len; i++)
> + msg->buf[i2c_bus->controller_xfer_cnt + i] =
> + readb(i2c_bus->buf_base + 0x10 + i);
> + } else {
> + xfer_len = 1;
> + msg->buf[i2c_bus->controller_xfer_cnt] =
> + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
> + AST2600_I2CC_STS_AND_BUFF));
> + }
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + msg->len = min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
> + msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
> + msg->flags &= ~I2C_M_RECV_LEN;
> + }
> + i2c_bus->controller_xfer_cnt += xfer_len;
> +
> + if (i2c_bus->controller_xfer_cnt == msg->len) {
> + if (i2c_bus->mode == DMA_MODE) {
> + dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
> + msg->len, DMA_FROM_DEVICE);
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> + msg, true);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> +
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + } else {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + }
> + } else {
> + /* next rx */
> + cmd |= AST2600_I2CM_RX_CMD;
> + if (i2c_bus->mode == DMA_MODE) {
> + cmd |= AST2600_I2CM_RX_DMA_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > AST2600_I2C_DMA_SIZE) {
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + } else {
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
> + i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> + } else if (i2c_bus->mode == BUFF_MODE) {
> + cmd |= AST2600_I2CM_RX_BUFF_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > i2c_bus->buf_size) {
> + xfer_len = i2c_bus->buf_size;
> + } else {
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
> + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> + } else {
> + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> + ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + }
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> + }
> + break;
> + default:
> + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
> + break;
> + }
> +}
> +
> +static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus *i2c_bus)
> +{
> + u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
> + u32 ctrl;
> +
> + sts &= ~AST2600_I2CM_SMBUS_ALT;
> +
> + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
> + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + i2c_bus->cmd_err = -EPROTO;
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + if (AST2600_I2CM_BUS_RECOVER & sts) {
> + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + i2c_bus->cmd_err = 0;
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
> + if (i2c_bus->cmd_err) {
> + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + if (AST2600_I2CM_PKT_DONE & sts) {
> + ast2600_i2c_controller_package_irq(i2c_bus, sts);
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id)
> +{
> + struct ast2600_i2c_bus *i2c_bus = dev_id;
> +
> + return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
> +}
> +
> +static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
> +{
> + struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
> + unsigned long timeout;
> + int ret;
> +
> + if (!i2c_bus->multi_master &&
> + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_BUS_BUSY_STS)) {
> + ret = ast2600_i2c_recover_bus(i2c_bus);
> + if (ret)
> + return ret;
> + }
> +
> + i2c_bus->cmd_err = 0;
> + i2c_bus->msgs = msgs;
> + i2c_bus->msgs_index = 0;
> + i2c_bus->msgs_count = num;
> + reinit_completion(&i2c_bus->cmd_complete);
> + ret = ast2600_i2c_do_start(i2c_bus);
> + if (ret)
> + goto controller_out;
> + timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
> + if (timeout == 0) {
> + u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
> + readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
> + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + if (i2c_bus->multi_master &&
> + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> + AST2600_I2CC_BUS_BUSY_STS))
> + ast2600_i2c_recover_bus(i2c_bus);
> +
> + ret = -ETIMEDOUT;
> + } else {
> + ret = i2c_bus->cmd_err;
> + }
> +
> + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr, i2c_bus->cmd_err);
> +
> +controller_out:
> + if (i2c_bus->mode == DMA_MODE) {
> + kfree(i2c_bus->controller_dma_safe_buf);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> +
> + return ret;
> +}
> +
> +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct platform_device *pdev = to_platform_device(i2c_bus->dev);
> + u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE | AST2600_I2CC_MASTER_EN;
> +
> + /* I2C Reset */
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + i2c_bus->multi_master = device_property_read_bool(&pdev->dev, "multi-master");
> + if (!i2c_bus->multi_master)
> + fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
> +
> + /* Enable Controller Mode */
> + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + /* disable target address */
> + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
> +
> + /* Set AC Timing */
> + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base + AST2600_I2CC_AC_TIMING);
> +
> + /* Clear Interrupt */
> + writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR);
> +}
> +
> +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
> +}
> +
> +static const struct i2c_algorithm i2c_ast2600_algorithm = {
> + .xfer = ast2600_i2c_controller_xfer,
> + .functionality = ast2600_i2c_functionality,
> +};
> +
> +static int ast2600_i2c_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct ast2600_i2c_bus *i2c_bus;
> + struct resource *res;
> + u32 global_ctrl;
> + int ret;
> +
> + i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
> + if (!i2c_bus)
> + return -ENOMEM;
> +
> + i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(i2c_bus->reg_base))
> + return PTR_ERR(i2c_bus->reg_base);
> +
> + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> + if (IS_ERR(i2c_bus->rst))
> + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset ctrl\n");
> +
> + reset_control_deassert(i2c_bus->rst);
> +
> + i2c_bus->global_regs =
> + syscon_regmap_lookup_by_phandle(dev_of_node(dev), "aspeed,global-regs");
> + if (IS_ERR(i2c_bus->global_regs))
> + return PTR_ERR(i2c_bus->global_regs);
> +
> + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
> + if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
> + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL, AST2600_GLOBAL_INIT);
> + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, I2CCG_DIV_CTRL);
> + }
> +
> + i2c_bus->dev = dev;
> + i2c_bus->mode = BUFF_MODE;
> +
> + if (device_property_read_bool(dev, "aspeed,enable-dma"))
> + i2c_bus->mode = DMA_MODE;
> +
> + if (i2c_bus->mode == BUFF_MODE) {
> + i2c_bus->buf_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> + if (IS_ERR(i2c_bus->buf_base))
> + i2c_bus->mode = BYTE_MODE;
> + else
> + i2c_bus->buf_size = resource_size(res) / 2;
> + }
> +
> + /*
> + * i2c timeout counter: use base clk4 1Mhz,
> + * per unit: 1/(1000/4096) = 4096us
> + */
> + ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us", &i2c_bus->timeout);
> + if (!ret)
> + i2c_bus->timeout /= 4096;
> +
> + init_completion(&i2c_bus->cmd_complete);
> +
> + i2c_bus->irq = platform_get_irq(pdev, 0);
> + if (i2c_bus->irq < 0)
> + return i2c_bus->irq;
> +
> + platform_set_drvdata(pdev, i2c_bus);
> +
> + i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
> + if (IS_ERR(i2c_bus->clk))
> + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't get clock\n");
> +
> + i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
> +
> + i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
> +
> + /* Initialize the I2C adapter */
> + i2c_bus->adap.owner = THIS_MODULE;
> + i2c_bus->adap.algo = &i2c_ast2600_algorithm;
> + i2c_bus->adap.retries = 0;
> + i2c_bus->adap.dev.parent = i2c_bus->dev;
> + device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
> + i2c_bus->adap.algo_data = i2c_bus;
> + strscpy(i2c_bus->adap.name, pdev->name);
> + i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
> +
> + ast2600_i2c_init(i2c_bus);
> +
> + ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
> + dev_name(dev), i2c_bus);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Unable to request irq %d\n", i2c_bus->irq);
> +
> + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
> + i2c_bus->reg_base + AST2600_I2CM_IER);
> +
> + ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void ast2600_i2c_remove(struct platform_device *pdev)
> +{
> + struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
> +
> + /* Disable everything. */
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER);
> +}
> +
> +static const struct of_device_id ast2600_i2c_bus_of_table[] = {
> + {
> + .compatible = "aspeed,ast2600-i2cv2",
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
> +
> +static struct platform_driver ast2600_i2c_bus_driver = {
> + .probe = ast2600_i2c_probe,
> + .remove = ast2600_i2c_remove,
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .of_match_table = ast2600_i2c_bus_of_table,
> + },
> +};
> +
> +module_platform_driver(ast2600_i2c_bus_driver);
> +
> +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
> +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
2024-11-11 11:00 ` Naresh Solanki
@ 2024-11-12 4:54 ` Yikai Tsai
2024-11-12 6:55 ` Ryan Chen
2024-11-12 10:22 ` Philipp Zabel
2 siblings, 1 reply; 15+ messages in thread
From: Yikai Tsai @ 2024-11-12 4:54 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt,
conor+dt, andrew, p.zabel, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
Hi Ryan,
Thank you for the I2Cv2 driver, it helps us a lot.
We have the need to use byte-mode. After consulting with Aspeed, we set
the reg property in DTS to use byte-mode, for example:
&i2c13 {
status = "okay";
clock-frequency = <100000>;
multi-master;
/delete-property/ reg;
reg = <0x700 0x80>;
...
};
However, we will see "invalid resource" under dmesg.
[ 5.482254] i2c_ast2600 1e78a700.i2c: invalid resource (null)
[ 5.496110] i2c_ast2600 1e78a700.i2c: i2c [13]: adapter [100 khz]
mode [0]
According to Aspeed, i2c-13 still has byte-mode enabled despite the
occurrence of "invalid resource". However, the "invalid resource"
message doesn't clearly express what happened to it.
Could you please change this message to be presented in a way that is
easier to read?
Additionally, we propose another way: add an enable-byte option
--- a/drivers/i2c/busses/i2c-ast2600.c
+++ b/drivers/i2c/busses/i2c-ast2600.c
@@ -1643,6 +1643,9 @@ static int ast2600_i2c_probe(struct
platform_device *pdev)
i2c_bus->mode = BUFF_MODE;
#endif
+ if (device_property_read_bool(dev, "aspeed,enable-byte"))
+ i2c_bus->mode = BYTE_MODE;
+
if (device_property_read_bool(dev, "aspeed,enable-buff"))
i2c_bus->mode = BUFF_MODE;
This way, we would only need to add "aspeed,enable-byte;" in the DTS
to enable it, and no additional log would appear in dmesg.
&i2c13 {
status = "okay";
clock-frequency = <100000>;
multi-master;
aspeed,enable-byte;
...
};
The above is our feedback. Thank you for your consideration!
Best regards,
Yikai
Ryan Chen 於 2024/10/7 上午 11:52 寫道:
> Add i2c new register mode driver to support AST2600 i2c
> new register mode. AST2600 i2c controller have legacy and
> new register mode. The new register mode have global register
> support 4 base clock for scl clock selection, and new clock
> divider mode. The new register mode have separate register
> set to control i2c controller and target. This patch is for i2c
> controller mode driver.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
> drivers/i2c/busses/Kconfig | 11 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-ast2600.c | 1032 ++++++++++++++++++++++++++++++
> 3 files changed, 1044 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-ast2600.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index a22f9125322a..abfb027350d4 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -410,6 +410,17 @@ config I2C_ALTERA
> This driver can also be built as a module. If so, the module
> will be called i2c-altera.
>
> +config I2C_AST2600
> + tristate "Aspeed I2C v2 Controller"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + select I2C_SMBUS
> + help
> + If you say yes to this option, support will be included for the
> + Aspeed I2C controller with new register set.
> +
> + This driver can also be built as a module. If so, the module
> + will be called i2c-ast2600.
> +
> config I2C_ASPEED
> tristate "Aspeed I2C Controller"
> depends on ARCH_ASPEED || COMPILE_TEST
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 78d0561339e5..5665b60b1566 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
> obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
> obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o
> obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
> +obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
> obj-$(CONFIG_I2C_AT91) += i2c-at91.o
> i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
> ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
> diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2600.c
> new file mode 100644
> index 000000000000..17ba0ee77c27
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-ast2600.c
> @@ -0,0 +1,1032 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * ASPEED AST2600 new register set I2C controller driver
> + *
> + * Copyright (C) ASPEED Technology Inc.
> + */
> +#include <asm/unaligned.h>
> +#include <linux/array_size.h>
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/i2c-smbus.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/minmax.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/string_helpers.h>
> +
> +#define AST2600_I2CG_ISR 0x00
> +#define AST2600_I2CG_SLAVE_ISR 0x04
> +#define AST2600_I2CG_OWNER 0x08
> +#define AST2600_I2CG_CTRL 0x0C
> +#define AST2600_I2CG_CLK_DIV_CTRL 0x10
> +
> +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
> +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
> +#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
> +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
> +#define AST2600_GLOBAL_INIT \
> + (AST2600_I2CG_CTRL_NEW_REG | AST2600_I2CG_CTRL_NEW_CLK_DIV)
> +/*
> + * APB clk : 100Mhz
> + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
> + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6)
> + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
> + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
> + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
> + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
> + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
> + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
> + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
> + * 0x12 : 400Khz : 10Mhz : 1.6us
> + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
> + * 0x08 : 1Mhz : 20Mhz : 0.8us
> + */
> +#define I2CCG_DIV_CTRL 0xC6411208
> +
> +/* 0x00 : I2CC Controller/Target Function Control Register */
> +#define AST2600_I2CC_FUN_CTRL 0x00
> +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
> +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
> +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0)) << 18)
> +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
> +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
> +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
> +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
> +#define AST2600_I2CC_MSB_STS BIT(9)
> +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
> +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
> +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
> +/* reserver 5 : 2 */
> +#define AST2600_I2CC_SLAVE_EN BIT(1)
> +#define AST2600_I2CC_MASTER_EN BIT(0)
> +
> +/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
> +#define AST2600_I2CC_AC_TIMING 0x04
> +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0)) << 24)
> +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0)) << 20)
> +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
> +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
> +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
> +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1, 0)) << 8)
> +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
> +
> +/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
> +#define AST2600_I2CC_STS_AND_BUFF 0x08
> +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
> +#define AST2600_I2CC_SDA_OE BIT(28)
> +#define AST2600_I2CC_SDA_O BIT(27)
> +#define AST2600_I2CC_SCL_OE BIT(26)
> +#define AST2600_I2CC_SCL_O BIT(25)
> +
> +#define AST2600_I2CC_SCL_LINE_STS BIT(18)
> +#define AST2600_I2CC_SDA_LINE_STS BIT(17)
> +#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
> +
> +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) & GENMASK(7, 0))
> +
> +/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
> +#define AST2600_I2CC_BUFF_CTRL 0x0C
> +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29, 24)) >> 24)
> +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 16) | BIT(0))
> +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 8) | BIT(0))
> +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12, 8)) >> 8) + 1)
> +
> +/* 0x10 : I2CM Controller Interrupt Control Register */
> +#define AST2600_I2CM_IER 0x10
> +/* 0x14 : I2CM Controller Interrupt Status Register : WC */
> +#define AST2600_I2CM_ISR 0x14
> +
> +#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
> +#define AST2600_I2CM_PKT_ERROR BIT(17)
> +#define AST2600_I2CM_PKT_DONE BIT(16)
> +
> +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
> +#define AST2600_I2CM_SDA_DL_TO BIT(14)
> +#define AST2600_I2CM_BUS_RECOVER BIT(13)
> +#define AST2600_I2CM_SMBUS_ALT BIT(12)
> +
> +#define AST2600_I2CM_SCL_LOW_TO BIT(6)
> +#define AST2600_I2CM_ABNORMAL BIT(5)
> +#define AST2600_I2CM_NORMAL_STOP BIT(4)
> +#define AST2600_I2CM_ARBIT_LOSS BIT(3)
> +#define AST2600_I2CM_RX_DONE BIT(2)
> +#define AST2600_I2CM_TX_NAK BIT(1)
> +#define AST2600_I2CM_TX_ACK BIT(0)
> +
> +/* 0x18 : I2CM Controller Command/Status Register */
> +#define AST2600_I2CM_CMD_STS 0x18
> +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0)) << 24)
> +#define AST2600_I2CM_PKT_EN BIT(16)
> +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
> +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
> +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
> +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
> +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
> +
> +#define AST2600_I2CM_RX_DMA_EN BIT(9)
> +#define AST2600_I2CM_TX_DMA_EN BIT(8)
> +/* Command Bit */
> +#define AST2600_I2CM_RX_BUFF_EN BIT(7)
> +#define AST2600_I2CM_TX_BUFF_EN BIT(6)
> +#define AST2600_I2CM_STOP_CMD BIT(5)
> +#define AST2600_I2CM_RX_CMD_LAST BIT(4)
> +#define AST2600_I2CM_RX_CMD BIT(3)
> +
> +#define AST2600_I2CM_TX_CMD BIT(1)
> +#define AST2600_I2CM_START_CMD BIT(0)
> +
> +/* 0x1C : I2CM Controller DMA Transfer Length Register */
> +#define AST2600_I2CM_DMA_LEN 0x1C
> +/* Tx Rx support length 1 ~ 4096 */
> +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0)) << 16) | BIT(31))
> +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0)) | BIT(15))
> +
> +/* 0x20 : I2CS Target Interrupt Control Register */
> +#define AST2600_I2CS_IER 0x20
> +/* 0x24 : I2CS Target Interrupt Status Register */
> +#define AST2600_I2CS_ISR 0x24
> +
> +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
> +#define AST2600_I2CS_SLAVE_PENDING BIT(29)
> +
> +#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
> +#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
> +
> +#define AST2600_I2CS_ADDR3_NAK BIT(22)
> +#define AST2600_I2CS_ADDR2_NAK BIT(21)
> +#define AST2600_I2CS_ADDR1_NAK BIT(20)
> +
> +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
> +#define AST2600_I2CS_PKT_ERROR BIT(17)
> +#define AST2600_I2CS_PKT_DONE BIT(16)
> +#define AST2600_I2CS_INACTIVE_TO BIT(15)
> +
> +#define AST2600_I2CS_SLAVE_MATCH BIT(7)
> +#define AST2600_I2CS_ABNOR_STOP BIT(5)
> +#define AST2600_I2CS_STOP BIT(4)
> +#define AST2600_I2CS_RX_DONE_NAK BIT(3)
> +#define AST2600_I2CS_RX_DONE BIT(2)
> +#define AST2600_I2CS_TX_NAK BIT(1)
> +#define AST2600_I2CS_TX_ACK BIT(0)
> +
> +/* 0x28 : I2CS Target CMD/Status Register */
> +#define AST2600_I2CS_CMD_STS 0x28
> +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
> +#define AST2600_I2CS_PKT_MODE_EN BIT(16)
> +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
> +#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
> +
> +#define AST2600_I2CS_ALT_EN BIT(10)
> +#define AST2600_I2CS_RX_DMA_EN BIT(9)
> +#define AST2600_I2CS_TX_DMA_EN BIT(8)
> +#define AST2600_I2CS_RX_BUFF_EN BIT(7)
> +#define AST2600_I2CS_TX_BUFF_EN BIT(6)
> +#define AST2600_I2CS_RX_CMD_LAST BIT(4)
> +
> +#define AST2600_I2CS_TX_CMD BIT(2)
> +
> +#define AST2600_I2CS_DMA_LEN 0x2C
> +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0)) << 16) | BIT(31))
> +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0)) | BIT(15))
> +
> +/* I2CM Controller DMA Tx Buffer Register */
> +#define AST2600_I2CM_TX_DMA 0x30
> +/* I2CM Controller DMA Rx Buffer Register */
> +#define AST2600_I2CM_RX_DMA 0x34
> +/* I2CS Target DMA Tx Buffer Register */
> +#define AST2600_I2CS_TX_DMA 0x38
> +/* I2CS Target DMA Rx Buffer Register */
> +#define AST2600_I2CS_RX_DMA 0x3C
> +
> +#define AST2600_I2CS_ADDR_CTRL 0x40
> +
> +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
> +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
> +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
> +
> +#define AST2600_I2CM_DMA_LEN_STS 0x48
> +#define AST2600_I2CS_DMA_LEN_STS 0x4C
> +
> +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
> +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28, 16)) >> 16)
> +
> +/* 0x40 : Target Device Address Register */
> +#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
> +#define AST2600_I2CS_ADDR3(x) ((x) << 16)
> +#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
> +#define AST2600_I2CS_ADDR2(x) ((x) << 8)
> +#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
> +#define AST2600_I2CS_ADDR1(x) (x)
> +
> +#define I2C_TARGET_MSG_BUF_SIZE 256
> +
> +#define AST2600_I2C_DMA_SIZE 4096
> +
> +#define CONTROLLER_TRIGGER_LAST_STOP (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
> +#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL | AST2600_I2CS_PKT_MODE_EN)
> +
> +#define AST_I2C_TIMEOUT_CLK 0x2
> +
> +enum xfer_mode {
> + BYTE_MODE,
> + BUFF_MODE,
> + DMA_MODE,
> +};
> +
> +struct ast2600_i2c_bus {
> + struct i2c_adapter adap;
> + struct device *dev;
> + void __iomem *reg_base;
> + struct regmap *global_regs;
> + struct reset_control *rst;
> + struct clk *clk;
> + struct i2c_timings timing_info;
> + struct completion cmd_complete;
> + struct i2c_msg *msgs;
> + u8 *controller_dma_safe_buf;
> + dma_addr_t controller_dma_addr;
> + u32 apb_clk;
> + u32 timeout;
> + int irq;
> + int cmd_err;
> + int msgs_index;
> + int msgs_count;
> + int controller_xfer_cnt;
> + size_t buf_index;
> + size_t buf_size;
> + enum xfer_mode mode;
> + bool multi_master;
> + /* Buffer mode */
> + void __iomem *buf_base;
> + struct i2c_smbus_alert_setup alert_data;
> +};
> +
> +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
> +{
> + unsigned long base_clk[16];
> + int baseclk_idx = 0;
> + int divisor = 0;
> + u32 clk_div_reg;
> + u32 scl_low;
> + u32 scl_high;
> + u32 data;
> +
> + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, &clk_div_reg);
> +
> + for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
> + if (i == 0)
> + base_clk[i] = i2c_bus->apb_clk;
> + else if (i < 5)
> + base_clk[i] = (i2c_bus->apb_clk * 2) /
> + (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
> + else
> + base_clk[i] = base_clk[4] >> (i - 5);
> +
> + if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
> + baseclk_idx = i;
> + divisor = DIV_ROUND_UP(base_clk[i], i2c_bus->timing_info.bus_freq_hz);
> + break;
> + }
> + }
> + baseclk_idx = min(baseclk_idx, 15);
> + divisor = min(divisor, 32);
> + scl_low = min(divisor * 9 / 16 - 1, 15);
> + scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
> + data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
> + if (i2c_bus->timeout) {
> + data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
> + data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
> + }
> +
> + return data;
> +}
> +
> +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus)
> +{
> + u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + int ret = 0;
> + u32 ctrl;
> + int r;
> +
> + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n", i2c_bus->adap.nr, state);
> +
> + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + /* Disable controller */
> + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
> + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) | AST2600_I2CC_MASTER_EN,
> + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + reinit_completion(&i2c_bus->cmd_complete);
> + i2c_bus->cmd_err = 0;
> +
> + /* Check 0x14's SDA and SCL status */
> + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state & AST2600_I2CC_SCL_LINE_STS)) {
> + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> + r = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
> + if (r == 0) {
> + dev_dbg(i2c_bus->dev, "recovery timed out\n");
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + return -ETIMEDOUT;
> + } else if (i2c_bus->cmd_err) {
> + dev_dbg(i2c_bus->dev, "recovery error\n");
> + ret = -EPROTO;
> + }
> + }
> +
> + /* Recovery done */
> + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + if (state & AST2600_I2CC_BUS_BUSY_STS) {
> + dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
> + ret = -EPROTO;
> + }
> +
> + /* restore original controller setting */
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + return ret;
> +}
> +
> +static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + int ret;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > AST2600_I2C_DMA_SIZE)
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (cmd & AST2600_I2CM_START_CMD) {
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
> + if (!i2c_bus->controller_dma_safe_buf)
> + return -ENOMEM;
> + i2c_bus->controller_dma_addr =
> + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> + msg->len, DMA_TO_DEVICE);
> + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> + if (ret) {
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + return ret;
> + }
> + }
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
> + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
> + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
> + i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 wbuf_dword;
> + int xfer_len;
> + int i;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > i2c_bus->buf_size)
> + xfer_len = i2c_bus->buf_size;
> + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (cmd & AST2600_I2CM_START_CMD)
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
> + /*
> + * The controller's buffer register supports dword writes only.
> + * Therefore, write dwords to the buffer register in a 4-byte aligned,
> + * and write the remaining unaligned data at the end.
> + */
> + for (i = 0; i < xfer_len; i += 4) {
> + int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
> +
> + switch (min(xfer_len - i, 4) % 4) {
> + case 1:
> + wbuf_dword = msg->buf[xfer_cnt];
> + break;
> + case 2:
> + wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
> + break;
> + case 3:
> + wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
> + break;
> + default:
> + wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
> + break;
> + }
> + writel(wbuf_dword, i2c_bus->buf_base + i);
> + }
> + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
> + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> +
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> +
> + cmd |= AST2600_I2CM_PKT_EN;
> +
> + if (cmd & AST2600_I2CM_START_CMD)
> + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> +
> + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> + ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
> + cmd |= AST2600_I2CM_STOP_CMD;
> +
> + if (xfer_len) {
> + cmd |= AST2600_I2CM_TX_CMD;
> + writel(msg->buf[i2c_bus->controller_xfer_cnt],
> + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + u32 cmd;
> + int ret;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + xfer_len = 1;
> + } else if (msg->len > AST2600_I2C_DMA_SIZE) {
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + } else {
> + xfer_len = msg->len;
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg, 1);
> + if (!i2c_bus->controller_dma_safe_buf)
> + return -ENOMEM;
> + i2c_bus->controller_dma_addr =
> + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> + msg->len, DMA_FROM_DEVICE);
> + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> + if (ret) {
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf, msg, false);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + return ret;
> + }
> + writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + int xfer_len;
> + u32 cmd;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + dev_dbg(i2c_bus->dev, "smbus read\n");
> + xfer_len = 1;
> + } else if (msg->len > i2c_bus->buf_size) {
> + xfer_len = i2c_bus->buf_size;
> + } else {
> + xfer_len = msg->len;
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 cmd;
> +
> + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) |
> + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + dev_dbg(i2c_bus->dev, "smbus read\n");
> + } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
> + if (msg->len == 1)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> +
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> +
> + return 0;
> +}
> +
> +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> +
> + /* send start */
> + dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
> + i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
> + msg->len, str_plural(msg->len),
> + msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
> +
> + i2c_bus->controller_xfer_cnt = 0;
> + i2c_bus->buf_index = 0;
> +
> + if (msg->flags & I2C_M_RD) {
> + if (i2c_bus->mode == DMA_MODE)
> + return ast2600_i2c_setup_dma_rx(i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + return ast2600_i2c_setup_buff_rx(i2c_bus);
> + else
> + return ast2600_i2c_setup_byte_rx(i2c_bus);
> + } else {
> + if (i2c_bus->mode == DMA_MODE)
> + return ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + else
> + return ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
> + }
> +}
> +
> +static int ast2600_i2c_irq_err_to_errno(u32 irq_status)
> +{
> + if (irq_status & AST2600_I2CM_ARBIT_LOSS)
> + return -EAGAIN;
> + if (irq_status & (AST2600_I2CM_SDA_DL_TO | AST2600_I2CM_SCL_LOW_TO))
> + return -EBUSY;
> + if (irq_status & (AST2600_I2CM_ABNORMAL))
> + return -EPROTO;
> +
> + return 0;
> +}
> +
> +static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus *i2c_bus, u32 sts)
> +{
> + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> + u32 cmd = AST2600_I2CM_PKT_EN;
> + int xfer_len;
> + int i;
> +
> + sts &= ~AST2600_I2CM_PKT_DONE;
> + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + switch (sts) {
> + case AST2600_I2CM_PKT_ERROR:
> + i2c_bus->cmd_err = -EAGAIN;
> + complete(&i2c_bus->cmd_complete);
> + break;
> + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for issue */
> + fallthrough;
> + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK | AST2600_I2CM_NORMAL_STOP:
> + i2c_bus->cmd_err = -ENXIO;
> + complete(&i2c_bus->cmd_complete);
> + break;
> + case AST2600_I2CM_NORMAL_STOP:
> + /* write 0 byte only have stop isr */
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + } else {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + }
> + break;
> + case AST2600_I2CM_TX_ACK:
> + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
> + if (i2c_bus->mode == DMA_MODE)
> + xfer_len = AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CM_DMA_LEN_STS));
> + else if (i2c_bus->mode == BUFF_MODE)
> + xfer_len = AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CC_BUFF_CTRL));
> + else
> + xfer_len = 1;
> +
> + i2c_bus->controller_xfer_cnt += xfer_len;
> +
> + if (i2c_bus->controller_xfer_cnt == msg->len) {
> + if (i2c_bus->mode == DMA_MODE) {
> + dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
> + msg->len, DMA_TO_DEVICE);
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> + msg, true);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + } else {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + }
> + } else {
> + if (i2c_bus->mode == DMA_MODE)
> + ast2600_i2c_setup_dma_tx(0, i2c_bus);
> + else if (i2c_bus->mode == BUFF_MODE)
> + ast2600_i2c_setup_buff_tx(0, i2c_bus);
> + else
> + ast2600_i2c_setup_byte_tx(0, i2c_bus);
> + }
> + break;
> + case AST2600_I2CM_RX_DONE:
> + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
> + /* do next rx */
> + if (i2c_bus->mode == DMA_MODE) {
> + xfer_len = AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CM_DMA_LEN_STS));
> + } else if (i2c_bus->mode == BUFF_MODE) {
> + xfer_len = AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
> + AST2600_I2CC_BUFF_CTRL));
> + for (i = 0; i < xfer_len; i++)
> + msg->buf[i2c_bus->controller_xfer_cnt + i] =
> + readb(i2c_bus->buf_base + 0x10 + i);
> + } else {
> + xfer_len = 1;
> + msg->buf[i2c_bus->controller_xfer_cnt] =
> + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
> + AST2600_I2CC_STS_AND_BUFF));
> + }
> +
> + if (msg->flags & I2C_M_RECV_LEN) {
> + msg->len = min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
> + msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
> + msg->flags &= ~I2C_M_RECV_LEN;
> + }
> + i2c_bus->controller_xfer_cnt += xfer_len;
> +
> + if (i2c_bus->controller_xfer_cnt == msg->len) {
> + if (i2c_bus->mode == DMA_MODE) {
> + dma_unmap_single(i2c_bus->dev, i2c_bus->controller_dma_addr,
> + msg->len, DMA_FROM_DEVICE);
> + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> + msg, true);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> +
> + i2c_bus->msgs_index++;
> + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> + i2c_bus->cmd_err = i2c_bus->msgs_index;
> + complete(&i2c_bus->cmd_complete);
> + } else {
> + if (ast2600_i2c_do_start(i2c_bus)) {
> + i2c_bus->cmd_err = -ENOMEM;
> + complete(&i2c_bus->cmd_complete);
> + }
> + }
> + } else {
> + /* next rx */
> + cmd |= AST2600_I2CM_RX_CMD;
> + if (i2c_bus->mode == DMA_MODE) {
> + cmd |= AST2600_I2CM_RX_DMA_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > AST2600_I2C_DMA_SIZE) {
> + xfer_len = AST2600_I2C_DMA_SIZE;
> + } else {
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> + writel(i2c_bus->controller_dma_addr + i2c_bus->controller_xfer_cnt,
> + i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> + } else if (i2c_bus->mode == BUFF_MODE) {
> + cmd |= AST2600_I2CM_RX_BUFF_EN;
> + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> + if (xfer_len > i2c_bus->buf_size) {
> + xfer_len = i2c_bus->buf_size;
> + } else {
> + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
> + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> + } else {
> + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> + ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
> + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> + }
> + }
> + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> + }
> + break;
> + default:
> + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
> + break;
> + }
> +}
> +
> +static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus *i2c_bus)
> +{
> + u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
> + u32 ctrl;
> +
> + sts &= ~AST2600_I2CM_SMBUS_ALT;
> +
> + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
> + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + i2c_bus->cmd_err = -EPROTO;
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + if (AST2600_I2CM_BUS_RECOVER & sts) {
> + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + i2c_bus->cmd_err = 0;
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
> + if (i2c_bus->cmd_err) {
> + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR);
> + complete(&i2c_bus->cmd_complete);
> + return 1;
> + }
> +
> + if (AST2600_I2CM_PKT_DONE & sts) {
> + ast2600_i2c_controller_package_irq(i2c_bus, sts);
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id)
> +{
> + struct ast2600_i2c_bus *i2c_bus = dev_id;
> +
> + return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
> +}
> +
> +static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
> +{
> + struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
> + unsigned long timeout;
> + int ret;
> +
> + if (!i2c_bus->multi_master &&
> + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_BUS_BUSY_STS)) {
> + ret = ast2600_i2c_recover_bus(i2c_bus);
> + if (ret)
> + return ret;
> + }
> +
> + i2c_bus->cmd_err = 0;
> + i2c_bus->msgs = msgs;
> + i2c_bus->msgs_index = 0;
> + i2c_bus->msgs_count = num;
> + reinit_completion(&i2c_bus->cmd_complete);
> + ret = ast2600_i2c_do_start(i2c_bus);
> + if (ret)
> + goto controller_out;
> + timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.timeout);
> + if (timeout == 0) {
> + u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
> + readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
> + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + if (i2c_bus->multi_master &&
> + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> + AST2600_I2CC_BUS_BUSY_STS))
> + ast2600_i2c_recover_bus(i2c_bus);
> +
> + ret = -ETIMEDOUT;
> + } else {
> + ret = i2c_bus->cmd_err;
> + }
> +
> + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr, i2c_bus->cmd_err);
> +
> +controller_out:
> + if (i2c_bus->mode == DMA_MODE) {
> + kfree(i2c_bus->controller_dma_safe_buf);
> + i2c_bus->controller_dma_safe_buf = NULL;
> + }
> +
> + return ret;
> +}
> +
> +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus)
> +{
> + struct platform_device *pdev = to_platform_device(i2c_bus->dev);
> + u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE | AST2600_I2CC_MASTER_EN;
> +
> + /* I2C Reset */
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> +
> + i2c_bus->multi_master = device_property_read_bool(&pdev->dev, "multi-master");
> + if (!i2c_bus->multi_master)
> + fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
> +
> + /* Enable Controller Mode */
> + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + /* disable target address */
> + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
> +
> + /* Set AC Timing */
> + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base + AST2600_I2CC_AC_TIMING);
> +
> + /* Clear Interrupt */
> + writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR);
> +}
> +
> +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
> +}
> +
> +static const struct i2c_algorithm i2c_ast2600_algorithm = {
> + .xfer = ast2600_i2c_controller_xfer,
> + .functionality = ast2600_i2c_functionality,
> +};
> +
> +static int ast2600_i2c_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct ast2600_i2c_bus *i2c_bus;
> + struct resource *res;
> + u32 global_ctrl;
> + int ret;
> +
> + i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
> + if (!i2c_bus)
> + return -ENOMEM;
> +
> + i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(i2c_bus->reg_base))
> + return PTR_ERR(i2c_bus->reg_base);
> +
> + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> + if (IS_ERR(i2c_bus->rst))
> + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset ctrl\n");
> +
> + reset_control_deassert(i2c_bus->rst);
> +
> + i2c_bus->global_regs =
> + syscon_regmap_lookup_by_phandle(dev_of_node(dev), "aspeed,global-regs");
> + if (IS_ERR(i2c_bus->global_regs))
> + return PTR_ERR(i2c_bus->global_regs);
> +
> + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
> + if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
> + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL, AST2600_GLOBAL_INIT);
> + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, I2CCG_DIV_CTRL);
> + }
> +
> + i2c_bus->dev = dev;
> + i2c_bus->mode = BUFF_MODE;
> +
> + if (device_property_read_bool(dev, "aspeed,enable-dma"))
> + i2c_bus->mode = DMA_MODE;
> +
> + if (i2c_bus->mode == BUFF_MODE) {
> + i2c_bus->buf_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> + if (IS_ERR(i2c_bus->buf_base))
> + i2c_bus->mode = BYTE_MODE;
> + else
> + i2c_bus->buf_size = resource_size(res) / 2;
> + }
> +
> + /*
> + * i2c timeout counter: use base clk4 1Mhz,
> + * per unit: 1/(1000/4096) = 4096us
> + */
> + ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us", &i2c_bus->timeout);
> + if (!ret)
> + i2c_bus->timeout /= 4096;
> +
> + init_completion(&i2c_bus->cmd_complete);
> +
> + i2c_bus->irq = platform_get_irq(pdev, 0);
> + if (i2c_bus->irq < 0)
> + return i2c_bus->irq;
> +
> + platform_set_drvdata(pdev, i2c_bus);
> +
> + i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
> + if (IS_ERR(i2c_bus->clk))
> + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't get clock\n");
> +
> + i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
> +
> + i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
> +
> + /* Initialize the I2C adapter */
> + i2c_bus->adap.owner = THIS_MODULE;
> + i2c_bus->adap.algo = &i2c_ast2600_algorithm;
> + i2c_bus->adap.retries = 0;
> + i2c_bus->adap.dev.parent = i2c_bus->dev;
> + device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
> + i2c_bus->adap.algo_data = i2c_bus;
> + strscpy(i2c_bus->adap.name, pdev->name);
> + i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
> +
> + ast2600_i2c_init(i2c_bus);
> +
> + ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
> + dev_name(dev), i2c_bus);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Unable to request irq %d\n", i2c_bus->irq);
> +
> + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
> + i2c_bus->reg_base + AST2600_I2CM_IER);
> +
> + ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void ast2600_i2c_remove(struct platform_device *pdev)
> +{
> + struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
> +
> + /* Disable everything. */
> + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER);
> +}
> +
> +static const struct of_device_id ast2600_i2c_bus_of_table[] = {
> + {
> + .compatible = "aspeed,ast2600-i2cv2",
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
> +
> +static struct platform_driver ast2600_i2c_bus_driver = {
> + .probe = ast2600_i2c_probe,
> + .remove = ast2600_i2c_remove,
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .of_match_table = ast2600_i2c_bus_of_table,
> + },
> +};
> +
> +module_platform_driver(ast2600_i2c_bus_driver);
> +
> +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
> +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-12 4:54 ` Yikai Tsai
@ 2024-11-12 6:55 ` Ryan Chen
0 siblings, 0 replies; 15+ messages in thread
From: Ryan Chen @ 2024-11-12 6:55 UTC (permalink / raw)
To: Yikai Tsai, brendan.higgins@linux.dev, benh@kernel.crashing.org,
joel@jms.id.au, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, p.zabel@pengutronix.de,
andriy.shevchenko@linux.intel.com, linux-i2c@vger.kernel.org,
openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register
> mode driver
>
> Hi Ryan,
>
> Thank you for the I2Cv2 driver, it helps us a lot.
>
> We have the need to use byte-mode. After consulting with Aspeed, we set the
> reg property in DTS to use byte-mode, for example:
>
> &i2c13 {
> status = "okay";
> clock-frequency = <100000>;
> multi-master;
> /delete-property/ reg;
> reg = <0x700 0x80>;
> ...
> };
>
> However, we will see "invalid resource" under dmesg.
>
> [ 5.482254] i2c_ast2600 1e78a700.i2c: invalid resource (null)
> [ 5.496110] i2c_ast2600 1e78a700.i2c: i2c [13]: adapter [100 khz]
> mode [0]
>
> According to Aspeed, i2c-13 still has byte-mode enabled despite the
> occurrence of "invalid resource". However, the "invalid resource"
> message doesn't clearly express what happened to it.
> Could you please change this message to be presented in a way that is easier
> to read?
>
>
> Additionally, we propose another way: add an enable-byte option
>
> --- a/drivers/i2c/busses/i2c-ast2600.c
> +++ b/drivers/i2c/busses/i2c-ast2600.c
> @@ -1643,6 +1643,9 @@ static int ast2600_i2c_probe(struct platform_device
> *pdev)
> i2c_bus->mode = BUFF_MODE;
> #endif
>
> + if (device_property_read_bool(dev, "aspeed,enable-byte"))
> + i2c_bus->mode = BYTE_MODE;
> +
> if (device_property_read_bool(dev, "aspeed,enable-buff"))
> i2c_bus->mode = BUFF_MODE;
>
> This way, we would only need to add "aspeed,enable-byte;" in the DTS to
> enable it, and no additional log would appear in dmesg.
Yes, will add this property, force byte mode.
>
> &i2c13 {
> status = "okay";
> clock-frequency = <100000>;
> multi-master;
> aspeed,enable-byte;
> ...
> };
>
> The above is our feedback. Thank you for your consideration!
>
> Best regards,
> Yikai
>
>
> Ryan Chen 於 2024/10/7 上午 11:52 寫道:
> > Add i2c new register mode driver to support AST2600 i2c new register
> > mode. AST2600 i2c controller have legacy and new register mode. The
> > new register mode have global register support 4 base clock for scl
> > clock selection, and new clock divider mode. The new register mode
> > have separate register set to control i2c controller and target. This
> > patch is for i2c controller mode driver.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> > drivers/i2c/busses/Kconfig | 11 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-ast2600.c | 1032
> ++++++++++++++++++++++++++++++
> > 3 files changed, 1044 insertions(+)
> > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index a22f9125322a..abfb027350d4 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -410,6 +410,17 @@ config I2C_ALTERA
> > This driver can also be built as a module. If so, the module
> > will be called i2c-altera.
> >
> > +config I2C_AST2600
> > + tristate "Aspeed I2C v2 Controller"
> > + depends on ARCH_ASPEED || COMPILE_TEST
> > + select I2C_SMBUS
> > + help
> > + If you say yes to this option, support will be included for the
> > + Aspeed I2C controller with new register set.
> > +
> > + This driver can also be built as a module. If so, the module
> > + will be called i2c-ast2600.
> > +
> > config I2C_ASPEED
> > tristate "Aspeed I2C Controller"
> > depends on ARCH_ASPEED || COMPILE_TEST diff --git
> > a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index
> > 78d0561339e5..5665b60b1566 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
> > obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
> > obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o
> i2c-amd-mp2-plat.o
> > obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
> > +obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
> > obj-$(CONFIG_I2C_AT91) += i2c-at91.o
> > i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
> > ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
> > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > b/drivers/i2c/busses/i2c-ast2600.c
> > new file mode 100644
> > index 000000000000..17ba0ee77c27
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > @@ -0,0 +1,1032 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * ASPEED AST2600 new register set I2C controller driver
> > + *
> > + * Copyright (C) ASPEED Technology Inc.
> > + */
> > +#include <asm/unaligned.h>
> > +#include <linux/array_size.h>
> > +#include <linux/bits.h>
> > +#include <linux/clk.h>
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/err.h>
> > +#include <linux/i2c.h>
> > +#include <linux/i2c-smbus.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/minmax.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/property.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +#include <linux/slab.h>
> > +#include <linux/string_helpers.h>
> > +
> > +#define AST2600_I2CG_ISR 0x00
> > +#define AST2600_I2CG_SLAVE_ISR 0x04
> > +#define AST2600_I2CG_OWNER 0x08
> > +#define AST2600_I2CG_CTRL 0x0C
> > +#define AST2600_I2CG_CLK_DIV_CTRL 0x10
> > +
> > +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
> > +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
> > +#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
> > +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
> > +#define AST2600_GLOBAL_INIT \
> > + (AST2600_I2CG_CTRL_NEW_REG |
> AST2600_I2CG_CTRL_NEW_CLK_DIV)
> > +/*
> > + * APB clk : 100Mhz
> > + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
> > + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter
> > +(0xC6)
> > + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
> > + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
> > + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
> > + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
> > + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
> > + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
> > + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
> > + * 0x12 : 400Khz : 10Mhz : 1.6us
> > + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
> > + * 0x08 : 1Mhz : 20Mhz : 0.8us
> > + */
> > +#define I2CCG_DIV_CTRL 0xC6411208
> > +
> > +/* 0x00 : I2CC Controller/Target Function Control Register */
> > +#define AST2600_I2CC_FUN_CTRL 0x00
> > +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
> > +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
> > +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0))
> << 18)
> > +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
> > +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
> > +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
> > +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
> > +#define AST2600_I2CC_MSB_STS BIT(9)
> > +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
> > +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
> > +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
> > +/* reserver 5 : 2 */
> > +#define AST2600_I2CC_SLAVE_EN BIT(1)
> > +#define AST2600_I2CC_MASTER_EN BIT(0)
> > +
> > +/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
> > +#define AST2600_I2CC_AC_TIMING 0x04
> > +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0))
> << 24)
> > +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0))
> << 20)
> > +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
> > +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
> > +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
> > +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1,
> 0)) << 8)
> > +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
> > +
> > +/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
> > +#define AST2600_I2CC_STS_AND_BUFF 0x08
> > +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
> > +#define AST2600_I2CC_SDA_OE BIT(28)
> > +#define AST2600_I2CC_SDA_O BIT(27)
> > +#define AST2600_I2CC_SCL_OE BIT(26)
> > +#define AST2600_I2CC_SCL_O BIT(25)
> > +
> > +#define AST2600_I2CC_SCL_LINE_STS BIT(18)
> > +#define AST2600_I2CC_SDA_LINE_STS BIT(17)
> > +#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
> > +
> > +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) &
> GENMASK(7, 0))
> > +
> > +/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
> > +#define AST2600_I2CC_BUFF_CTRL 0x0C
> > +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29,
> 24)) >> 24)
> > +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> 0)) << 16) | BIT(0))
> > +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> 0)) << 8) | BIT(0))
> > +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12,
> 8)) >> 8) + 1)
> > +
> > +/* 0x10 : I2CM Controller Interrupt Control Register */
> > +#define AST2600_I2CM_IER 0x10
> > +/* 0x14 : I2CM Controller Interrupt Status Register : WC */
> > +#define AST2600_I2CM_ISR 0x14
> > +
> > +#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
> > +#define AST2600_I2CM_PKT_ERROR BIT(17)
> > +#define AST2600_I2CM_PKT_DONE BIT(16)
> > +
> > +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
> > +#define AST2600_I2CM_SDA_DL_TO BIT(14)
> > +#define AST2600_I2CM_BUS_RECOVER BIT(13)
> > +#define AST2600_I2CM_SMBUS_ALT BIT(12)
> > +
> > +#define AST2600_I2CM_SCL_LOW_TO BIT(6)
> > +#define AST2600_I2CM_ABNORMAL BIT(5)
> > +#define AST2600_I2CM_NORMAL_STOP BIT(4)
> > +#define AST2600_I2CM_ARBIT_LOSS BIT(3)
> > +#define AST2600_I2CM_RX_DONE BIT(2)
> > +#define AST2600_I2CM_TX_NAK BIT(1)
> > +#define AST2600_I2CM_TX_ACK BIT(0)
> > +
> > +/* 0x18 : I2CM Controller Command/Status Register */
> > +#define AST2600_I2CM_CMD_STS 0x18
> > +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0))
> << 24)
> > +#define AST2600_I2CM_PKT_EN BIT(16)
> > +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
> > +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
> > +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
> > +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
> > +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
> > +
> > +#define AST2600_I2CM_RX_DMA_EN BIT(9)
> > +#define AST2600_I2CM_TX_DMA_EN BIT(8)
> > +/* Command Bit */
> > +#define AST2600_I2CM_RX_BUFF_EN BIT(7)
> > +#define AST2600_I2CM_TX_BUFF_EN BIT(6)
> > +#define AST2600_I2CM_STOP_CMD BIT(5)
> > +#define AST2600_I2CM_RX_CMD_LAST BIT(4)
> > +#define AST2600_I2CM_RX_CMD BIT(3)
> > +
> > +#define AST2600_I2CM_TX_CMD BIT(1)
> > +#define AST2600_I2CM_START_CMD BIT(0)
> > +
> > +/* 0x1C : I2CM Controller DMA Transfer Length Register */
> > +#define AST2600_I2CM_DMA_LEN 0x1C
> > +/* Tx Rx support length 1 ~ 4096 */
> > +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0))
> << 16) | BIT(31))
> > +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0))
> | BIT(15))
> > +
> > +/* 0x20 : I2CS Target Interrupt Control Register */
> > +#define AST2600_I2CS_IER 0x20
> > +/* 0x24 : I2CS Target Interrupt Status Register */
> > +#define AST2600_I2CS_ISR 0x24
> > +
> > +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
> > +#define AST2600_I2CS_SLAVE_PENDING BIT(29)
> > +
> > +#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
> > +#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
> > +
> > +#define AST2600_I2CS_ADDR3_NAK BIT(22)
> > +#define AST2600_I2CS_ADDR2_NAK BIT(21)
> > +#define AST2600_I2CS_ADDR1_NAK BIT(20)
> > +
> > +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
> > +#define AST2600_I2CS_PKT_ERROR BIT(17)
> > +#define AST2600_I2CS_PKT_DONE BIT(16)
> > +#define AST2600_I2CS_INACTIVE_TO BIT(15)
> > +
> > +#define AST2600_I2CS_SLAVE_MATCH BIT(7)
> > +#define AST2600_I2CS_ABNOR_STOP BIT(5)
> > +#define AST2600_I2CS_STOP BIT(4)
> > +#define AST2600_I2CS_RX_DONE_NAK BIT(3)
> > +#define AST2600_I2CS_RX_DONE BIT(2)
> > +#define AST2600_I2CS_TX_NAK BIT(1)
> > +#define AST2600_I2CS_TX_ACK BIT(0)
> > +
> > +/* 0x28 : I2CS Target CMD/Status Register */
> > +#define AST2600_I2CS_CMD_STS 0x28
> > +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
> > +#define AST2600_I2CS_PKT_MODE_EN BIT(16)
> > +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
> > +#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
> > +
> > +#define AST2600_I2CS_ALT_EN BIT(10)
> > +#define AST2600_I2CS_RX_DMA_EN BIT(9)
> > +#define AST2600_I2CS_TX_DMA_EN BIT(8)
> > +#define AST2600_I2CS_RX_BUFF_EN BIT(7)
> > +#define AST2600_I2CS_TX_BUFF_EN BIT(6)
> > +#define AST2600_I2CS_RX_CMD_LAST BIT(4)
> > +
> > +#define AST2600_I2CS_TX_CMD BIT(2)
> > +
> > +#define AST2600_I2CS_DMA_LEN 0x2C
> > +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0))
> << 16) | BIT(31))
> > +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0))
> | BIT(15))
> > +
> > +/* I2CM Controller DMA Tx Buffer Register */
> > +#define AST2600_I2CM_TX_DMA 0x30
> > +/* I2CM Controller DMA Rx Buffer Register */
> > +#define AST2600_I2CM_RX_DMA 0x34
> > +/* I2CS Target DMA Tx Buffer Register */
> > +#define AST2600_I2CS_TX_DMA 0x38
> > +/* I2CS Target DMA Rx Buffer Register */
> > +#define AST2600_I2CS_RX_DMA 0x3C
> > +
> > +#define AST2600_I2CS_ADDR_CTRL 0x40
> > +
> > +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
> > +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
> > +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
> > +
> > +#define AST2600_I2CM_DMA_LEN_STS 0x48
> > +#define AST2600_I2CS_DMA_LEN_STS 0x4C
> > +
> > +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
> > +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28,
> 16)) >> 16)
> > +
> > +/* 0x40 : Target Device Address Register */
> > +#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
> > +#define AST2600_I2CS_ADDR3(x) ((x) << 16)
> > +#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
> > +#define AST2600_I2CS_ADDR2(x) ((x) << 8)
> > +#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
> > +#define AST2600_I2CS_ADDR1(x) (x)
> > +
> > +#define I2C_TARGET_MSG_BUF_SIZE 256
> > +
> > +#define AST2600_I2C_DMA_SIZE 4096
> > +
> > +#define CONTROLLER_TRIGGER_LAST_STOP
> (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
> > +#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL |
> AST2600_I2CS_PKT_MODE_EN)
> > +
> > +#define AST_I2C_TIMEOUT_CLK 0x2
> > +
> > +enum xfer_mode {
> > + BYTE_MODE,
> > + BUFF_MODE,
> > + DMA_MODE,
> > +};
> > +
> > +struct ast2600_i2c_bus {
> > + struct i2c_adapter adap;
> > + struct device *dev;
> > + void __iomem *reg_base;
> > + struct regmap *global_regs;
> > + struct reset_control *rst;
> > + struct clk *clk;
> > + struct i2c_timings timing_info;
> > + struct completion cmd_complete;
> > + struct i2c_msg *msgs;
> > + u8 *controller_dma_safe_buf;
> > + dma_addr_t controller_dma_addr;
> > + u32 apb_clk;
> > + u32 timeout;
> > + int irq;
> > + int cmd_err;
> > + int msgs_index;
> > + int msgs_count;
> > + int controller_xfer_cnt;
> > + size_t buf_index;
> > + size_t buf_size;
> > + enum xfer_mode mode;
> > + bool multi_master;
> > + /* Buffer mode */
> > + void __iomem *buf_base;
> > + struct i2c_smbus_alert_setup alert_data;
> > +};
> > +
> > +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + unsigned long base_clk[16];
> > + int baseclk_idx = 0;
> > + int divisor = 0;
> > + u32 clk_div_reg;
> > + u32 scl_low;
> > + u32 scl_high;
> > + u32 data;
> > +
> > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> > +&clk_div_reg);
> > +
> > + for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
> > + if (i == 0)
> > + base_clk[i] = i2c_bus->apb_clk;
> > + else if (i < 5)
> > + base_clk[i] = (i2c_bus->apb_clk * 2) /
> > + (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
> > + else
> > + base_clk[i] = base_clk[4] >> (i - 5);
> > +
> > + if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
> > + baseclk_idx = i;
> > + divisor = DIV_ROUND_UP(base_clk[i],
> i2c_bus->timing_info.bus_freq_hz);
> > + break;
> > + }
> > + }
> > + baseclk_idx = min(baseclk_idx, 15);
> > + divisor = min(divisor, 32);
> > + scl_low = min(divisor * 9 / 16 - 1, 15);
> > + scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
> > + data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
> > + if (i2c_bus->timeout) {
> > + data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
> > + data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
> > + }
> > +
> > + return data;
> > +}
> > +
> > +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus) {
> > + u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + int ret = 0;
> > + u32 ctrl;
> > + int r;
> > +
> > + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n",
> > +i2c_bus->adap.nr, state);
> > +
> > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + /* Disable controller */
> > + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
> > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) |
> AST2600_I2CC_MASTER_EN,
> > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + reinit_completion(&i2c_bus->cmd_complete);
> > + i2c_bus->cmd_err = 0;
> > +
> > + /* Check 0x14's SDA and SCL status */
> > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state &
> AST2600_I2CC_SCL_LINE_STS)) {
> > + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base +
> AST2600_I2CM_CMD_STS);
> > + r = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> i2c_bus->adap.timeout);
> > + if (r == 0) {
> > + dev_dbg(i2c_bus->dev, "recovery timed out\n");
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + return -ETIMEDOUT;
> > + } else if (i2c_bus->cmd_err) {
> > + dev_dbg(i2c_bus->dev, "recovery error\n");
> > + ret = -EPROTO;
> > + }
> > + }
> > +
> > + /* Recovery done */
> > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + if (state & AST2600_I2CC_BUS_BUSY_STS) {
> > + dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
> > + ret = -EPROTO;
> > + }
> > +
> > + /* restore original controller setting */
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + return ret;
> > +}
> > +
> > +static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + int ret;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > AST2600_I2C_DMA_SIZE)
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD) {
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > + i2c_bus->controller_dma_safe_buf =
> i2c_get_dma_safe_msg_buf(msg, 1);
> > + if (!i2c_bus->controller_dma_safe_buf)
> > + return -ENOMEM;
> > + i2c_bus->controller_dma_addr =
> > + dma_map_single(i2c_bus->dev,
> i2c_bus->controller_dma_safe_buf,
> > + msg->len, DMA_TO_DEVICE);
> > + ret = dma_mapping_error(i2c_bus->dev,
> i2c_bus->controller_dma_addr);
> > + if (ret) {
> > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> msg, false);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + return ret;
> > + }
> > + }
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
> > + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
> > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + writel(i2c_bus->controller_dma_addr +
> i2c_bus->controller_xfer_cnt,
> > + i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 wbuf_dword;
> > + int xfer_len;
> > + int i;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > i2c_bus->buf_size)
> > + xfer_len = i2c_bus->buf_size;
> > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD)
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
> > + /*
> > + * The controller's buffer register supports dword writes only.
> > + * Therefore, write dwords to the buffer register in a 4-byte aligned,
> > + * and write the remaining unaligned data at the end.
> > + */
> > + for (i = 0; i < xfer_len; i += 4) {
> > + int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
> > +
> > + switch (min(xfer_len - i, 4) % 4) {
> > + case 1:
> > + wbuf_dword = msg->buf[xfer_cnt];
> > + break;
> > + case 2:
> > + wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
> > + break;
> > + case 3:
> > + wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
> > + break;
> > + default:
> > + wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
> > + break;
> > + }
> > + writel(wbuf_dword, i2c_bus->buf_base + i);
> > + }
> > + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
> > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > +
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD)
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > +
> > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_CMD;
> > + writel(msg->buf[i2c_bus->controller_xfer_cnt],
> > + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + u32 cmd;
> > + int ret;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + xfer_len = 1;
> > + } else if (msg->len > AST2600_I2C_DMA_SIZE) {
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + } else {
> > + xfer_len = msg->len;
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg,
> 1);
> > + if (!i2c_bus->controller_dma_safe_buf)
> > + return -ENOMEM;
> > + i2c_bus->controller_dma_addr =
> > + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> > + msg->len, DMA_FROM_DEVICE);
> > + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> > + if (ret) {
> > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> msg, false);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + return ret;
> > + }
> > + writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base +
> > +AST2600_I2CM_RX_DMA);
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + u32 cmd;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > + xfer_len = 1;
> > + } else if (msg->len > i2c_bus->buf_size) {
> > + xfer_len = i2c_bus->buf_size;
> > + } else {
> > + xfer_len = msg->len;
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base +
> > +AST2600_I2CC_BUFF_CTRL);
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 cmd;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > + } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
> > + if (msg->len == 1)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > +
> > + /* send start */
> > + dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
> > + i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
> > + msg->len, str_plural(msg->len),
> > + msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
> > +
> > + i2c_bus->controller_xfer_cnt = 0;
> > + i2c_bus->buf_index = 0;
> > +
> > + if (msg->flags & I2C_M_RD) {
> > + if (i2c_bus->mode == DMA_MODE)
> > + return ast2600_i2c_setup_dma_rx(i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + return ast2600_i2c_setup_buff_rx(i2c_bus);
> > + else
> > + return ast2600_i2c_setup_byte_rx(i2c_bus);
> > + } else {
> > + if (i2c_bus->mode == DMA_MODE)
> > + return
> ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD,
> i2c_bus);
> > + else
> > + return
> ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > + }
> > +}
> > +
> > +static int ast2600_i2c_irq_err_to_errno(u32 irq_status) {
> > + if (irq_status & AST2600_I2CM_ARBIT_LOSS)
> > + return -EAGAIN;
> > + if (irq_status & (AST2600_I2CM_SDA_DL_TO |
> AST2600_I2CM_SCL_LOW_TO))
> > + return -EBUSY;
> > + if (irq_status & (AST2600_I2CM_ABNORMAL))
> > + return -EPROTO;
> > +
> > + return 0;
> > +}
> > +
> > +static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus
> > +*i2c_bus, u32 sts) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 cmd = AST2600_I2CM_PKT_EN;
> > + int xfer_len;
> > + int i;
> > +
> > + sts &= ~AST2600_I2CM_PKT_DONE;
> > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + switch (sts) {
> > + case AST2600_I2CM_PKT_ERROR:
> > + i2c_bus->cmd_err = -EAGAIN;
> > + complete(&i2c_bus->cmd_complete);
> > + break;
> > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for
> issue */
> > + fallthrough;
> > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK |
> AST2600_I2CM_NORMAL_STOP:
> > + i2c_bus->cmd_err = -ENXIO;
> > + complete(&i2c_bus->cmd_complete);
> > + break;
> > + case AST2600_I2CM_NORMAL_STOP:
> > + /* write 0 byte only have stop isr */
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + } else {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + break;
> > + case AST2600_I2CM_TX_ACK:
> > + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
> > + if (i2c_bus->mode == DMA_MODE)
> > + xfer_len =
> AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CM_DMA_LEN_STS));
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + xfer_len =
> AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_BUFF_CTRL));
> > + else
> > + xfer_len = 1;
> > +
> > + i2c_bus->controller_xfer_cnt += xfer_len;
> > +
> > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > + if (i2c_bus->mode == DMA_MODE) {
> > + dma_unmap_single(i2c_bus->dev,
> i2c_bus->controller_dma_addr,
> > + msg->len, DMA_TO_DEVICE);
> > +
> i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > + msg, true);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + } else {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + }
> > + } else {
> > + if (i2c_bus->mode == DMA_MODE)
> > + ast2600_i2c_setup_dma_tx(0, i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + ast2600_i2c_setup_buff_tx(0, i2c_bus);
> > + else
> > + ast2600_i2c_setup_byte_tx(0, i2c_bus);
> > + }
> > + break;
> > + case AST2600_I2CM_RX_DONE:
> > + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
> > + /* do next rx */
> > + if (i2c_bus->mode == DMA_MODE) {
> > + xfer_len =
> AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CM_DMA_LEN_STS));
> > + } else if (i2c_bus->mode == BUFF_MODE) {
> > + xfer_len =
> AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_BUFF_CTRL));
> > + for (i = 0; i < xfer_len; i++)
> > + msg->buf[i2c_bus->controller_xfer_cnt + i] =
> > + readb(i2c_bus->buf_base + 0x10 + i);
> > + } else {
> > + xfer_len = 1;
> > + msg->buf[i2c_bus->controller_xfer_cnt] =
> > + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_STS_AND_BUFF));
> > + }
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + msg->len = min_t(unsigned int, msg->buf[0],
> I2C_SMBUS_BLOCK_MAX);
> > + msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
> > + msg->flags &= ~I2C_M_RECV_LEN;
> > + }
> > + i2c_bus->controller_xfer_cnt += xfer_len;
> > +
> > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > + if (i2c_bus->mode == DMA_MODE) {
> > + dma_unmap_single(i2c_bus->dev,
> i2c_bus->controller_dma_addr,
> > + msg->len, DMA_FROM_DEVICE);
> > +
> i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > + msg, true);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > +
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + } else {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + }
> > + } else {
> > + /* next rx */
> > + cmd |= AST2600_I2CM_RX_CMD;
> > + if (i2c_bus->mode == DMA_MODE) {
> > + cmd |= AST2600_I2CM_RX_DMA_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > AST2600_I2C_DMA_SIZE) {
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + } else {
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + writel(i2c_bus->controller_dma_addr +
> i2c_bus->controller_xfer_cnt,
> > + i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> > + } else if (i2c_bus->mode == BUFF_MODE) {
> > + cmd |= AST2600_I2CM_RX_BUFF_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > i2c_bus->buf_size) {
> > + xfer_len = i2c_bus->buf_size;
> > + } else {
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
> > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > + } else {
> > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + }
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > + }
> > + break;
> > + default:
> > + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
> > + break;
> > + }
> > +}
> > +
> > +static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
> > + u32 ctrl;
> > +
> > + sts &= ~AST2600_I2CM_SMBUS_ALT;
> > +
> > + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
> > + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + i2c_bus->cmd_err = -EPROTO;
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + if (AST2600_I2CM_BUS_RECOVER & sts) {
> > + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + i2c_bus->cmd_err = 0;
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
> > + if (i2c_bus->cmd_err) {
> > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + if (AST2600_I2CM_PKT_DONE & sts) {
> > + ast2600_i2c_controller_package_irq(i2c_bus, sts);
> > + return 1;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id) {
> > + struct ast2600_i2c_bus *i2c_bus = dev_id;
> > +
> > + return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
> > +}
> > +
> > +static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap,
> > +struct i2c_msg *msgs, int num) {
> > + struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
> > + unsigned long timeout;
> > + int ret;
> > +
> > + if (!i2c_bus->multi_master &&
> > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> AST2600_I2CC_BUS_BUSY_STS)) {
> > + ret = ast2600_i2c_recover_bus(i2c_bus);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + i2c_bus->cmd_err = 0;
> > + i2c_bus->msgs = msgs;
> > + i2c_bus->msgs_index = 0;
> > + i2c_bus->msgs_count = num;
> > + reinit_completion(&i2c_bus->cmd_complete);
> > + ret = ast2600_i2c_do_start(i2c_bus);
> > + if (ret)
> > + goto controller_out;
> > + timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> i2c_bus->adap.timeout);
> > + if (timeout == 0) {
> > + u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
> > + readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
> > + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + if (i2c_bus->multi_master &&
> > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> > + AST2600_I2CC_BUS_BUSY_STS))
> > + ast2600_i2c_recover_bus(i2c_bus);
> > +
> > + ret = -ETIMEDOUT;
> > + } else {
> > + ret = i2c_bus->cmd_err;
> > + }
> > +
> > + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr,
> > +i2c_bus->cmd_err);
> > +
> > +controller_out:
> > + if (i2c_bus->mode == DMA_MODE) {
> > + kfree(i2c_bus->controller_dma_safe_buf);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus) {
> > + struct platform_device *pdev = to_platform_device(i2c_bus->dev);
> > + u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE |
> > +AST2600_I2CC_MASTER_EN;
> > +
> > + /* I2C Reset */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + i2c_bus->multi_master = device_property_read_bool(&pdev->dev,
> "multi-master");
> > + if (!i2c_bus->multi_master)
> > + fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
> > +
> > + /* Enable Controller Mode */
> > + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + /* disable target address */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
> > +
> > + /* Set AC Timing */
> > + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base +
> > +AST2600_I2CC_AC_TIMING);
> > +
> > + /* Clear Interrupt */
> > + writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR); }
> > +
> > +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap) {
> > + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
> > +I2C_FUNC_SMBUS_BLOCK_DATA; }
> > +
> > +static const struct i2c_algorithm i2c_ast2600_algorithm = {
> > + .xfer = ast2600_i2c_controller_xfer,
> > + .functionality = ast2600_i2c_functionality, };
> > +
> > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct ast2600_i2c_bus *i2c_bus;
> > + struct resource *res;
> > + u32 global_ctrl;
> > + int ret;
> > +
> > + i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
> > + if (!i2c_bus)
> > + return -ENOMEM;
> > +
> > + i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(i2c_bus->reg_base))
> > + return PTR_ERR(i2c_bus->reg_base);
> > +
> > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > + if (IS_ERR(i2c_bus->rst))
> > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset
> > +ctrl\n");
> > +
> > + reset_control_deassert(i2c_bus->rst);
> > +
> > + i2c_bus->global_regs =
> > + syscon_regmap_lookup_by_phandle(dev_of_node(dev),
> "aspeed,global-regs");
> > + if (IS_ERR(i2c_bus->global_regs))
> > + return PTR_ERR(i2c_bus->global_regs);
> > +
> > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
> > + if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
> > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL,
> AST2600_GLOBAL_INIT);
> > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> I2CCG_DIV_CTRL);
> > + }
> > +
> > + i2c_bus->dev = dev;
> > + i2c_bus->mode = BUFF_MODE;
> > +
> > + if (device_property_read_bool(dev, "aspeed,enable-dma"))
> > + i2c_bus->mode = DMA_MODE;
> > +
> > + if (i2c_bus->mode == BUFF_MODE) {
> > + i2c_bus->buf_base =
> devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> > + if (IS_ERR(i2c_bus->buf_base))
> > + i2c_bus->mode = BYTE_MODE;
> > + else
> > + i2c_bus->buf_size = resource_size(res) / 2;
> > + }
> > +
> > + /*
> > + * i2c timeout counter: use base clk4 1Mhz,
> > + * per unit: 1/(1000/4096) = 4096us
> > + */
> > + ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us",
> &i2c_bus->timeout);
> > + if (!ret)
> > + i2c_bus->timeout /= 4096;
> > +
> > + init_completion(&i2c_bus->cmd_complete);
> > +
> > + i2c_bus->irq = platform_get_irq(pdev, 0);
> > + if (i2c_bus->irq < 0)
> > + return i2c_bus->irq;
> > +
> > + platform_set_drvdata(pdev, i2c_bus);
> > +
> > + i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
> > + if (IS_ERR(i2c_bus->clk))
> > + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't
> > +get clock\n");
> > +
> > + i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
> > +
> > + i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
> > +
> > + /* Initialize the I2C adapter */
> > + i2c_bus->adap.owner = THIS_MODULE;
> > + i2c_bus->adap.algo = &i2c_ast2600_algorithm;
> > + i2c_bus->adap.retries = 0;
> > + i2c_bus->adap.dev.parent = i2c_bus->dev;
> > + device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
> > + i2c_bus->adap.algo_data = i2c_bus;
> > + strscpy(i2c_bus->adap.name, pdev->name);
> > + i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
> > +
> > + ast2600_i2c_init(i2c_bus);
> > +
> > + ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
> > + dev_name(dev), i2c_bus);
> > + if (ret < 0)
> > + return dev_err_probe(dev, ret, "Unable to request irq %d\n",
> > +i2c_bus->irq);
> > +
> > + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
> > + i2c_bus->reg_base + AST2600_I2CM_IER);
> > +
> > + ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static void ast2600_i2c_remove(struct platform_device *pdev) {
> > + struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
> > +
> > + /* Disable everything. */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER); }
> > +
> > +static const struct of_device_id ast2600_i2c_bus_of_table[] = {
> > + {
> > + .compatible = "aspeed,ast2600-i2cv2",
> > + },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
> > +
> > +static struct platform_driver ast2600_i2c_bus_driver = {
> > + .probe = ast2600_i2c_probe,
> > + .remove = ast2600_i2c_remove,
> > + .driver = {
> > + .name = KBUILD_MODNAME,
> > + .of_match_table = ast2600_i2c_bus_of_table,
> > + },
> > +};
> > +
> > +module_platform_driver(ast2600_i2c_bus_driver);
> > +
> > +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> > +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
> > +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-11 11:00 ` Naresh Solanki
@ 2024-11-12 7:00 ` Ryan Chen
2024-11-12 9:22 ` Naresh Solanki
0 siblings, 1 reply; 15+ messages in thread
From: Ryan Chen @ 2024-11-12 7:00 UTC (permalink / raw)
To: Naresh Solanki, brendan.higgins@linux.dev,
benh@kernel.crashing.org, joel@jms.id.au, andi.shyti@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, p.zabel@pengutronix.de,
andriy.shevchenko@linux.intel.com, linux-i2c@vger.kernel.org,
openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register
> mode driver
>
> Hi Ryan,
>
> I've tested the driver changes in my machine based on "SOC: AST2600-A3".
>
> I faced some issue testing the driver.
> While the driver functions correctly in
> Normal mode, I encountered issues when attempting to run it in DMA and
> BUFF modes. Given the instability in these modes, I suspect there may be
> misconfigurations in my device tree setup.
>
> Could you please provide a sample configuration for the device tree that would
> ensure stable operation of the driver in both DMA and BUFF modes?
>
You may refer the following dtsi.
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi#L1334-L1357
> Thank you for your support.
>
> Regards,
> Naresh
>
>
> On 07-10-2024 09:22:34, Ryan Chen wrote:
> > Add i2c new register mode driver to support AST2600 i2c new register
> > mode. AST2600 i2c controller have legacy and new register mode. The
> > new register mode have global register support 4 base clock for scl
> > clock selection, and new clock divider mode. The new register mode
> > have separate register set to control i2c controller and target. This
> > patch is for i2c controller mode driver.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> > drivers/i2c/busses/Kconfig | 11 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-ast2600.c | 1032
> ++++++++++++++++++++++++++++++
> > 3 files changed, 1044 insertions(+)
> > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index a22f9125322a..abfb027350d4 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -410,6 +410,17 @@ config I2C_ALTERA
> > This driver can also be built as a module. If so, the module
> > will be called i2c-altera.
> >
> > +config I2C_AST2600
> > + tristate "Aspeed I2C v2 Controller"
> > + depends on ARCH_ASPEED || COMPILE_TEST
> > + select I2C_SMBUS
> > + help
> > + If you say yes to this option, support will be included for the
> > + Aspeed I2C controller with new register set.
> > +
> > + This driver can also be built as a module. If so, the module
> > + will be called i2c-ast2600.
> > +
> > config I2C_ASPEED
> > tristate "Aspeed I2C Controller"
> > depends on ARCH_ASPEED || COMPILE_TEST diff --git
> > a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index
> > 78d0561339e5..5665b60b1566 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
> > obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
> > obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o
> i2c-amd-mp2-plat.o
> > obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
> > +obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
> > obj-$(CONFIG_I2C_AT91) += i2c-at91.o
> > i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
> > ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
> > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > b/drivers/i2c/busses/i2c-ast2600.c
> > new file mode 100644
> > index 000000000000..17ba0ee77c27
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > @@ -0,0 +1,1032 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * ASPEED AST2600 new register set I2C controller driver
> > + *
> > + * Copyright (C) ASPEED Technology Inc.
> > + */
> > +#include <asm/unaligned.h>
> > +#include <linux/array_size.h>
> > +#include <linux/bits.h>
> > +#include <linux/clk.h>
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/err.h>
> > +#include <linux/i2c.h>
> > +#include <linux/i2c-smbus.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/minmax.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/property.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +#include <linux/slab.h>
> > +#include <linux/string_helpers.h>
> > +
> > +#define AST2600_I2CG_ISR 0x00
> > +#define AST2600_I2CG_SLAVE_ISR 0x04
> > +#define AST2600_I2CG_OWNER 0x08
> > +#define AST2600_I2CG_CTRL 0x0C
> > +#define AST2600_I2CG_CLK_DIV_CTRL 0x10
> > +
> > +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
> > +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
> > +#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
> > +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
> > +#define AST2600_GLOBAL_INIT \
> > + (AST2600_I2CG_CTRL_NEW_REG |
> AST2600_I2CG_CTRL_NEW_CLK_DIV)
> > +/*
> > + * APB clk : 100Mhz
> > + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
> > + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter
> > +(0xC6)
> > + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
> > + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
> > + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
> > + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
> > + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
> > + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
> > + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
> > + * 0x12 : 400Khz : 10Mhz : 1.6us
> > + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
> > + * 0x08 : 1Mhz : 20Mhz : 0.8us
> > + */
> > +#define I2CCG_DIV_CTRL 0xC6411208
> > +
> > +/* 0x00 : I2CC Controller/Target Function Control Register */
> > +#define AST2600_I2CC_FUN_CTRL 0x00
> > +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
> > +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
> > +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0))
> << 18)
> > +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
> > +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
> > +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
> > +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
> > +#define AST2600_I2CC_MSB_STS BIT(9)
> > +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
> > +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
> > +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
> > +/* reserver 5 : 2 */
> > +#define AST2600_I2CC_SLAVE_EN BIT(1)
> > +#define AST2600_I2CC_MASTER_EN BIT(0)
> > +
> > +/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
> > +#define AST2600_I2CC_AC_TIMING 0x04
> > +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0))
> << 24)
> > +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0))
> << 20)
> > +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
> > +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
> > +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
> > +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1,
> 0)) << 8)
> > +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
> > +
> > +/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
> > +#define AST2600_I2CC_STS_AND_BUFF 0x08
> > +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
> > +#define AST2600_I2CC_SDA_OE BIT(28)
> > +#define AST2600_I2CC_SDA_O BIT(27)
> > +#define AST2600_I2CC_SCL_OE BIT(26)
> > +#define AST2600_I2CC_SCL_O BIT(25)
> > +
> > +#define AST2600_I2CC_SCL_LINE_STS BIT(18)
> > +#define AST2600_I2CC_SDA_LINE_STS BIT(17)
> > +#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
> > +
> > +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) &
> GENMASK(7, 0))
> > +
> > +/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
> > +#define AST2600_I2CC_BUFF_CTRL 0x0C
> > +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29,
> 24)) >> 24)
> > +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> 0)) << 16) | BIT(0))
> > +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> 0)) << 8) | BIT(0))
> > +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12,
> 8)) >> 8) + 1)
> > +
> > +/* 0x10 : I2CM Controller Interrupt Control Register */
> > +#define AST2600_I2CM_IER 0x10
> > +/* 0x14 : I2CM Controller Interrupt Status Register : WC */
> > +#define AST2600_I2CM_ISR 0x14
> > +
> > +#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
> > +#define AST2600_I2CM_PKT_ERROR BIT(17)
> > +#define AST2600_I2CM_PKT_DONE BIT(16)
> > +
> > +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
> > +#define AST2600_I2CM_SDA_DL_TO BIT(14)
> > +#define AST2600_I2CM_BUS_RECOVER BIT(13)
> > +#define AST2600_I2CM_SMBUS_ALT BIT(12)
> > +
> > +#define AST2600_I2CM_SCL_LOW_TO BIT(6)
> > +#define AST2600_I2CM_ABNORMAL BIT(5)
> > +#define AST2600_I2CM_NORMAL_STOP BIT(4)
> > +#define AST2600_I2CM_ARBIT_LOSS BIT(3)
> > +#define AST2600_I2CM_RX_DONE BIT(2)
> > +#define AST2600_I2CM_TX_NAK BIT(1)
> > +#define AST2600_I2CM_TX_ACK BIT(0)
> > +
> > +/* 0x18 : I2CM Controller Command/Status Register */
> > +#define AST2600_I2CM_CMD_STS 0x18
> > +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0))
> << 24)
> > +#define AST2600_I2CM_PKT_EN BIT(16)
> > +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
> > +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
> > +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
> > +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
> > +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
> > +
> > +#define AST2600_I2CM_RX_DMA_EN BIT(9)
> > +#define AST2600_I2CM_TX_DMA_EN BIT(8)
> > +/* Command Bit */
> > +#define AST2600_I2CM_RX_BUFF_EN BIT(7)
> > +#define AST2600_I2CM_TX_BUFF_EN BIT(6)
> > +#define AST2600_I2CM_STOP_CMD BIT(5)
> > +#define AST2600_I2CM_RX_CMD_LAST BIT(4)
> > +#define AST2600_I2CM_RX_CMD BIT(3)
> > +
> > +#define AST2600_I2CM_TX_CMD BIT(1)
> > +#define AST2600_I2CM_START_CMD BIT(0)
> > +
> > +/* 0x1C : I2CM Controller DMA Transfer Length Register */
> > +#define AST2600_I2CM_DMA_LEN 0x1C
> > +/* Tx Rx support length 1 ~ 4096 */
> > +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0))
> << 16) | BIT(31))
> > +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0))
> | BIT(15))
> > +
> > +/* 0x20 : I2CS Target Interrupt Control Register */
> > +#define AST2600_I2CS_IER 0x20
> > +/* 0x24 : I2CS Target Interrupt Status Register */
> > +#define AST2600_I2CS_ISR 0x24
> > +
> > +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
> > +#define AST2600_I2CS_SLAVE_PENDING BIT(29)
> > +
> > +#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
> > +#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
> > +
> > +#define AST2600_I2CS_ADDR3_NAK BIT(22)
> > +#define AST2600_I2CS_ADDR2_NAK BIT(21)
> > +#define AST2600_I2CS_ADDR1_NAK BIT(20)
> > +
> > +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
> > +#define AST2600_I2CS_PKT_ERROR BIT(17)
> > +#define AST2600_I2CS_PKT_DONE BIT(16)
> > +#define AST2600_I2CS_INACTIVE_TO BIT(15)
> > +
> > +#define AST2600_I2CS_SLAVE_MATCH BIT(7)
> > +#define AST2600_I2CS_ABNOR_STOP BIT(5)
> > +#define AST2600_I2CS_STOP BIT(4)
> > +#define AST2600_I2CS_RX_DONE_NAK BIT(3)
> > +#define AST2600_I2CS_RX_DONE BIT(2)
> > +#define AST2600_I2CS_TX_NAK BIT(1)
> > +#define AST2600_I2CS_TX_ACK BIT(0)
> > +
> > +/* 0x28 : I2CS Target CMD/Status Register */
> > +#define AST2600_I2CS_CMD_STS 0x28
> > +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
> > +#define AST2600_I2CS_PKT_MODE_EN BIT(16)
> > +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
> > +#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
> > +
> > +#define AST2600_I2CS_ALT_EN BIT(10)
> > +#define AST2600_I2CS_RX_DMA_EN BIT(9)
> > +#define AST2600_I2CS_TX_DMA_EN BIT(8)
> > +#define AST2600_I2CS_RX_BUFF_EN BIT(7)
> > +#define AST2600_I2CS_TX_BUFF_EN BIT(6)
> > +#define AST2600_I2CS_RX_CMD_LAST BIT(4)
> > +
> > +#define AST2600_I2CS_TX_CMD BIT(2)
> > +
> > +#define AST2600_I2CS_DMA_LEN 0x2C
> > +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0))
> << 16) | BIT(31))
> > +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0))
> | BIT(15))
> > +
> > +/* I2CM Controller DMA Tx Buffer Register */
> > +#define AST2600_I2CM_TX_DMA 0x30
> > +/* I2CM Controller DMA Rx Buffer Register */
> > +#define AST2600_I2CM_RX_DMA 0x34
> > +/* I2CS Target DMA Tx Buffer Register */
> > +#define AST2600_I2CS_TX_DMA 0x38
> > +/* I2CS Target DMA Rx Buffer Register */
> > +#define AST2600_I2CS_RX_DMA 0x3C
> > +
> > +#define AST2600_I2CS_ADDR_CTRL 0x40
> > +
> > +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
> > +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
> > +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
> > +
> > +#define AST2600_I2CM_DMA_LEN_STS 0x48
> > +#define AST2600_I2CS_DMA_LEN_STS 0x4C
> > +
> > +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
> > +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28,
> 16)) >> 16)
> > +
> > +/* 0x40 : Target Device Address Register */
> > +#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
> > +#define AST2600_I2CS_ADDR3(x) ((x) << 16)
> > +#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
> > +#define AST2600_I2CS_ADDR2(x) ((x) << 8)
> > +#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
> > +#define AST2600_I2CS_ADDR1(x) (x)
> > +
> > +#define I2C_TARGET_MSG_BUF_SIZE 256
> > +
> > +#define AST2600_I2C_DMA_SIZE 4096
> > +
> > +#define CONTROLLER_TRIGGER_LAST_STOP
> (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
> > +#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL |
> AST2600_I2CS_PKT_MODE_EN)
> > +
> > +#define AST_I2C_TIMEOUT_CLK 0x2
> > +
> > +enum xfer_mode {
> > + BYTE_MODE,
> > + BUFF_MODE,
> > + DMA_MODE,
> > +};
> > +
> > +struct ast2600_i2c_bus {
> > + struct i2c_adapter adap;
> > + struct device *dev;
> > + void __iomem *reg_base;
> > + struct regmap *global_regs;
> > + struct reset_control *rst;
> > + struct clk *clk;
> > + struct i2c_timings timing_info;
> > + struct completion cmd_complete;
> > + struct i2c_msg *msgs;
> > + u8 *controller_dma_safe_buf;
> > + dma_addr_t controller_dma_addr;
> > + u32 apb_clk;
> > + u32 timeout;
> > + int irq;
> > + int cmd_err;
> > + int msgs_index;
> > + int msgs_count;
> > + int controller_xfer_cnt;
> > + size_t buf_index;
> > + size_t buf_size;
> > + enum xfer_mode mode;
> > + bool multi_master;
> > + /* Buffer mode */
> > + void __iomem *buf_base;
> > + struct i2c_smbus_alert_setup alert_data;
> > +};
> > +
> > +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + unsigned long base_clk[16];
> > + int baseclk_idx = 0;
> > + int divisor = 0;
> > + u32 clk_div_reg;
> > + u32 scl_low;
> > + u32 scl_high;
> > + u32 data;
> > +
> > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> > +&clk_div_reg);
> > +
> > + for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
> > + if (i == 0)
> > + base_clk[i] = i2c_bus->apb_clk;
> > + else if (i < 5)
> > + base_clk[i] = (i2c_bus->apb_clk * 2) /
> > + (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
> > + else
> > + base_clk[i] = base_clk[4] >> (i - 5);
> > +
> > + if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
> > + baseclk_idx = i;
> > + divisor = DIV_ROUND_UP(base_clk[i],
> i2c_bus->timing_info.bus_freq_hz);
> > + break;
> > + }
> > + }
> > + baseclk_idx = min(baseclk_idx, 15);
> > + divisor = min(divisor, 32);
> > + scl_low = min(divisor * 9 / 16 - 1, 15);
> > + scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
> > + data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
> > + if (i2c_bus->timeout) {
> > + data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
> > + data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
> > + }
> > +
> > + return data;
> > +}
> > +
> > +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus) {
> > + u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + int ret = 0;
> > + u32 ctrl;
> > + int r;
> > +
> > + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n",
> > +i2c_bus->adap.nr, state);
> > +
> > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + /* Disable controller */
> > + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
> > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) |
> AST2600_I2CC_MASTER_EN,
> > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + reinit_completion(&i2c_bus->cmd_complete);
> > + i2c_bus->cmd_err = 0;
> > +
> > + /* Check 0x14's SDA and SCL status */
> > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state &
> AST2600_I2CC_SCL_LINE_STS)) {
> > + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base +
> AST2600_I2CM_CMD_STS);
> > + r = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> i2c_bus->adap.timeout);
> > + if (r == 0) {
> > + dev_dbg(i2c_bus->dev, "recovery timed out\n");
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + return -ETIMEDOUT;
> > + } else if (i2c_bus->cmd_err) {
> > + dev_dbg(i2c_bus->dev, "recovery error\n");
> > + ret = -EPROTO;
> > + }
> > + }
> > +
> > + /* Recovery done */
> > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + if (state & AST2600_I2CC_BUS_BUSY_STS) {
> > + dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
> > + ret = -EPROTO;
> > + }
> > +
> > + /* restore original controller setting */
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + return ret;
> > +}
> > +
> > +static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + int ret;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > AST2600_I2C_DMA_SIZE)
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD) {
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > + i2c_bus->controller_dma_safe_buf =
> i2c_get_dma_safe_msg_buf(msg, 1);
> > + if (!i2c_bus->controller_dma_safe_buf)
> > + return -ENOMEM;
> > + i2c_bus->controller_dma_addr =
> > + dma_map_single(i2c_bus->dev,
> i2c_bus->controller_dma_safe_buf,
> > + msg->len, DMA_TO_DEVICE);
> > + ret = dma_mapping_error(i2c_bus->dev,
> i2c_bus->controller_dma_addr);
> > + if (ret) {
> > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> msg, false);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + return ret;
> > + }
> > + }
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
> > + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
> > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + writel(i2c_bus->controller_dma_addr +
> i2c_bus->controller_xfer_cnt,
> > + i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 wbuf_dword;
> > + int xfer_len;
> > + int i;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > i2c_bus->buf_size)
> > + xfer_len = i2c_bus->buf_size;
> > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD)
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
> > + /*
> > + * The controller's buffer register supports dword writes only.
> > + * Therefore, write dwords to the buffer register in a 4-byte aligned,
> > + * and write the remaining unaligned data at the end.
> > + */
> > + for (i = 0; i < xfer_len; i += 4) {
> > + int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
> > +
> > + switch (min(xfer_len - i, 4) % 4) {
> > + case 1:
> > + wbuf_dword = msg->buf[xfer_cnt];
> > + break;
> > + case 2:
> > + wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
> > + break;
> > + case 3:
> > + wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
> > + break;
> > + default:
> > + wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
> > + break;
> > + }
> > + writel(wbuf_dword, i2c_bus->buf_base + i);
> > + }
> > + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
> > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > +
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > +
> > + cmd |= AST2600_I2CM_PKT_EN;
> > +
> > + if (cmd & AST2600_I2CM_START_CMD)
> > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > +
> > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
> > + cmd |= AST2600_I2CM_STOP_CMD;
> > +
> > + if (xfer_len) {
> > + cmd |= AST2600_I2CM_TX_CMD;
> > + writel(msg->buf[i2c_bus->controller_xfer_cnt],
> > + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + u32 cmd;
> > + int ret;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + xfer_len = 1;
> > + } else if (msg->len > AST2600_I2C_DMA_SIZE) {
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + } else {
> > + xfer_len = msg->len;
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg,
> 1);
> > + if (!i2c_bus->controller_dma_safe_buf)
> > + return -ENOMEM;
> > + i2c_bus->controller_dma_addr =
> > + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> > + msg->len, DMA_FROM_DEVICE);
> > + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> > + if (ret) {
> > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> msg, false);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + return ret;
> > + }
> > + writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base +
> > +AST2600_I2CM_RX_DMA);
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + int xfer_len;
> > + u32 cmd;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > + xfer_len = 1;
> > + } else if (msg->len > i2c_bus->buf_size) {
> > + xfer_len = i2c_bus->buf_size;
> > + } else {
> > + xfer_len = msg->len;
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base +
> > +AST2600_I2CC_BUFF_CTRL);
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
> > +{
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 cmd;
> > +
> > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> |
> > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > + } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
> > + if (msg->len == 1)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > +
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > +
> > + return 0;
> > +}
> > +
> > +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > +
> > + /* send start */
> > + dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
> > + i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
> > + msg->len, str_plural(msg->len),
> > + msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
> > +
> > + i2c_bus->controller_xfer_cnt = 0;
> > + i2c_bus->buf_index = 0;
> > +
> > + if (msg->flags & I2C_M_RD) {
> > + if (i2c_bus->mode == DMA_MODE)
> > + return ast2600_i2c_setup_dma_rx(i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + return ast2600_i2c_setup_buff_rx(i2c_bus);
> > + else
> > + return ast2600_i2c_setup_byte_rx(i2c_bus);
> > + } else {
> > + if (i2c_bus->mode == DMA_MODE)
> > + return
> ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD,
> i2c_bus);
> > + else
> > + return
> ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > + }
> > +}
> > +
> > +static int ast2600_i2c_irq_err_to_errno(u32 irq_status) {
> > + if (irq_status & AST2600_I2CM_ARBIT_LOSS)
> > + return -EAGAIN;
> > + if (irq_status & (AST2600_I2CM_SDA_DL_TO |
> AST2600_I2CM_SCL_LOW_TO))
> > + return -EBUSY;
> > + if (irq_status & (AST2600_I2CM_ABNORMAL))
> > + return -EPROTO;
> > +
> > + return 0;
> > +}
> > +
> > +static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus
> > +*i2c_bus, u32 sts) {
> > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > + u32 cmd = AST2600_I2CM_PKT_EN;
> > + int xfer_len;
> > + int i;
> > +
> > + sts &= ~AST2600_I2CM_PKT_DONE;
> > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + switch (sts) {
> > + case AST2600_I2CM_PKT_ERROR:
> > + i2c_bus->cmd_err = -EAGAIN;
> > + complete(&i2c_bus->cmd_complete);
> > + break;
> > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for
> issue */
> > + fallthrough;
> > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK |
> AST2600_I2CM_NORMAL_STOP:
> > + i2c_bus->cmd_err = -ENXIO;
> > + complete(&i2c_bus->cmd_complete);
> > + break;
> > + case AST2600_I2CM_NORMAL_STOP:
> > + /* write 0 byte only have stop isr */
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + } else {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + break;
> > + case AST2600_I2CM_TX_ACK:
> > + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
> > + if (i2c_bus->mode == DMA_MODE)
> > + xfer_len =
> AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CM_DMA_LEN_STS));
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + xfer_len =
> AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_BUFF_CTRL));
> > + else
> > + xfer_len = 1;
> > +
> > + i2c_bus->controller_xfer_cnt += xfer_len;
> > +
> > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > + if (i2c_bus->mode == DMA_MODE) {
> > + dma_unmap_single(i2c_bus->dev,
> i2c_bus->controller_dma_addr,
> > + msg->len, DMA_TO_DEVICE);
> > +
> i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > + msg, true);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + } else {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + }
> > + } else {
> > + if (i2c_bus->mode == DMA_MODE)
> > + ast2600_i2c_setup_dma_tx(0, i2c_bus);
> > + else if (i2c_bus->mode == BUFF_MODE)
> > + ast2600_i2c_setup_buff_tx(0, i2c_bus);
> > + else
> > + ast2600_i2c_setup_byte_tx(0, i2c_bus);
> > + }
> > + break;
> > + case AST2600_I2CM_RX_DONE:
> > + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
> > + /* do next rx */
> > + if (i2c_bus->mode == DMA_MODE) {
> > + xfer_len =
> AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CM_DMA_LEN_STS));
> > + } else if (i2c_bus->mode == BUFF_MODE) {
> > + xfer_len =
> AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_BUFF_CTRL));
> > + for (i = 0; i < xfer_len; i++)
> > + msg->buf[i2c_bus->controller_xfer_cnt + i] =
> > + readb(i2c_bus->buf_base + 0x10 + i);
> > + } else {
> > + xfer_len = 1;
> > + msg->buf[i2c_bus->controller_xfer_cnt] =
> > + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
> > + AST2600_I2CC_STS_AND_BUFF));
> > + }
> > +
> > + if (msg->flags & I2C_M_RECV_LEN) {
> > + msg->len = min_t(unsigned int, msg->buf[0],
> I2C_SMBUS_BLOCK_MAX);
> > + msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
> > + msg->flags &= ~I2C_M_RECV_LEN;
> > + }
> > + i2c_bus->controller_xfer_cnt += xfer_len;
> > +
> > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > + if (i2c_bus->mode == DMA_MODE) {
> > + dma_unmap_single(i2c_bus->dev,
> i2c_bus->controller_dma_addr,
> > + msg->len, DMA_FROM_DEVICE);
> > +
> i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > + msg, true);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > +
> > + i2c_bus->msgs_index++;
> > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > + complete(&i2c_bus->cmd_complete);
> > + } else {
> > + if (ast2600_i2c_do_start(i2c_bus)) {
> > + i2c_bus->cmd_err = -ENOMEM;
> > + complete(&i2c_bus->cmd_complete);
> > + }
> > + }
> > + } else {
> > + /* next rx */
> > + cmd |= AST2600_I2CM_RX_CMD;
> > + if (i2c_bus->mode == DMA_MODE) {
> > + cmd |= AST2600_I2CM_RX_DMA_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > AST2600_I2C_DMA_SIZE) {
> > + xfer_len = AST2600_I2C_DMA_SIZE;
> > + } else {
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > + writel(i2c_bus->controller_dma_addr +
> i2c_bus->controller_xfer_cnt,
> > + i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> > + } else if (i2c_bus->mode == BUFF_MODE) {
> > + cmd |= AST2600_I2CM_RX_BUFF_EN;
> > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > + if (xfer_len > i2c_bus->buf_size) {
> > + xfer_len = i2c_bus->buf_size;
> > + } else {
> > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
> > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > + } else {
> > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
> > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > + }
> > + }
> > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > + }
> > + break;
> > + default:
> > + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
> > + break;
> > + }
> > +}
> > +
> > +static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus
> > +*i2c_bus) {
> > + u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
> > + u32 ctrl;
> > +
> > + sts &= ~AST2600_I2CM_SMBUS_ALT;
> > +
> > + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
> > + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + i2c_bus->cmd_err = -EPROTO;
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + if (AST2600_I2CM_BUS_RECOVER & sts) {
> > + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + i2c_bus->cmd_err = 0;
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
> > + if (i2c_bus->cmd_err) {
> > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> AST2600_I2CM_ISR);
> > + complete(&i2c_bus->cmd_complete);
> > + return 1;
> > + }
> > +
> > + if (AST2600_I2CM_PKT_DONE & sts) {
> > + ast2600_i2c_controller_package_irq(i2c_bus, sts);
> > + return 1;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id) {
> > + struct ast2600_i2c_bus *i2c_bus = dev_id;
> > +
> > + return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
> > +}
> > +
> > +static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap,
> > +struct i2c_msg *msgs, int num) {
> > + struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
> > + unsigned long timeout;
> > + int ret;
> > +
> > + if (!i2c_bus->multi_master &&
> > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> AST2600_I2CC_BUS_BUSY_STS)) {
> > + ret = ast2600_i2c_recover_bus(i2c_bus);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + i2c_bus->cmd_err = 0;
> > + i2c_bus->msgs = msgs;
> > + i2c_bus->msgs_index = 0;
> > + i2c_bus->msgs_count = num;
> > + reinit_completion(&i2c_bus->cmd_complete);
> > + ret = ast2600_i2c_do_start(i2c_bus);
> > + if (ret)
> > + goto controller_out;
> > + timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> i2c_bus->adap.timeout);
> > + if (timeout == 0) {
> > + u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
> > + readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
> > + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + if (i2c_bus->multi_master &&
> > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> > + AST2600_I2CC_BUS_BUSY_STS))
> > + ast2600_i2c_recover_bus(i2c_bus);
> > +
> > + ret = -ETIMEDOUT;
> > + } else {
> > + ret = i2c_bus->cmd_err;
> > + }
> > +
> > + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr,
> > +i2c_bus->cmd_err);
> > +
> > +controller_out:
> > + if (i2c_bus->mode == DMA_MODE) {
> > + kfree(i2c_bus->controller_dma_safe_buf);
> > + i2c_bus->controller_dma_safe_buf = NULL;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus) {
> > + struct platform_device *pdev = to_platform_device(i2c_bus->dev);
> > + u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE |
> > +AST2600_I2CC_MASTER_EN;
> > +
> > + /* I2C Reset */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > +
> > + i2c_bus->multi_master = device_property_read_bool(&pdev->dev,
> "multi-master");
> > + if (!i2c_bus->multi_master)
> > + fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
> > +
> > + /* Enable Controller Mode */
> > + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + /* disable target address */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
> > +
> > + /* Set AC Timing */
> > + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base +
> > +AST2600_I2CC_AC_TIMING);
> > +
> > + /* Clear Interrupt */
> > + writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR); }
> > +
> > +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap) {
> > + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
> > +I2C_FUNC_SMBUS_BLOCK_DATA; }
> > +
> > +static const struct i2c_algorithm i2c_ast2600_algorithm = {
> > + .xfer = ast2600_i2c_controller_xfer,
> > + .functionality = ast2600_i2c_functionality, };
> > +
> > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct ast2600_i2c_bus *i2c_bus;
> > + struct resource *res;
> > + u32 global_ctrl;
> > + int ret;
> > +
> > + i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
> > + if (!i2c_bus)
> > + return -ENOMEM;
> > +
> > + i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(i2c_bus->reg_base))
> > + return PTR_ERR(i2c_bus->reg_base);
> > +
> > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > + if (IS_ERR(i2c_bus->rst))
> > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset
> > +ctrl\n");
> > +
> > + reset_control_deassert(i2c_bus->rst);
> > +
> > + i2c_bus->global_regs =
> > + syscon_regmap_lookup_by_phandle(dev_of_node(dev),
> "aspeed,global-regs");
> > + if (IS_ERR(i2c_bus->global_regs))
> > + return PTR_ERR(i2c_bus->global_regs);
> > +
> > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
> > + if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
> > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL,
> AST2600_GLOBAL_INIT);
> > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> I2CCG_DIV_CTRL);
> > + }
> > +
> > + i2c_bus->dev = dev;
> > + i2c_bus->mode = BUFF_MODE;
> > +
> > + if (device_property_read_bool(dev, "aspeed,enable-dma"))
> > + i2c_bus->mode = DMA_MODE;
> > +
> > + if (i2c_bus->mode == BUFF_MODE) {
> > + i2c_bus->buf_base =
> devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> > + if (IS_ERR(i2c_bus->buf_base))
> > + i2c_bus->mode = BYTE_MODE;
> > + else
> > + i2c_bus->buf_size = resource_size(res) / 2;
> > + }
> > +
> > + /*
> > + * i2c timeout counter: use base clk4 1Mhz,
> > + * per unit: 1/(1000/4096) = 4096us
> > + */
> > + ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us",
> &i2c_bus->timeout);
> > + if (!ret)
> > + i2c_bus->timeout /= 4096;
> > +
> > + init_completion(&i2c_bus->cmd_complete);
> > +
> > + i2c_bus->irq = platform_get_irq(pdev, 0);
> > + if (i2c_bus->irq < 0)
> > + return i2c_bus->irq;
> > +
> > + platform_set_drvdata(pdev, i2c_bus);
> > +
> > + i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
> > + if (IS_ERR(i2c_bus->clk))
> > + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't
> > +get clock\n");
> > +
> > + i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
> > +
> > + i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
> > +
> > + /* Initialize the I2C adapter */
> > + i2c_bus->adap.owner = THIS_MODULE;
> > + i2c_bus->adap.algo = &i2c_ast2600_algorithm;
> > + i2c_bus->adap.retries = 0;
> > + i2c_bus->adap.dev.parent = i2c_bus->dev;
> > + device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
> > + i2c_bus->adap.algo_data = i2c_bus;
> > + strscpy(i2c_bus->adap.name, pdev->name);
> > + i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
> > +
> > + ast2600_i2c_init(i2c_bus);
> > +
> > + ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
> > + dev_name(dev), i2c_bus);
> > + if (ret < 0)
> > + return dev_err_probe(dev, ret, "Unable to request irq %d\n",
> > +i2c_bus->irq);
> > +
> > + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
> > + i2c_bus->reg_base + AST2600_I2CM_IER);
> > +
> > + ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static void ast2600_i2c_remove(struct platform_device *pdev) {
> > + struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
> > +
> > + /* Disable everything. */
> > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER); }
> > +
> > +static const struct of_device_id ast2600_i2c_bus_of_table[] = {
> > + {
> > + .compatible = "aspeed,ast2600-i2cv2",
> > + },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
> > +
> > +static struct platform_driver ast2600_i2c_bus_driver = {
> > + .probe = ast2600_i2c_probe,
> > + .remove = ast2600_i2c_remove,
> > + .driver = {
> > + .name = KBUILD_MODNAME,
> > + .of_match_table = ast2600_i2c_bus_of_table,
> > + },
> > +};
> > +
> > +module_platform_driver(ast2600_i2c_bus_driver);
> > +
> > +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> > +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
> > +MODULE_LICENSE("GPL");
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-12 7:00 ` Ryan Chen
@ 2024-11-12 9:22 ` Naresh Solanki
0 siblings, 0 replies; 15+ messages in thread
From: Naresh Solanki @ 2024-11-12 9:22 UTC (permalink / raw)
To: Ryan Chen
Cc: brendan.higgins@linux.dev, benh@kernel.crashing.org,
joel@jms.id.au, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, p.zabel@pengutronix.de,
andriy.shevchenko@linux.intel.com, linux-i2c@vger.kernel.org,
openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Hi Ryan,
On Tue, 12 Nov 2024 at 12:30, Ryan Chen <ryan_chen@aspeedtech.com> wrote:
>
> > Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register
> > mode driver
> >
> > Hi Ryan,
> >
> > I've tested the driver changes in my machine based on "SOC: AST2600-A3".
> >
> > I faced some issue testing the driver.
> > While the driver functions correctly in
> > Normal mode, I encountered issues when attempting to run it in DMA and
> > BUFF modes. Given the instability in these modes, I suspect there may be
> > misconfigurations in my device tree setup.
> >
> > Could you please provide a sample configuration for the device tree that would
> > ensure stable operation of the driver in both DMA and BUFF modes?
> >
> You may refer the following dtsi.
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi#L1334-L1357
That worked for me. Thanks a ton :)
Regards,
Naresh
>
> > Thank you for your support.
> >
> > Regards,
> > Naresh
> >
> >
> > On 07-10-2024 09:22:34, Ryan Chen wrote:
> > > Add i2c new register mode driver to support AST2600 i2c new register
> > > mode. AST2600 i2c controller have legacy and new register mode. The
> > > new register mode have global register support 4 base clock for scl
> > > clock selection, and new clock divider mode. The new register mode
> > > have separate register set to control i2c controller and target. This
> > > patch is for i2c controller mode driver.
> > >
> > > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > > ---
> > > drivers/i2c/busses/Kconfig | 11 +
> > > drivers/i2c/busses/Makefile | 1 +
> > > drivers/i2c/busses/i2c-ast2600.c | 1032
> > ++++++++++++++++++++++++++++++
> > > 3 files changed, 1044 insertions(+)
> > > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> > >
> > > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > > index a22f9125322a..abfb027350d4 100644
> > > --- a/drivers/i2c/busses/Kconfig
> > > +++ b/drivers/i2c/busses/Kconfig
> > > @@ -410,6 +410,17 @@ config I2C_ALTERA
> > > This driver can also be built as a module. If so, the module
> > > will be called i2c-altera.
> > >
> > > +config I2C_AST2600
> > > + tristate "Aspeed I2C v2 Controller"
> > > + depends on ARCH_ASPEED || COMPILE_TEST
> > > + select I2C_SMBUS
> > > + help
> > > + If you say yes to this option, support will be included for the
> > > + Aspeed I2C controller with new register set.
> > > +
> > > + This driver can also be built as a module. If so, the module
> > > + will be called i2c-ast2600.
> > > +
> > > config I2C_ASPEED
> > > tristate "Aspeed I2C Controller"
> > > depends on ARCH_ASPEED || COMPILE_TEST diff --git
> > > a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index
> > > 78d0561339e5..5665b60b1566 100644
> > > --- a/drivers/i2c/busses/Makefile
> > > +++ b/drivers/i2c/busses/Makefile
> > > @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
> > > obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
> > > obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o
> > i2c-amd-mp2-plat.o
> > > obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
> > > +obj-$(CONFIG_I2C_AST2600) += i2c-ast2600.o
> > > obj-$(CONFIG_I2C_AT91) += i2c-at91.o
> > > i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
> > > ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
> > > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > > b/drivers/i2c/busses/i2c-ast2600.c
> > > new file mode 100644
> > > index 000000000000..17ba0ee77c27
> > > --- /dev/null
> > > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > > @@ -0,0 +1,1032 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * ASPEED AST2600 new register set I2C controller driver
> > > + *
> > > + * Copyright (C) ASPEED Technology Inc.
> > > + */
> > > +#include <asm/unaligned.h>
> > > +#include <linux/array_size.h>
> > > +#include <linux/bits.h>
> > > +#include <linux/clk.h>
> > > +#include <linux/completion.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/err.h>
> > > +#include <linux/i2c.h>
> > > +#include <linux/i2c-smbus.h>
> > > +#include <linux/interrupt.h>
> > > +#include <linux/io.h>
> > > +#include <linux/minmax.h>
> > > +#include <linux/mfd/syscon.h>
> > > +#include <linux/module.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/property.h>
> > > +#include <linux/regmap.h>
> > > +#include <linux/reset.h>
> > > +#include <linux/slab.h>
> > > +#include <linux/string_helpers.h>
> > > +
> > > +#define AST2600_I2CG_ISR 0x00
> > > +#define AST2600_I2CG_SLAVE_ISR 0x04
> > > +#define AST2600_I2CG_OWNER 0x08
> > > +#define AST2600_I2CG_CTRL 0x0C
> > > +#define AST2600_I2CG_CLK_DIV_CTRL 0x10
> > > +
> > > +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4)
> > > +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3)
> > > +#define AST2600_I2CG_CTRL_NEW_REG BIT(2)
> > > +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1)
> > > +#define AST2600_GLOBAL_INIT \
> > > + (AST2600_I2CG_CTRL_NEW_REG |
> > AST2600_I2CG_CTRL_NEW_CLK_DIV)
> > > +/*
> > > + * APB clk : 100Mhz
> > > + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16]
> > > + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter
> > > +(0xC6)
> > > + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
> > > + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
> > > + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
> > > + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
> > > + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
> > > + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
> > > + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
> > > + * 0x12 : 400Khz : 10Mhz : 1.6us
> > > + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
> > > + * 0x08 : 1Mhz : 20Mhz : 0.8us
> > > + */
> > > +#define I2CCG_DIV_CTRL 0xC6411208
> > > +
> > > +/* 0x00 : I2CC Controller/Target Function Control Register */
> > > +#define AST2600_I2CC_FUN_CTRL 0x00
> > > +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20)
> > > +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18)
> > > +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0))
> > << 18)
> > > +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17)
> > > +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16)
> > > +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15)
> > > +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14)
> > > +#define AST2600_I2CC_MSB_STS BIT(9)
> > > +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8)
> > > +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7)
> > > +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6)
> > > +/* reserver 5 : 2 */
> > > +#define AST2600_I2CC_SLAVE_EN BIT(1)
> > > +#define AST2600_I2CC_MASTER_EN BIT(0)
> > > +
> > > +/* 0x04 : I2CC Controller/Target Clock and AC Timing Control Register #1 */
> > > +#define AST2600_I2CC_AC_TIMING 0x04
> > > +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0))
> > << 24)
> > > +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0))
> > << 20)
> > > +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16)
> > > +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12)
> > > +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10)
> > > +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1,
> > 0)) << 8)
> > > +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0))
> > > +
> > > +/* 0x08 : I2CC Controller/Target Transmit/Receive Byte Buffer Register */
> > > +#define AST2600_I2CC_STS_AND_BUFF 0x08
> > > +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29)
> > > +#define AST2600_I2CC_SDA_OE BIT(28)
> > > +#define AST2600_I2CC_SDA_O BIT(27)
> > > +#define AST2600_I2CC_SCL_OE BIT(26)
> > > +#define AST2600_I2CC_SCL_O BIT(25)
> > > +
> > > +#define AST2600_I2CC_SCL_LINE_STS BIT(18)
> > > +#define AST2600_I2CC_SDA_LINE_STS BIT(17)
> > > +#define AST2600_I2CC_BUS_BUSY_STS BIT(16)
> > > +
> > > +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) &
> > GENMASK(7, 0))
> > > +
> > > +/* 0x0C : I2CC Controller/Target Pool Buffer Control Register */
> > > +#define AST2600_I2CC_BUFF_CTRL 0x0C
> > > +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) & GENMASK(29,
> > 24)) >> 24)
> > > +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> > 0)) << 16) | BIT(0))
> > > +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4,
> > 0)) << 8) | BIT(0))
> > > +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) & GENMASK(12,
> > 8)) >> 8) + 1)
> > > +
> > > +/* 0x10 : I2CM Controller Interrupt Control Register */
> > > +#define AST2600_I2CM_IER 0x10
> > > +/* 0x14 : I2CM Controller Interrupt Status Register : WC */
> > > +#define AST2600_I2CM_ISR 0x14
> > > +
> > > +#define AST2600_I2CM_PKT_TIMEOUT BIT(18)
> > > +#define AST2600_I2CM_PKT_ERROR BIT(17)
> > > +#define AST2600_I2CM_PKT_DONE BIT(16)
> > > +
> > > +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15)
> > > +#define AST2600_I2CM_SDA_DL_TO BIT(14)
> > > +#define AST2600_I2CM_BUS_RECOVER BIT(13)
> > > +#define AST2600_I2CM_SMBUS_ALT BIT(12)
> > > +
> > > +#define AST2600_I2CM_SCL_LOW_TO BIT(6)
> > > +#define AST2600_I2CM_ABNORMAL BIT(5)
> > > +#define AST2600_I2CM_NORMAL_STOP BIT(4)
> > > +#define AST2600_I2CM_ARBIT_LOSS BIT(3)
> > > +#define AST2600_I2CM_RX_DONE BIT(2)
> > > +#define AST2600_I2CM_TX_NAK BIT(1)
> > > +#define AST2600_I2CM_TX_ACK BIT(0)
> > > +
> > > +/* 0x18 : I2CM Controller Command/Status Register */
> > > +#define AST2600_I2CM_CMD_STS 0x18
> > > +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0))
> > << 24)
> > > +#define AST2600_I2CM_PKT_EN BIT(16)
> > > +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15)
> > > +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14)
> > > +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13)
> > > +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12)
> > > +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11)
> > > +
> > > +#define AST2600_I2CM_RX_DMA_EN BIT(9)
> > > +#define AST2600_I2CM_TX_DMA_EN BIT(8)
> > > +/* Command Bit */
> > > +#define AST2600_I2CM_RX_BUFF_EN BIT(7)
> > > +#define AST2600_I2CM_TX_BUFF_EN BIT(6)
> > > +#define AST2600_I2CM_STOP_CMD BIT(5)
> > > +#define AST2600_I2CM_RX_CMD_LAST BIT(4)
> > > +#define AST2600_I2CM_RX_CMD BIT(3)
> > > +
> > > +#define AST2600_I2CM_TX_CMD BIT(1)
> > > +#define AST2600_I2CM_START_CMD BIT(0)
> > > +
> > > +/* 0x1C : I2CM Controller DMA Transfer Length Register */
> > > +#define AST2600_I2CM_DMA_LEN 0x1C
> > > +/* Tx Rx support length 1 ~ 4096 */
> > > +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0))
> > << 16) | BIT(31))
> > > +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0))
> > | BIT(15))
> > > +
> > > +/* 0x20 : I2CS Target Interrupt Control Register */
> > > +#define AST2600_I2CS_IER 0x20
> > > +/* 0x24 : I2CS Target Interrupt Status Register */
> > > +#define AST2600_I2CS_ISR 0x24
> > > +
> > > +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30)
> > > +#define AST2600_I2CS_SLAVE_PENDING BIT(29)
> > > +
> > > +#define AST2600_I2CS_WAIT_TX_DMA BIT(25)
> > > +#define AST2600_I2CS_WAIT_RX_DMA BIT(24)
> > > +
> > > +#define AST2600_I2CS_ADDR3_NAK BIT(22)
> > > +#define AST2600_I2CS_ADDR2_NAK BIT(21)
> > > +#define AST2600_I2CS_ADDR1_NAK BIT(20)
> > > +
> > > +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18)
> > > +#define AST2600_I2CS_PKT_ERROR BIT(17)
> > > +#define AST2600_I2CS_PKT_DONE BIT(16)
> > > +#define AST2600_I2CS_INACTIVE_TO BIT(15)
> > > +
> > > +#define AST2600_I2CS_SLAVE_MATCH BIT(7)
> > > +#define AST2600_I2CS_ABNOR_STOP BIT(5)
> > > +#define AST2600_I2CS_STOP BIT(4)
> > > +#define AST2600_I2CS_RX_DONE_NAK BIT(3)
> > > +#define AST2600_I2CS_RX_DONE BIT(2)
> > > +#define AST2600_I2CS_TX_NAK BIT(1)
> > > +#define AST2600_I2CS_TX_ACK BIT(0)
> > > +
> > > +/* 0x28 : I2CS Target CMD/Status Register */
> > > +#define AST2600_I2CS_CMD_STS 0x28
> > > +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17)
> > > +#define AST2600_I2CS_PKT_MODE_EN BIT(16)
> > > +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15)
> > > +#define AST2600_I2CS_AUTO_NAK_EN BIT(14)
> > > +
> > > +#define AST2600_I2CS_ALT_EN BIT(10)
> > > +#define AST2600_I2CS_RX_DMA_EN BIT(9)
> > > +#define AST2600_I2CS_TX_DMA_EN BIT(8)
> > > +#define AST2600_I2CS_RX_BUFF_EN BIT(7)
> > > +#define AST2600_I2CS_TX_BUFF_EN BIT(6)
> > > +#define AST2600_I2CS_RX_CMD_LAST BIT(4)
> > > +
> > > +#define AST2600_I2CS_TX_CMD BIT(2)
> > > +
> > > +#define AST2600_I2CS_DMA_LEN 0x2C
> > > +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0))
> > << 16) | BIT(31))
> > > +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0))
> > | BIT(15))
> > > +
> > > +/* I2CM Controller DMA Tx Buffer Register */
> > > +#define AST2600_I2CM_TX_DMA 0x30
> > > +/* I2CM Controller DMA Rx Buffer Register */
> > > +#define AST2600_I2CM_RX_DMA 0x34
> > > +/* I2CS Target DMA Tx Buffer Register */
> > > +#define AST2600_I2CS_TX_DMA 0x38
> > > +/* I2CS Target DMA Rx Buffer Register */
> > > +#define AST2600_I2CS_RX_DMA 0x3C
> > > +
> > > +#define AST2600_I2CS_ADDR_CTRL 0x40
> > > +
> > > +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16)
> > > +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8)
> > > +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0)
> > > +
> > > +#define AST2600_I2CM_DMA_LEN_STS 0x48
> > > +#define AST2600_I2CS_DMA_LEN_STS 0x4C
> > > +
> > > +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0))
> > > +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) & GENMASK(28,
> > 16)) >> 16)
> > > +
> > > +/* 0x40 : Target Device Address Register */
> > > +#define AST2600_I2CS_ADDR3_ENABLE BIT(23)
> > > +#define AST2600_I2CS_ADDR3(x) ((x) << 16)
> > > +#define AST2600_I2CS_ADDR2_ENABLE BIT(15)
> > > +#define AST2600_I2CS_ADDR2(x) ((x) << 8)
> > > +#define AST2600_I2CS_ADDR1_ENABLE BIT(7)
> > > +#define AST2600_I2CS_ADDR1(x) (x)
> > > +
> > > +#define I2C_TARGET_MSG_BUF_SIZE 256
> > > +
> > > +#define AST2600_I2C_DMA_SIZE 4096
> > > +
> > > +#define CONTROLLER_TRIGGER_LAST_STOP
> > (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_STOP_CMD)
> > > +#define TARGET_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL |
> > AST2600_I2CS_PKT_MODE_EN)
> > > +
> > > +#define AST_I2C_TIMEOUT_CLK 0x2
> > > +
> > > +enum xfer_mode {
> > > + BYTE_MODE,
> > > + BUFF_MODE,
> > > + DMA_MODE,
> > > +};
> > > +
> > > +struct ast2600_i2c_bus {
> > > + struct i2c_adapter adap;
> > > + struct device *dev;
> > > + void __iomem *reg_base;
> > > + struct regmap *global_regs;
> > > + struct reset_control *rst;
> > > + struct clk *clk;
> > > + struct i2c_timings timing_info;
> > > + struct completion cmd_complete;
> > > + struct i2c_msg *msgs;
> > > + u8 *controller_dma_safe_buf;
> > > + dma_addr_t controller_dma_addr;
> > > + u32 apb_clk;
> > > + u32 timeout;
> > > + int irq;
> > > + int cmd_err;
> > > + int msgs_index;
> > > + int msgs_count;
> > > + int controller_xfer_cnt;
> > > + size_t buf_index;
> > > + size_t buf_size;
> > > + enum xfer_mode mode;
> > > + bool multi_master;
> > > + /* Buffer mode */
> > > + void __iomem *buf_base;
> > > + struct i2c_smbus_alert_setup alert_data;
> > > +};
> > > +
> > > +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus)
> > > +{
> > > + unsigned long base_clk[16];
> > > + int baseclk_idx = 0;
> > > + int divisor = 0;
> > > + u32 clk_div_reg;
> > > + u32 scl_low;
> > > + u32 scl_high;
> > > + u32 data;
> > > +
> > > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> > > +&clk_div_reg);
> > > +
> > > + for (int i = 0; i < ARRAY_SIZE(base_clk); i++) {
> > > + if (i == 0)
> > > + base_clk[i] = i2c_bus->apb_clk;
> > > + else if (i < 5)
> > > + base_clk[i] = (i2c_bus->apb_clk * 2) /
> > > + (((clk_div_reg >> ((i - 1) * 8)) & GENMASK(7, 0)) + 2);
> > > + else
> > > + base_clk[i] = base_clk[4] >> (i - 5);
> > > +
> > > + if ((base_clk[i] / i2c_bus->timing_info.bus_freq_hz) <= 32) {
> > > + baseclk_idx = i;
> > > + divisor = DIV_ROUND_UP(base_clk[i],
> > i2c_bus->timing_info.bus_freq_hz);
> > > + break;
> > > + }
> > > + }
> > > + baseclk_idx = min(baseclk_idx, 15);
> > > + divisor = min(divisor, 32);
> > > + scl_low = min(divisor * 9 / 16 - 1, 15);
> > > + scl_high = (divisor - scl_low - 2) & GENMASK(3, 0);
> > > + data = (scl_high - 1) << 20 | scl_high << 16 | scl_low << 12 | baseclk_idx;
> > > + if (i2c_bus->timeout) {
> > > + data |= AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK);
> > > + data |= AST2600_I2CC_TTIMEOUT(i2c_bus->timeout);
> > > + }
> > > +
> > > + return data;
> > > +}
> > > +
> > > +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus) {
> > > + u32 state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > > + int ret = 0;
> > > + u32 ctrl;
> > > + int r;
> > > +
> > > + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n",
> > > +i2c_bus->adap.nr, state);
> > > +
> > > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + /* Disable controller */
> > > + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN),
> > > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) |
> > AST2600_I2CC_MASTER_EN,
> > > + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + reinit_completion(&i2c_bus->cmd_complete);
> > > + i2c_bus->cmd_err = 0;
> > > +
> > > + /* Check 0x14's SDA and SCL status */
> > > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > > + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state &
> > AST2600_I2CC_SCL_LINE_STS)) {
> > > + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base +
> > AST2600_I2CM_CMD_STS);
> > > + r = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> > i2c_bus->adap.timeout);
> > > + if (r == 0) {
> > > + dev_dbg(i2c_bus->dev, "recovery timed out\n");
> > > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + return -ETIMEDOUT;
> > > + } else if (i2c_bus->cmd_err) {
> > > + dev_dbg(i2c_bus->dev, "recovery error\n");
> > > + ret = -EPROTO;
> > > + }
> > > + }
> > > +
> > > + /* Recovery done */
> > > + state = readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > > + if (state & AST2600_I2CC_BUS_BUSY_STS) {
> > > + dev_dbg(i2c_bus->dev, "Can't recover bus [%x]\n", state);
> > > + ret = -EPROTO;
> > > + }
> > > +
> > > + /* restore original controller setting */
> > > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + return ret;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_dma_tx(u32 cmd, struct ast2600_i2c_bus
> > > +*i2c_bus) {
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + int xfer_len;
> > > + int ret;
> > > +
> > > + cmd |= AST2600_I2CM_PKT_EN;
> > > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > > + if (xfer_len > AST2600_I2C_DMA_SIZE)
> > > + xfer_len = AST2600_I2C_DMA_SIZE;
> > > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= AST2600_I2CM_STOP_CMD;
> > > +
> > > + if (cmd & AST2600_I2CM_START_CMD) {
> > > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > > + i2c_bus->controller_dma_safe_buf =
> > i2c_get_dma_safe_msg_buf(msg, 1);
> > > + if (!i2c_bus->controller_dma_safe_buf)
> > > + return -ENOMEM;
> > > + i2c_bus->controller_dma_addr =
> > > + dma_map_single(i2c_bus->dev,
> > i2c_bus->controller_dma_safe_buf,
> > > + msg->len, DMA_TO_DEVICE);
> > > + ret = dma_mapping_error(i2c_bus->dev,
> > i2c_bus->controller_dma_addr);
> > > + if (ret) {
> > > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > msg, false);
> > > + i2c_bus->controller_dma_safe_buf = NULL;
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + if (xfer_len) {
> > > + cmd |= AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD;
> > > + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1),
> > > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > > + writel(i2c_bus->controller_dma_addr +
> > i2c_bus->controller_xfer_cnt,
> > > + i2c_bus->reg_base + AST2600_I2CM_TX_DMA);
> > > + }
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_buff_tx(u32 cmd, struct ast2600_i2c_bus
> > > +*i2c_bus) {
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + u32 wbuf_dword;
> > > + int xfer_len;
> > > + int i;
> > > +
> > > + cmd |= AST2600_I2CM_PKT_EN;
> > > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > > + if (xfer_len > i2c_bus->buf_size)
> > > + xfer_len = i2c_bus->buf_size;
> > > + else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= AST2600_I2CM_STOP_CMD;
> > > +
> > > + if (cmd & AST2600_I2CM_START_CMD)
> > > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > > +
> > > + if (xfer_len) {
> > > + cmd |= AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD;
> > > + /*
> > > + * The controller's buffer register supports dword writes only.
> > > + * Therefore, write dwords to the buffer register in a 4-byte aligned,
> > > + * and write the remaining unaligned data at the end.
> > > + */
> > > + for (i = 0; i < xfer_len; i += 4) {
> > > + int xfer_cnt = i2c_bus->controller_xfer_cnt + i;
> > > +
> > > + switch (min(xfer_len - i, 4) % 4) {
> > > + case 1:
> > > + wbuf_dword = msg->buf[xfer_cnt];
> > > + break;
> > > + case 2:
> > > + wbuf_dword = get_unaligned_le16(&msg->buf[xfer_cnt]);
> > > + break;
> > > + case 3:
> > > + wbuf_dword = get_unaligned_le24(&msg->buf[xfer_cnt]);
> > > + break;
> > > + default:
> > > + wbuf_dword = get_unaligned_le32(&msg->buf[xfer_cnt]);
> > > + break;
> > > + }
> > > + writel(wbuf_dword, i2c_bus->buf_base + i);
> > > + }
> > > + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len),
> > > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > > + }
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_byte_tx(u32 cmd, struct ast2600_i2c_bus
> > > +*i2c_bus) {
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + int xfer_len;
> > > +
> > > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > > +
> > > + cmd |= AST2600_I2CM_PKT_EN;
> > > +
> > > + if (cmd & AST2600_I2CM_START_CMD)
> > > + cmd |= AST2600_I2CM_PKT_ADDR(msg->addr);
> > > +
> > > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len))
> > > + cmd |= AST2600_I2CM_STOP_CMD;
> > > +
> > > + if (xfer_len) {
> > > + cmd |= AST2600_I2CM_TX_CMD;
> > > + writel(msg->buf[i2c_bus->controller_xfer_cnt],
> > > + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF);
> > > + }
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_dma_rx(struct ast2600_i2c_bus *i2c_bus)
> > > +{
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + int xfer_len;
> > > + u32 cmd;
> > > + int ret;
> > > +
> > > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> > |
> > > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_DMA_EN;
> > > +
> > > + if (msg->flags & I2C_M_RECV_LEN) {
> > > + xfer_len = 1;
> > > + } else if (msg->len > AST2600_I2C_DMA_SIZE) {
> > > + xfer_len = AST2600_I2C_DMA_SIZE;
> > > + } else {
> > > + xfer_len = msg->len;
> > > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> > i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > > + i2c_bus->controller_dma_safe_buf = i2c_get_dma_safe_msg_buf(msg,
> > 1);
> > > + if (!i2c_bus->controller_dma_safe_buf)
> > > + return -ENOMEM;
> > > + i2c_bus->controller_dma_addr =
> > > + dma_map_single(i2c_bus->dev, i2c_bus->controller_dma_safe_buf,
> > > + msg->len, DMA_FROM_DEVICE);
> > > + ret = dma_mapping_error(i2c_bus->dev, i2c_bus->controller_dma_addr);
> > > + if (ret) {
> > > + i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > msg, false);
> > > + i2c_bus->controller_dma_safe_buf = NULL;
> > > + return ret;
> > > + }
> > > + writel(i2c_bus->controller_dma_addr, i2c_bus->reg_base +
> > > +AST2600_I2CM_RX_DMA);
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_buff_rx(struct ast2600_i2c_bus *i2c_bus)
> > > +{
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + int xfer_len;
> > > + u32 cmd;
> > > +
> > > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> > |
> > > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_BUFF_EN;
> > > +
> > > + if (msg->flags & I2C_M_RECV_LEN) {
> > > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > > + xfer_len = 1;
> > > + } else if (msg->len > i2c_bus->buf_size) {
> > > + xfer_len = i2c_bus->buf_size;
> > > + } else {
> > > + xfer_len = msg->len;
> > > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), i2c_bus->reg_base +
> > > +AST2600_I2CC_BUFF_CTRL);
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_setup_byte_rx(struct ast2600_i2c_bus *i2c_bus)
> > > +{
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + u32 cmd;
> > > +
> > > + cmd = AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr)
> > |
> > > + AST2600_I2CM_START_CMD | AST2600_I2CM_RX_CMD;
> > > +
> > > + if (msg->flags & I2C_M_RECV_LEN) {
> > > + dev_dbg(i2c_bus->dev, "smbus read\n");
> > > + } else if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) {
> > > + if (msg->len == 1)
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > +
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus) {
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > +
> > > + /* send start */
> > > + dev_dbg(i2c_bus->dev, "[%d] %s %d byte%s %s 0x%02x\n",
> > > + i2c_bus->msgs_index, str_read_write(msg->flags & I2C_M_RD),
> > > + msg->len, str_plural(msg->len),
> > > + msg->flags & I2C_M_RD ? "from" : "to", msg->addr);
> > > +
> > > + i2c_bus->controller_xfer_cnt = 0;
> > > + i2c_bus->buf_index = 0;
> > > +
> > > + if (msg->flags & I2C_M_RD) {
> > > + if (i2c_bus->mode == DMA_MODE)
> > > + return ast2600_i2c_setup_dma_rx(i2c_bus);
> > > + else if (i2c_bus->mode == BUFF_MODE)
> > > + return ast2600_i2c_setup_buff_rx(i2c_bus);
> > > + else
> > > + return ast2600_i2c_setup_byte_rx(i2c_bus);
> > > + } else {
> > > + if (i2c_bus->mode == DMA_MODE)
> > > + return
> > ast2600_i2c_setup_dma_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > > + else if (i2c_bus->mode == BUFF_MODE)
> > > + return ast2600_i2c_setup_buff_tx(AST2600_I2CM_START_CMD,
> > i2c_bus);
> > > + else
> > > + return
> > ast2600_i2c_setup_byte_tx(AST2600_I2CM_START_CMD, i2c_bus);
> > > + }
> > > +}
> > > +
> > > +static int ast2600_i2c_irq_err_to_errno(u32 irq_status) {
> > > + if (irq_status & AST2600_I2CM_ARBIT_LOSS)
> > > + return -EAGAIN;
> > > + if (irq_status & (AST2600_I2CM_SDA_DL_TO |
> > AST2600_I2CM_SCL_LOW_TO))
> > > + return -EBUSY;
> > > + if (irq_status & (AST2600_I2CM_ABNORMAL))
> > > + return -EPROTO;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void ast2600_i2c_controller_package_irq(struct ast2600_i2c_bus
> > > +*i2c_bus, u32 sts) {
> > > + struct i2c_msg *msg = &i2c_bus->msgs[i2c_bus->msgs_index];
> > > + u32 cmd = AST2600_I2CM_PKT_EN;
> > > + int xfer_len;
> > > + int i;
> > > +
> > > + sts &= ~AST2600_I2CM_PKT_DONE;
> > > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> > AST2600_I2CM_ISR);
> > > + switch (sts) {
> > > + case AST2600_I2CM_PKT_ERROR:
> > > + i2c_bus->cmd_err = -EAGAIN;
> > > + complete(&i2c_bus->cmd_complete);
> > > + break;
> > > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for
> > issue */
> > > + fallthrough;
> > > + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK |
> > AST2600_I2CM_NORMAL_STOP:
> > > + i2c_bus->cmd_err = -ENXIO;
> > > + complete(&i2c_bus->cmd_complete);
> > > + break;
> > > + case AST2600_I2CM_NORMAL_STOP:
> > > + /* write 0 byte only have stop isr */
> > > + i2c_bus->msgs_index++;
> > > + if (i2c_bus->msgs_index < i2c_bus->msgs_count) {
> > > + if (ast2600_i2c_do_start(i2c_bus)) {
> > > + i2c_bus->cmd_err = -ENOMEM;
> > > + complete(&i2c_bus->cmd_complete);
> > > + }
> > > + } else {
> > > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > > + complete(&i2c_bus->cmd_complete);
> > > + }
> > > + break;
> > > + case AST2600_I2CM_TX_ACK:
> > > + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP:
> > > + if (i2c_bus->mode == DMA_MODE)
> > > + xfer_len =
> > AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base +
> > > + AST2600_I2CM_DMA_LEN_STS));
> > > + else if (i2c_bus->mode == BUFF_MODE)
> > > + xfer_len =
> > AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base +
> > > + AST2600_I2CC_BUFF_CTRL));
> > > + else
> > > + xfer_len = 1;
> > > +
> > > + i2c_bus->controller_xfer_cnt += xfer_len;
> > > +
> > > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > > + if (i2c_bus->mode == DMA_MODE) {
> > > + dma_unmap_single(i2c_bus->dev,
> > i2c_bus->controller_dma_addr,
> > > + msg->len, DMA_TO_DEVICE);
> > > +
> > i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > > + msg, true);
> > > + i2c_bus->controller_dma_safe_buf = NULL;
> > > + }
> > > + i2c_bus->msgs_index++;
> > > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > > + complete(&i2c_bus->cmd_complete);
> > > + } else {
> > > + if (ast2600_i2c_do_start(i2c_bus)) {
> > > + i2c_bus->cmd_err = -ENOMEM;
> > > + complete(&i2c_bus->cmd_complete);
> > > + }
> > > + }
> > > + } else {
> > > + if (i2c_bus->mode == DMA_MODE)
> > > + ast2600_i2c_setup_dma_tx(0, i2c_bus);
> > > + else if (i2c_bus->mode == BUFF_MODE)
> > > + ast2600_i2c_setup_buff_tx(0, i2c_bus);
> > > + else
> > > + ast2600_i2c_setup_byte_tx(0, i2c_bus);
> > > + }
> > > + break;
> > > + case AST2600_I2CM_RX_DONE:
> > > + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP:
> > > + /* do next rx */
> > > + if (i2c_bus->mode == DMA_MODE) {
> > > + xfer_len =
> > AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base +
> > > + AST2600_I2CM_DMA_LEN_STS));
> > > + } else if (i2c_bus->mode == BUFF_MODE) {
> > > + xfer_len =
> > AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base +
> > > + AST2600_I2CC_BUFF_CTRL));
> > > + for (i = 0; i < xfer_len; i++)
> > > + msg->buf[i2c_bus->controller_xfer_cnt + i] =
> > > + readb(i2c_bus->buf_base + 0x10 + i);
> > > + } else {
> > > + xfer_len = 1;
> > > + msg->buf[i2c_bus->controller_xfer_cnt] =
> > > + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base +
> > > + AST2600_I2CC_STS_AND_BUFF));
> > > + }
> > > +
> > > + if (msg->flags & I2C_M_RECV_LEN) {
> > > + msg->len = min_t(unsigned int, msg->buf[0],
> > I2C_SMBUS_BLOCK_MAX);
> > > + msg->len += ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
> > > + msg->flags &= ~I2C_M_RECV_LEN;
> > > + }
> > > + i2c_bus->controller_xfer_cnt += xfer_len;
> > > +
> > > + if (i2c_bus->controller_xfer_cnt == msg->len) {
> > > + if (i2c_bus->mode == DMA_MODE) {
> > > + dma_unmap_single(i2c_bus->dev,
> > i2c_bus->controller_dma_addr,
> > > + msg->len, DMA_FROM_DEVICE);
> > > +
> > i2c_put_dma_safe_msg_buf(i2c_bus->controller_dma_safe_buf,
> > > + msg, true);
> > > + i2c_bus->controller_dma_safe_buf = NULL;
> > > + }
> > > +
> > > + i2c_bus->msgs_index++;
> > > + if (i2c_bus->msgs_index == i2c_bus->msgs_count) {
> > > + i2c_bus->cmd_err = i2c_bus->msgs_index;
> > > + complete(&i2c_bus->cmd_complete);
> > > + } else {
> > > + if (ast2600_i2c_do_start(i2c_bus)) {
> > > + i2c_bus->cmd_err = -ENOMEM;
> > > + complete(&i2c_bus->cmd_complete);
> > > + }
> > > + }
> > > + } else {
> > > + /* next rx */
> > > + cmd |= AST2600_I2CM_RX_CMD;
> > > + if (i2c_bus->mode == DMA_MODE) {
> > > + cmd |= AST2600_I2CM_RX_DMA_EN;
> > > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > > + if (xfer_len > AST2600_I2C_DMA_SIZE) {
> > > + xfer_len = AST2600_I2C_DMA_SIZE;
> > > + } else {
> > > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1),
> > > + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN);
> > > + writel(i2c_bus->controller_dma_addr +
> > i2c_bus->controller_xfer_cnt,
> > > + i2c_bus->reg_base + AST2600_I2CM_RX_DMA);
> > > + } else if (i2c_bus->mode == BUFF_MODE) {
> > > + cmd |= AST2600_I2CM_RX_BUFF_EN;
> > > + xfer_len = msg->len - i2c_bus->controller_xfer_cnt;
> > > + if (xfer_len > i2c_bus->buf_size) {
> > > + xfer_len = i2c_bus->buf_size;
> > > + } else {
> > > + if (i2c_bus->msgs_index + 1 == i2c_bus->msgs_count)
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len),
> > > + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL);
> > > + } else {
> > > + if ((i2c_bus->msgs_index + 1 == i2c_bus->msgs_count) &&
> > > + ((i2c_bus->controller_xfer_cnt + 1) == msg->len)) {
> > > + cmd |= CONTROLLER_TRIGGER_LAST_STOP;
> > > + }
> > > + }
> > > + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS);
> > > + }
> > > + break;
> > > + default:
> > > + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts);
> > > + break;
> > > + }
> > > +}
> > > +
> > > +static int ast2600_i2c_controller_irq(struct ast2600_i2c_bus
> > > +*i2c_bus) {
> > > + u32 sts = readl(i2c_bus->reg_base + AST2600_I2CM_ISR);
> > > + u32 ctrl;
> > > +
> > > + sts &= ~AST2600_I2CM_SMBUS_ALT;
> > > +
> > > + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) {
> > > + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base +
> > AST2600_I2CM_ISR);
> > > + ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + i2c_bus->cmd_err = -EPROTO;
> > > + complete(&i2c_bus->cmd_complete);
> > > + return 1;
> > > + }
> > > +
> > > + if (AST2600_I2CM_BUS_RECOVER & sts) {
> > > + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base +
> > AST2600_I2CM_ISR);
> > > + i2c_bus->cmd_err = 0;
> > > + complete(&i2c_bus->cmd_complete);
> > > + return 1;
> > > + }
> > > +
> > > + i2c_bus->cmd_err = ast2600_i2c_irq_err_to_errno(sts);
> > > + if (i2c_bus->cmd_err) {
> > > + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base +
> > AST2600_I2CM_ISR);
> > > + complete(&i2c_bus->cmd_complete);
> > > + return 1;
> > > + }
> > > +
> > > + if (AST2600_I2CM_PKT_DONE & sts) {
> > > + ast2600_i2c_controller_package_irq(i2c_bus, sts);
> > > + return 1;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id) {
> > > + struct ast2600_i2c_bus *i2c_bus = dev_id;
> > > +
> > > + return IRQ_RETVAL(ast2600_i2c_controller_irq(i2c_bus));
> > > +}
> > > +
> > > +static int ast2600_i2c_controller_xfer(struct i2c_adapter *adap,
> > > +struct i2c_msg *msgs, int num) {
> > > + struct ast2600_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
> > > + unsigned long timeout;
> > > + int ret;
> > > +
> > > + if (!i2c_bus->multi_master &&
> > > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> > AST2600_I2CC_BUS_BUSY_STS)) {
> > > + ret = ast2600_i2c_recover_bus(i2c_bus);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > + i2c_bus->cmd_err = 0;
> > > + i2c_bus->msgs = msgs;
> > > + i2c_bus->msgs_index = 0;
> > > + i2c_bus->msgs_count = num;
> > > + reinit_completion(&i2c_bus->cmd_complete);
> > > + ret = ast2600_i2c_do_start(i2c_bus);
> > > + if (ret)
> > > + goto controller_out;
> > > + timeout = wait_for_completion_timeout(&i2c_bus->cmd_complete,
> > i2c_bus->adap.timeout);
> > > + if (timeout == 0) {
> > > + u32 ctrl = readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n",
> > > + readl(i2c_bus->reg_base + AST2600_I2CM_ISR),
> > > + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF));
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + if (i2c_bus->multi_master &&
> > > + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) &
> > > + AST2600_I2CC_BUS_BUSY_STS))
> > > + ast2600_i2c_recover_bus(i2c_bus);
> > > +
> > > + ret = -ETIMEDOUT;
> > > + } else {
> > > + ret = i2c_bus->cmd_err;
> > > + }
> > > +
> > > + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr,
> > > +i2c_bus->cmd_err);
> > > +
> > > +controller_out:
> > > + if (i2c_bus->mode == DMA_MODE) {
> > > + kfree(i2c_bus->controller_dma_safe_buf);
> > > + i2c_bus->controller_dma_safe_buf = NULL;
> > > + }
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus) {
> > > + struct platform_device *pdev = to_platform_device(i2c_bus->dev);
> > > + u32 fun_ctrl = AST2600_I2CC_BUS_AUTO_RELEASE |
> > > +AST2600_I2CC_MASTER_EN;
> > > +
> > > + /* I2C Reset */
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > +
> > > + i2c_bus->multi_master = device_property_read_bool(&pdev->dev,
> > "multi-master");
> > > + if (!i2c_bus->multi_master)
> > > + fun_ctrl |= AST2600_I2CC_MULTI_MASTER_DIS;
> > > +
> > > + /* Enable Controller Mode */
> > > + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + /* disable target address */
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL);
> > > +
> > > + /* Set AC Timing */
> > > + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base +
> > > +AST2600_I2CC_AC_TIMING);
> > > +
> > > + /* Clear Interrupt */
> > > + writel(GENMASK(27, 0), i2c_bus->reg_base + AST2600_I2CM_ISR); }
> > > +
> > > +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap) {
> > > + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
> > > +I2C_FUNC_SMBUS_BLOCK_DATA; }
> > > +
> > > +static const struct i2c_algorithm i2c_ast2600_algorithm = {
> > > + .xfer = ast2600_i2c_controller_xfer,
> > > + .functionality = ast2600_i2c_functionality, };
> > > +
> > > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> > > + struct device *dev = &pdev->dev;
> > > + struct ast2600_i2c_bus *i2c_bus;
> > > + struct resource *res;
> > > + u32 global_ctrl;
> > > + int ret;
> > > +
> > > + i2c_bus = devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL);
> > > + if (!i2c_bus)
> > > + return -ENOMEM;
> > > +
> > > + i2c_bus->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > > + if (IS_ERR(i2c_bus->reg_base))
> > > + return PTR_ERR(i2c_bus->reg_base);
> > > +
> > > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > > + if (IS_ERR(i2c_bus->rst))
> > > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset
> > > +ctrl\n");
> > > +
> > > + reset_control_deassert(i2c_bus->rst);
> > > +
> > > + i2c_bus->global_regs =
> > > + syscon_regmap_lookup_by_phandle(dev_of_node(dev),
> > "aspeed,global-regs");
> > > + if (IS_ERR(i2c_bus->global_regs))
> > > + return PTR_ERR(i2c_bus->global_regs);
> > > +
> > > + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl);
> > > + if ((global_ctrl & AST2600_GLOBAL_INIT) != AST2600_GLOBAL_INIT) {
> > > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL,
> > AST2600_GLOBAL_INIT);
> > > + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL,
> > I2CCG_DIV_CTRL);
> > > + }
> > > +
> > > + i2c_bus->dev = dev;
> > > + i2c_bus->mode = BUFF_MODE;
> > > +
> > > + if (device_property_read_bool(dev, "aspeed,enable-dma"))
> > > + i2c_bus->mode = DMA_MODE;
> > > +
> > > + if (i2c_bus->mode == BUFF_MODE) {
> > > + i2c_bus->buf_base =
> > devm_platform_get_and_ioremap_resource(pdev, 1, &res);
> > > + if (IS_ERR(i2c_bus->buf_base))
> > > + i2c_bus->mode = BYTE_MODE;
> > > + else
> > > + i2c_bus->buf_size = resource_size(res) / 2;
> > > + }
> > > +
> > > + /*
> > > + * i2c timeout counter: use base clk4 1Mhz,
> > > + * per unit: 1/(1000/4096) = 4096us
> > > + */
> > > + ret = device_property_read_u32(dev, "i2c-scl-clk-low-timeout-us",
> > &i2c_bus->timeout);
> > > + if (!ret)
> > > + i2c_bus->timeout /= 4096;
> > > +
> > > + init_completion(&i2c_bus->cmd_complete);
> > > +
> > > + i2c_bus->irq = platform_get_irq(pdev, 0);
> > > + if (i2c_bus->irq < 0)
> > > + return i2c_bus->irq;
> > > +
> > > + platform_set_drvdata(pdev, i2c_bus);
> > > +
> > > + i2c_bus->clk = devm_clk_get(i2c_bus->dev, NULL);
> > > + if (IS_ERR(i2c_bus->clk))
> > > + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't
> > > +get clock\n");
> > > +
> > > + i2c_bus->apb_clk = clk_get_rate(i2c_bus->clk);
> > > +
> > > + i2c_parse_fw_timings(i2c_bus->dev, &i2c_bus->timing_info, true);
> > > +
> > > + /* Initialize the I2C adapter */
> > > + i2c_bus->adap.owner = THIS_MODULE;
> > > + i2c_bus->adap.algo = &i2c_ast2600_algorithm;
> > > + i2c_bus->adap.retries = 0;
> > > + i2c_bus->adap.dev.parent = i2c_bus->dev;
> > > + device_set_node(&i2c_bus->adap.dev, dev_fwnode(dev));
> > > + i2c_bus->adap.algo_data = i2c_bus;
> > > + strscpy(i2c_bus->adap.name, pdev->name);
> > > + i2c_set_adapdata(&i2c_bus->adap, i2c_bus);
> > > +
> > > + ast2600_i2c_init(i2c_bus);
> > > +
> > > + ret = devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0,
> > > + dev_name(dev), i2c_bus);
> > > + if (ret < 0)
> > > + return dev_err_probe(dev, ret, "Unable to request irq %d\n",
> > > +i2c_bus->irq);
> > > +
> > > + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER,
> > > + i2c_bus->reg_base + AST2600_I2CM_IER);
> > > +
> > > + ret = devm_i2c_add_adapter(dev, &i2c_bus->adap);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void ast2600_i2c_remove(struct platform_device *pdev) {
> > > + struct ast2600_i2c_bus *i2c_bus = platform_get_drvdata(pdev);
> > > +
> > > + /* Disable everything. */
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL);
> > > + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER); }
> > > +
> > > +static const struct of_device_id ast2600_i2c_bus_of_table[] = {
> > > + {
> > > + .compatible = "aspeed,ast2600-i2cv2",
> > > + },
> > > + {}
> > > +};
> > > +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table);
> > > +
> > > +static struct platform_driver ast2600_i2c_bus_driver = {
> > > + .probe = ast2600_i2c_probe,
> > > + .remove = ast2600_i2c_remove,
> > > + .driver = {
> > > + .name = KBUILD_MODNAME,
> > > + .of_match_table = ast2600_i2c_bus_of_table,
> > > + },
> > > +};
> > > +
> > > +module_platform_driver(ast2600_i2c_bus_driver);
> > > +
> > > +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> > > +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver");
> > > +MODULE_LICENSE("GPL");
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
2024-11-11 11:00 ` Naresh Solanki
2024-11-12 4:54 ` Yikai Tsai
@ 2024-11-12 10:22 ` Philipp Zabel
2024-11-13 7:43 ` Ryan Chen
2 siblings, 1 reply; 15+ messages in thread
From: Philipp Zabel @ 2024-11-12 10:22 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins, benh, joel, andi.shyti, robh, krzk+dt,
conor+dt, andrew, andriy.shevchenko, linux-i2c, openbmc,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Mo, 2024-10-07 at 11:52 +0800, Ryan Chen wrote:
> Add i2c new register mode driver to support AST2600 i2c
> new register mode. AST2600 i2c controller have legacy and
> new register mode. The new register mode have global register
> support 4 base clock for scl clock selection, and new clock
> divider mode. The new register mode have separate register
> set to control i2c controller and target. This patch is for i2c
> controller mode driver.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
> drivers/i2c/busses/Kconfig | 11 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-ast2600.c | 1032 ++++++++++++++++++++++++++++++
> 3 files changed, 1044 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-ast2600.c
>
[...]
> diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2600.c
> new file mode 100644
> index 000000000000..17ba0ee77c27
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-ast2600.c
> @@ -0,0 +1,1032 @@
[...]
> +static int ast2600_i2c_probe(struct platform_device *pdev)
> +{
[...]
> + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> + if (IS_ERR(i2c_bus->rst))
> + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset ctrl\n");
> +
> + reset_control_deassert(i2c_bus->rst);
The shared reset should be asserted again in ast2600_i2c_remove().
regards
Philipp
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-12 10:22 ` Philipp Zabel
@ 2024-11-13 7:43 ` Ryan Chen
2024-11-13 10:03 ` Philipp Zabel
0 siblings, 1 reply; 15+ messages in thread
From: Ryan Chen @ 2024-11-13 7:43 UTC (permalink / raw)
To: Philipp Zabel, brendan.higgins@linux.dev,
benh@kernel.crashing.org, joel@jms.id.au, andi.shyti@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, andriy.shevchenko@linux.intel.com,
linux-i2c@vger.kernel.org, openbmc@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register
> mode driver
>
> On Mo, 2024-10-07 at 11:52 +0800, Ryan Chen wrote:
> > Add i2c new register mode driver to support AST2600 i2c new register
> > mode. AST2600 i2c controller have legacy and new register mode. The
> > new register mode have global register support 4 base clock for scl
> > clock selection, and new clock divider mode. The new register mode
> > have separate register set to control i2c controller and target. This
> > patch is for i2c controller mode driver.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> > drivers/i2c/busses/Kconfig | 11 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-ast2600.c | 1032
> > ++++++++++++++++++++++++++++++
> > 3 files changed, 1044 insertions(+)
> > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> >
> [...]
> > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > b/drivers/i2c/busses/i2c-ast2600.c
> > new file mode 100644
> > index 000000000000..17ba0ee77c27
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > @@ -0,0 +1,1032 @@
> [...]
> > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> [...]
> > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > + if (IS_ERR(i2c_bus->rst))
> > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset
> > +ctrl\n");
> > +
> > + reset_control_deassert(i2c_bus->rst);
>
> The shared reset should be asserted again in ast2600_i2c_remove().
>
Hello,
It is share reset, if unbond driver and asserted the reset, it will affect others driver running (which is share with the same reset.)
> regards
> Philipp
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-13 7:43 ` Ryan Chen
@ 2024-11-13 10:03 ` Philipp Zabel
2024-11-15 0:18 ` Ryan Chen
0 siblings, 1 reply; 15+ messages in thread
From: Philipp Zabel @ 2024-11-13 10:03 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins@linux.dev, benh@kernel.crashing.org,
joel@jms.id.au, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, andriy.shevchenko@linux.intel.com,
linux-i2c@vger.kernel.org, openbmc@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
On Mi, 2024-11-13 at 07:43 +0000, Ryan Chen wrote:
> > Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new
> > register
> > mode driver
> >
> > On Mo, 2024-10-07 at 11:52 +0800, Ryan Chen wrote:
> > > Add i2c new register mode driver to support AST2600 i2c new
> > > register
> > > mode. AST2600 i2c controller have legacy and new register mode.
> > > The
> > > new register mode have global register support 4 base clock for
> > > scl
> > > clock selection, and new clock divider mode. The new register
> > > mode
> > > have separate register set to control i2c controller and target.
> > > This
> > > patch is for i2c controller mode driver.
> > >
> > > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > > ---
> > > drivers/i2c/busses/Kconfig | 11 +
> > > drivers/i2c/busses/Makefile | 1 +
> > > drivers/i2c/busses/i2c-ast2600.c | 1032
> > > ++++++++++++++++++++++++++++++
> > > 3 files changed, 1044 insertions(+)
> > > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> > >
> > [...]
> > > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > > b/drivers/i2c/busses/i2c-ast2600.c
> > > new file mode 100644
> > > index 000000000000..17ba0ee77c27
> > > --- /dev/null
> > > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > > @@ -0,0 +1,1032 @@
> > [...]
> > > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> > [...]
> > > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > > + if (IS_ERR(i2c_bus->rst))
> > > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst),
> > > "Missing reset
> > > +ctrl\n");
> > > +
> > > + reset_control_deassert(i2c_bus->rst);
> >
> > The shared reset should be asserted again in ast2600_i2c_remove().
> >
> Hello,
> It is share reset, if unbond driver and asserted the reset, it will
> affect others driver running (which is share with the same reset.)
Shared reset_control_deassert/assert are refcounted, like
clk_enable/disable, see [1]. The reset line will only be asserted when
the last driver calls reset_control_assert.
[1] https://docs.kernel.org/driver-api/reset.html#shared-and-exclusive-resets
regards
Philipp
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver
2024-11-13 10:03 ` Philipp Zabel
@ 2024-11-15 0:18 ` Ryan Chen
0 siblings, 0 replies; 15+ messages in thread
From: Ryan Chen @ 2024-11-15 0:18 UTC (permalink / raw)
To: Philipp Zabel, brendan.higgins@linux.dev,
benh@kernel.crashing.org, joel@jms.id.au, andi.shyti@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, andriy.shevchenko@linux.intel.com,
linux-i2c@vger.kernel.org, openbmc@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register
> mode driver
>
> On Mi, 2024-11-13 at 07:43 +0000, Ryan Chen wrote:
> > > Subject: Re: [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new
> > > register mode driver
> > >
> > > On Mo, 2024-10-07 at 11:52 +0800, Ryan Chen wrote:
> > > > Add i2c new register mode driver to support AST2600 i2c new
> > > > register mode. AST2600 i2c controller have legacy and new register
> > > > mode.
> > > > The
> > > > new register mode have global register support 4 base clock for
> > > > scl clock selection, and new clock divider mode. The new register
> > > > mode have separate register set to control i2c controller and
> > > > target.
> > > > This
> > > > patch is for i2c controller mode driver.
> > > >
> > > > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > > > ---
> > > > drivers/i2c/busses/Kconfig | 11 +
> > > > drivers/i2c/busses/Makefile | 1 +
> > > > drivers/i2c/busses/i2c-ast2600.c | 1032
> > > > ++++++++++++++++++++++++++++++
> > > > 3 files changed, 1044 insertions(+)
> > > > create mode 100644 drivers/i2c/busses/i2c-ast2600.c
> > > >
> > > [...]
> > > > diff --git a/drivers/i2c/busses/i2c-ast2600.c
> > > > b/drivers/i2c/busses/i2c-ast2600.c
> > > > new file mode 100644
> > > > index 000000000000..17ba0ee77c27
> > > > --- /dev/null
> > > > +++ b/drivers/i2c/busses/i2c-ast2600.c
> > > > @@ -0,0 +1,1032 @@
> > > [...]
> > > > +static int ast2600_i2c_probe(struct platform_device *pdev) {
> > > [...]
> > > > + i2c_bus->rst = devm_reset_control_get_shared(dev, NULL);
> > > > + if (IS_ERR(i2c_bus->rst))
> > > > + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst),
> > > > "Missing reset
> > > > +ctrl\n");
> > > > +
> > > > + reset_control_deassert(i2c_bus->rst);
> > >
> > > The shared reset should be asserted again in ast2600_i2c_remove().
> > >
> > Hello,
> > It is share reset, if unbond driver and asserted the reset, it will
> > affect others driver running (which is share with the same reset.)
>
> Shared reset_control_deassert/assert are refcounted, like clk_enable/disable,
> see [1]. The reset line will only be asserted when the last driver calls
> reset_control_assert.
>
> [1] https://docs.kernel.org/driver-api/reset.html#shared-and-exclusive-resets
>
Thanks a lot, I will add in next version submit.
> regards
> Philipp
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2
2024-10-07 3:52 ` [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Ryan Chen
@ 2025-02-21 8:25 ` Ryan Chen
2025-02-21 8:36 ` Krzysztof Kozlowski
0 siblings, 1 reply; 15+ messages in thread
From: Ryan Chen @ 2025-02-21 8:25 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins@linux.dev, benh@kernel.crashing.org,
joel@jms.id.au, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, p.zabel@pengutronix.de,
andriy.shevchenko@linux.intel.com, linux-i2c@vger.kernel.org,
openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski
Hello Krzysztof,
I am going to submit v16, and will update the yaml file, in my this version will add aspeed,enable-byte.
So, we should I do about this patch about " Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"
Should I remove it ? or I should keep this Reviewed-by?
> -----Original Message-----
> From: Ryan Chen <ryan_chen@aspeedtech.com>
> Sent: Monday, October 7, 2024 11:53 AM
> To: brendan.higgins@linux.dev; benh@kernel.crashing.org; joel@jms.id.au;
> andi.shyti@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; andrew@codeconstruct.com.au;
> p.zabel@pengutronix.de; andriy.shevchenko@linux.intel.com;
> linux-i2c@vger.kernel.org; openbmc@lists.ozlabs.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org; Ryan Chen
> <ryan_chen@aspeedtech.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Subject: [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2
>
> Add ast2600-i2cv2 compatible and aspeed,global-regs, aspeed,enable-dma
> and description for ast2600-i2cv2.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../devicetree/bindings/i2c/aspeed,i2c.yaml | 51 +++++++++++++++++--
> 1 file changed, 48 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> index 6df27b47b922..6c16fc76c978 100644
> --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> @@ -9,9 +9,6 @@ title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX
> SoCs
> maintainers:
> - Rayn Chen <rayn_chen@aspeedtech.com>
>
> -allOf:
> - - $ref: /schemas/i2c/i2c-controller.yaml#
> -
> properties:
> compatible:
> enum:
> @@ -49,12 +46,50 @@ properties:
> description:
> states that there is another master active on this bus
>
> + aspeed,enable-dma:
> + type: boolean
> + description: |
> + I2C bus enable dma mode transfer.
> +
> + ASPEED ast2600 platform equipped with 16 I2C controllers that share
> a
> + single DMA engine. DTS files can specify the data transfer mode
> to/from
> + the device, either DMA or programmed I/O. However, hardware
> limitations
> + may require a DTS to manually allocate which controller can use DMA
> mode.
> + The "aspeed,enable-dma" property allows control of this.
> +
> + In cases where one the hardware design results in a specific
> + controller handling a larger amount of data, a DTS would likely
> + enable DMA mode for that one controller.
> +
> + aspeed,global-regs:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle of i2c global register node.
> +
> required:
> - reg
> - compatible
> - clocks
> - resets
>
> +allOf:
> + - $ref: /schemas/i2c/i2c-controller.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: aspeed,ast2600-i2cv2
> +
> + then:
> + properties:
> + reg:
> + minItems: 2
> + required:
> + - aspeed,global-regs
> + else:
> + properties:
> + aspeed,global-regs: false
> + aspeed,enable-dma: false
> +
> unevaluatedProperties: false
>
> examples:
> @@ -71,3 +106,13 @@ examples:
> interrupts = <0>;
> interrupt-parent = <&i2c_ic>;
> };
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + i2c1: i2c@80 {
> + compatible = "aspeed,ast2600-i2cv2";
> + reg = <0x80 0x80>, <0xc00 0x20>;
> + aspeed,global-regs = <&i2c_global>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + };
> --
> 2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2
2025-02-21 8:25 ` Ryan Chen
@ 2025-02-21 8:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-21 8:36 UTC (permalink / raw)
To: Ryan Chen, brendan.higgins@linux.dev, benh@kernel.crashing.org,
joel@jms.id.au, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@codeconstruct.com.au, p.zabel@pengutronix.de,
andriy.shevchenko@linux.intel.com, linux-i2c@vger.kernel.org,
openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
On 21/02/2025 09:25, Ryan Chen wrote:
> Hello Krzysztof,
> I am going to submit v16, and will update the yaml file, in my this version will add aspeed,enable-byte.
> So, we should I do about this patch about " Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"
> Should I remove it ? or I should keep this Reviewed-by?
If you add a new property, then please drop the review tag.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2025-02-21 8:37 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-07 3:52 [PATCH v15 0/3] Add ASPEED AST2600 I2Cv2 controller driver Ryan Chen
2024-10-07 3:52 ` [PATCH v15 1/3] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Ryan Chen
2025-02-21 8:25 ` Ryan Chen
2025-02-21 8:36 ` Krzysztof Kozlowski
2024-10-07 3:52 ` [PATCH v15 2/3] i2c: aspeed: support AST2600 i2c new register mode driver Ryan Chen
2024-11-11 11:00 ` Naresh Solanki
2024-11-12 7:00 ` Ryan Chen
2024-11-12 9:22 ` Naresh Solanki
2024-11-12 4:54 ` Yikai Tsai
2024-11-12 6:55 ` Ryan Chen
2024-11-12 10:22 ` Philipp Zabel
2024-11-13 7:43 ` Ryan Chen
2024-11-13 10:03 ` Philipp Zabel
2024-11-15 0:18 ` Ryan Chen
2024-10-07 3:52 ` [PATCH v15 3/3] i2c: aspeed: support AST2600 i2c new register target " Ryan Chen
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