* [PATCH v1 00/10] Add MediaTek ISP7 camera system driver
@ 2024-10-09 11:15 Shu-hsiang Yang
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
` (11 more replies)
0 siblings, 12 replies; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
Based on linux-next/master, tag: next-20241008
The patch set adds the MediaTek ISP7.x camera system hardware driver.
This driver sets up ISP hardware, handles interrupts, and initializes
V4L2 device nodes and functions. Moreover, implement V4L2 standard
video driver that utilizes media framework APIs. It also connects
the sensors and ISP, bridging with the seninf interface. Communicate
with SCP co-processor to compose ISP registers in the firmware.
These patches include CSI received data from sensors, sensor interface
bridge, raw/YUV image pre-processing, ISP utility and ISP control parts.
Thank you for reviewing these patches.
Shu-hsiang Yang (10):
dt-bindings: media: mediatek: add camsys device
media: platform: mediatek: add seninf controller
media: platform: mediatek: add isp_7x seninf unit
media: platform: mediatek: add isp_7x cam-raw unit
media: platform: mediatek: add isp_7x camsys unit
media: platform: mediatek: add isp_7x utility
media: platform: mediatek: add isp_7x video ops
media: platform: mediatek: add isp_7x state ctrl
media: platform: mediatek: add isp_7x build config
uapi: linux: add mediatek isp_7x camsys user api
.../media/mediatek/mediatek,cam-raw.yaml | 169 +
.../media/mediatek/mediatek,cam-yuv.yaml | 148 +
.../media/mediatek/mediatek,camisp.yaml | 71 +
.../media/mediatek/mediatek,seninf-core.yaml | 106 +
.../media/mediatek/mediatek,seninf.yaml | 88 +
drivers/media/platform/mediatek/Kconfig | 1 +
drivers/media/platform/mediatek/Makefile | 2 +
drivers/media/platform/mediatek/isp/Kconfig | 21 +
.../platform/mediatek/isp/isp_7x/Makefile | 7 +
.../mediatek/isp/isp_7x/camsys/Makefile | 16 +
.../isp_7x/camsys/kd_imgsensor_define_v4l2.h | 87 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c | 1797 ++++++
.../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h | 140 +
.../isp/isp_7x/camsys/mtk_cam-debug.c | 1271 ++++
.../isp/isp_7x/camsys/mtk_cam-debug.h | 273 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-defs.h | 168 +
.../isp/isp_7x/camsys/mtk_cam-dmadbg.h | 721 +++
.../isp/isp_7x/camsys/mtk_cam-feature.c | 40 +
.../isp/isp_7x/camsys/mtk_cam-feature.h | 26 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h | 87 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h | 233 +
.../isp/isp_7x/camsys/mtk_cam-meta-mt8188.h | 2436 ++++++++
.../isp/isp_7x/camsys/mtk_cam-plat-util.c | 207 +
.../isp/isp_7x/camsys/mtk_cam-plat-util.h | 16 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-pool.c | 393 ++
.../mediatek/isp/isp_7x/camsys/mtk_cam-pool.h | 28 +
.../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++
.../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 +
.../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++
.../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 +
.../isp/isp_7x/camsys/mtk_cam-regs-mt8188.h | 382 ++
.../isp/isp_7x/camsys/mtk_cam-seninf-def.h | 193 +
.../isp/isp_7x/camsys/mtk_cam-seninf-drv.c | 1741 ++++++
.../isp/isp_7x/camsys/mtk_cam-seninf-drv.h | 16 +
.../isp/isp_7x/camsys/mtk_cam-seninf-hw.h | 120 +
.../isp/isp_7x/camsys/mtk_cam-seninf-if.h | 28 +
.../isp/isp_7x/camsys/mtk_cam-seninf-regs.h | 40 +
.../isp/isp_7x/camsys/mtk_cam-seninf-route.c | 356 ++
.../isp/isp_7x/camsys/mtk_cam-seninf-route.h | 23 +
.../isp/isp_7x/camsys/mtk_cam-seninf.h | 170 +
.../isp/isp_7x/camsys/mtk_cam-timesync.c | 125 +
.../isp/isp_7x/camsys/mtk_cam-timesync.h | 12 +
.../isp/isp_7x/camsys/mtk_cam-ufbc-def.h | 59 +
.../isp/isp_7x/camsys/mtk_cam-video.c | 1817 ++++++
.../isp/isp_7x/camsys/mtk_cam-video.h | 224 +
.../mediatek/isp/isp_7x/camsys/mtk_cam.c | 4168 +++++++++++++
.../mediatek/isp/isp_7x/camsys/mtk_cam.h | 733 +++
.../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 +
.../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 +
.../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 +++
.../mtk_cam-seninf-csi0-cphy.h | 69 +
.../mtk_cam-seninf-csi0-dphy.h | 139 +
.../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++
.../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 +
.../mtk_cam-seninf-seninf1-csi2.h | 415 ++
.../mtk_cam-seninf-seninf1-mux.h | 147 +
.../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 +
.../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 +
.../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 +
include/uapi/linux/mtkisp_camsys.h | 227 +
60 files changed, 30194 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-defs.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-dmadbg.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-meta-mt8188.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-regs-mt8188.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ufbc-def.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h
create mode 100644 include/uapi/linux/mtkisp_camsys.h
--
2.18.0
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
@ 2024-10-09 11:15 ` Shu-hsiang Yang
2024-10-09 21:00 ` Rob Herring
` (5 more replies)
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (10 subsequent siblings)
11 siblings, 6 replies; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
1. Add camera isp7x module device document
2. Add camera interface device document
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
.../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
.../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
.../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
.../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
.../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
5 files changed, 582 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
new file mode 100644
index 000000000000..c709e4bf0a18
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The cam-raw unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,cam-raw
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,cam-id:
+ description:
+ Describes the index of MediaTek cam-raw unit for ISP
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ mediatek,larbs:
+ description:
+ Describes MediaTek bus infrastructure unit for ISP system.
+ List of phandle to the local arbiters in the current SoCs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ interrupts:
+ minItems: 1
+
+ dma-ranges:
+ description:
+ Describes the address information of IOMMU mapping to memory.
+ Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
+ minItems: 1
+
+ power-domains:
+ minItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 16
+
+ clock-names:
+ minItems: 4
+ maxItems: 16
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ iommus:
+ description:
+ Points to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ Ports are according to the HW.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cam_raw_a@16030000 {
+ compatible = "mediatek,cam-raw";
+ reg = <0 0x16030000 0 0x8000>,
+ <0 0x16038000 0 0x8000>;
+ reg-names = "base", "inner_base";
+ mediatek,cam-id = <0>;
+ mediatek,larbs = <&larb16a>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM>,
+ <&camsys CLK_CAM_MAIN_CAMTG>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CAMTG>,
+ <&topckgen CLK_TOP_CAMTM>;
+ clock-names = "camsys_cam2mm0_cgpdn",
+ "camsys_cam2mm1_cgpdn",
+ "camsys_cam2sys_cgpdn",
+ "camsys_cam_cgpdn",
+ "camsys_camtg_cgpdn",
+ "camsys_rawa_larbx_cgpdn",
+ "camsys_rawa_cam_cgpdn",
+ "camsys_rawa_camtg_cgpdn",
+ "topckgen_top_cam",
+ "topckgen_top_camtg",
+ "topckgen_top_camtm";
+ assigned-clocks = <&topckgen CLK_TOP_CAM>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
+ iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
+ <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
+ <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
new file mode 100644
index 000000000000..30dfd5e5ecb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-yuv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The cam-yuv unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek cam-yuv is the camera YUV processing unit in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,cam-yuv
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,cam-id:
+ description:
+ Describes the index of MediaTek cam-yuv unit for ISP
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ mediatek,larbs:
+ description:
+ Describes MediaTek bus infrastructure unit for ISP system.
+ List of phandle to the local arbiters in the current SoCs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ interrupts:
+ minItems: 1
+
+ dma-ranges:
+ description:
+ Describes the address information of IOMMU mapping to memory.
+ Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
+ minItems: 1
+
+ power-domains:
+ minItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 16
+
+ clock-names:
+ minItems: 4
+ maxItems: 16
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ iommus:
+ description:
+ Points to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ Ports are according to the HW.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cam_yuv_b@16090000 {
+ compatible = "mediatek,cam-yuv";
+ reg = <0 0x16090000 0 0x8000>;
+ reg-names = "base";
+ mediatek,cam-id = <1>;
+ mediatek,larbs = <&larb17b>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBB>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_CAM>,
+ <&camsys_yuvb CLK_CAM_YUVB_CAMTG>;
+ clock-names = "camsys_cam2mm0_cgpdn",
+ "camsys_cam2mm1_cgpdn",
+ "camsys_cam2sys_cgpdn",
+ "camsys_yuvb_larbx_cgpdn",
+ "camsys_yuvb_cam_cgpdn",
+ "camsys_yuvb_camtg_cgpdn";
+ assigned-clocks = <&topckgen CLK_TOP_CAM>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
+ iommus = <&vdo_iommu M4U_PORT_L17B_YUVO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_YUVO_R3>,
+ <&vdo_iommu M4U_PORT_L17B_YUVCO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_YUVO_R2>,
+ <&vdo_iommu M4U_PORT_L17B_RZH1N2TO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_DRZS4NO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_TNCSO_R1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
new file mode 100644
index 000000000000..ce378ddbd5bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The camisp unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,camisp
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ mediatek,scp:
+ description: MediaTek co-process unit for ISP system
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camisp: camisp@16000000 {
+ compatible = "mediatek,camisp";
+ reg = <0 0x16000000 0 0x1000>;
+ reg-names = "base";
+ mediatek,scp = <&scp_dual>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
new file mode 100644
index 000000000000..bc509976a79e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,seninf-core.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The seninf-core top unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek seninf-core is the ISP sensor interface unit in MediaTek SoC.
+ The sensor interface serves as the MIPI-CSI2 top RX controller.
+
+properties:
+ compatible:
+ const: mediatek,seninf-core
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+
+ mtk_csi_phy_ver:
+ description:
+ Describes MediaTek camera Rx controller version
+ $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ power-domains:
+ minItems: 1
+ maxItems: 4
+
+ clocks:
+ minItems: 3
+ maxItems: 8
+
+ clock-names:
+ minItems: 3
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ seninf_top: seninf_top@16010000 {
+ compatible = "mediatek,seninf-core";
+ reg = <0 0x16010000 0 0x8000>,
+ <0 0x11ed0000 0 0xc000>;
+ reg-names = "base", "ana-rx";
+ mtk_csi_phy_ver = "mtk_csi_phy_2_0";
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CSIRX_TOP>,
+ <&spm MT8188_POWER_DOMAIN_CAM_VCORE>,
+ <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
+ clocks = <&camsys CLK_CAM_MAIN_SENINF>,
+ <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>,
+ <&topckgen CLK_TOP_CAMTM>;
+ clock-names = "clk_cam_seninf",
+ "clk_top_seninf",
+ "clk_top_seninf1",
+ "clk_top_camtm";
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
new file mode 100644
index 000000000000..37d94138c558
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The seninf unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC.
+ These ports provide the optional capability to define endpoints and set RX
+ controller for camera sensors.
+
+properties:
+ compatible:
+ const: mediatek,seninf
+
+ csi-port:
+ description: MediaTek CSI Rx port name
+ $ref: /schemas/types.yaml#/definitions/string
+
+ port:
+ description:
+ MediaTek sensor interface endpoints for one sensor bus.
+ $ref: /schemas/graph.yaml#/$defs/port-base
+
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^endpoint(@[0-9]+)?$":
+ description:
+ CSI port for one sensor endpoint configuration.
+ Consider one sensor bus can support differet links for MIPI PHY.
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ properties:
+ data-lanes:
+ items:
+ enum: [1, 2, 3, 4]
+ maxItems: 4
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - csi-port
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ seninf_top {
+ seninf_csi_port_0: seninf_csi_port_0 {
+ compatible = "mediatek,seninf";
+ csi-port = "0A";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ seninf_csi_port_0_in_1: endpoint {
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <1440000000 624000000>;
+ remote-endpoint = <&sensor0_out_1>;
+ };
+
+ seninf_csi_port_0_in_2: endpoint@2 {
+ reg = <2>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <336000000 207000000>;
+ remote-endpoint = <&sensor0_out_2>;
+ };
+ };
+ };
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
@ 2024-10-09 11:15 ` Shu-hsiang Yang
2024-10-14 9:25 ` CK Hu (胡俊光)
` (9 more replies)
2024-10-09 11:15 ` [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops Shu-hsiang Yang
` (9 subsequent siblings)
11 siblings, 10 replies; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
Introduces the driver of the MediaTek Sensor Interface,
focusing on integration with the MediaTek ISP CAMSYS. The
seninf device bridges camera sensors and the ISP system,
providing management for sensor data routing and processing.
Key features include V4L2 framework control, and dynamic
handling of stream configurations and virtual channels.
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
.../isp_7x/camsys/kd_imgsensor_define_v4l2.h | 87 +
.../isp/isp_7x/camsys/mtk_cam-seninf-def.h | 193 ++
.../isp/isp_7x/camsys/mtk_cam-seninf-drv.c | 1741 +++++++++++++++++
.../isp/isp_7x/camsys/mtk_cam-seninf-drv.h | 16 +
.../isp/isp_7x/camsys/mtk_cam-seninf-hw.h | 120 ++
.../isp/isp_7x/camsys/mtk_cam-seninf-if.h | 28 +
.../isp/isp_7x/camsys/mtk_cam-seninf-regs.h | 40 +
.../isp/isp_7x/camsys/mtk_cam-seninf-route.c | 356 ++++
.../isp/isp_7x/camsys/mtk_cam-seninf-route.h | 23 +
.../isp/isp_7x/camsys/mtk_cam-seninf.h | 170 ++
10 files changed, 2774 insertions(+)
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
new file mode 100644
index 000000000000..1684a79bbb84
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _KD_IMGSENSOR_DATA_V4L2_H
+#define _KD_IMGSENSOR_DATA_V4L2_H
+
+enum VC_FEATURE {
+ VC_NONE = 0,
+ VC_MIN_NUM,
+ VC_RAW_DATA = VC_MIN_NUM,
+ VC_RAW_DATA_MAX,
+
+ VC_PDAF_MIN_NUM = VC_RAW_DATA_MAX,
+ VC_PDAF_STATS = VC_PDAF_MIN_NUM,
+ VC_PDAF_STATS_NE,
+ VC_PDAF_STATS_ME,
+ VC_PDAF_STATS_SE,
+ VC_PDAF_STATS_PIX_1,
+ VC_PDAF_STATS_PIX_2,
+ VC_PDAF_STATS_NE_PIX_1 = VC_PDAF_STATS_PIX_1,
+ VC_PDAF_STATS_NE_PIX_2 = VC_PDAF_STATS_PIX_2,
+ VC_PDAF_STATS_ME_PIX_1,
+ VC_PDAF_STATS_ME_PIX_2,
+ VC_PDAF_STATS_SE_PIX_1,
+ VC_PDAF_STATS_SE_PIX_2,
+ VC_PDAF_MAX_NUM,
+
+ VC_HDR_MIN_NUM = VC_PDAF_MAX_NUM,
+ VC_HDR_MVHDR = VC_HDR_MIN_NUM,
+ VC_HDR_MAX_NUM,
+
+ VC_3HDR_MIN_NUM = VC_HDR_MAX_NUM,
+ VC_3HDR_EMBEDDED = VC_3HDR_MIN_NUM,
+ VC_3HDR_FLICKER,
+ VC_3HDR_Y,
+ VC_3HDR_AE,
+ VC_3HDR_MAX_NUM,
+
+ VC_STAGGER_MIN_NUM = VC_3HDR_MAX_NUM,
+ VC_STAGGER_EMBEDDED = VC_STAGGER_MIN_NUM,
+ VC_STAGGER_NE,
+ VC_STAGGER_ME,
+ VC_STAGGER_SE,
+ VC_STAGGER_MAX_NUM,
+
+ VC_YUV_MIN_NUM = VC_STAGGER_MAX_NUM,
+ VC_YUV_Y = VC_YUV_MIN_NUM,
+ VC_YUV_UV,
+ VC_YUV_MAX_NUM,
+
+ VC_RAW_EXT_MIN_NUM = VC_YUV_MAX_NUM,
+ VC_RAW_W_DATA = VC_RAW_EXT_MIN_NUM,
+ VC_RAW_PROCESSED_DATA,
+ VC_RAW_EXT_MAX_NUM,
+
+ VC_GENERAL_DATA_MIN_NUM = VC_RAW_EXT_MAX_NUM,
+ VC_GENERAL_EMBEDDED = VC_GENERAL_DATA_MIN_NUM,
+ VC_GENERAL_DATA_MAX_NUM,
+
+ VC_MAX_NUM = VC_GENERAL_DATA_MAX_NUM,
+};
+
+enum {
+ PAD_SINK = 0,
+ PAD_SRC_RAW0,
+ PAD_SRC_RAW1,
+ PAD_SRC_RAW2,
+ PAD_SRC_RAW_W0,
+ PAD_SRC_RAW_EXT0,
+ PAD_SRC_PDAF0,
+ PAD_SRC_PDAF1,
+ PAD_SRC_PDAF2,
+ PAD_SRC_PDAF3,
+ PAD_SRC_PDAF4,
+ PAD_SRC_PDAF5,
+ PAD_SRC_PDAF6,
+ PAD_SRC_HDR0,
+ PAD_SRC_HDR1,
+ PAD_SRC_HDR2,
+ PAD_SRC_GENERAL0,
+ PAD_MAXCNT,
+ PAD_ERR = 0xffff,
+};
+
+#endif /* _KD_IMGSENSOR_DATA_H */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
new file mode 100644
index 000000000000..0bad8f307c10
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_DEF_H__
+#define __MTK_CAM_SENINF_DEF_H__
+
+#define SENINF_VC_MAXCNT 8
+#define SENINF_DEF_PIXEL_MODE 2
+
+#define SENINF_CLK_MARGIN_IN_PERCENT 0
+#define HW_BUF_EFFECT 10
+
+#define SENINF_HS_TRAIL_EN_CONDITION 1450000000
+#define SENINF_TIMESTAMP_CLK 1000
+#define ISP_CLK_LOW 273000000
+
+#define SENINF_CPHY_SETTLE_DELAY_DT 0x10
+#define SENINF_DPHY_SETTLE_DELAY_DT 0x10
+#define SENINF_SETTLE_DELAY_CK 0x11
+#define SENINF_HS_TRAIL_PARAMETER 0x34
+
+#define SENSOR_CLOCK_POLARITY_HIGH 0
+#define SENSOR_CLOCK_POLARITY_LOW 1
+#define NUM_PORTS 2
+#define DEFAULT_WIDTH 1600
+#define DEFAULT_HEIGHT 1200
+
+enum CSI_PORT {
+ CSI_PORT_0 = 0,
+ CSI_PORT_1,
+ CSI_PORT_2,
+ CSI_PORT_3,
+ CSI_PORT_4,
+ CSI_PORT_5,
+ CSI_PORT_0A,
+ CSI_PORT_0B,
+ CSI_PORT_1A,
+ CSI_PORT_1B,
+ CSI_PORT_2A,
+ CSI_PORT_2B,
+ CSI_PORT_3A,
+ CSI_PORT_3B,
+ CSI_PORT_4A,
+ CSI_PORT_4B,
+ CSI_PORT_5A,
+ CSI_PORT_5B,
+ CSI_PORT_MAX_NUM,
+};
+
+#define SENINF_CSI_PORT_NAMES \
+ "0", \
+ "1", \
+ "2", \
+ "3", \
+ "4", \
+ "5", \
+ "0A", \
+ "0B", \
+ "1A", \
+ "1B", \
+ "2A", \
+ "2B", \
+ "3A", \
+ "3B", \
+ "4A", \
+ "4B", \
+ "5A", \
+ "5B", \
+
+enum SENINF_PHY_VER_ENUM {
+ SENINF_PHY_2_0,
+ SENINF_PHY_VER_NUM,
+};
+
+#define MTK_CSI_PHY_VERSIONS "mtk_csi_phy_2_0"
+
+enum SENINF_ENUM {
+ SENINF_1,
+ SENINF_2,
+ SENINF_3,
+ SENINF_4,
+ SENINF_5,
+ SENINF_6,
+ SENINF_7,
+ SENINF_8,
+ SENINF_9,
+ SENINF_10,
+ SENINF_11,
+ SENINF_12,
+ SENINF_NUM,
+};
+
+enum SENINF_MUX_ENUM {
+ SENINF_MUX1,
+ SENINF_MUX2,
+ SENINF_MUX3,
+ SENINF_MUX4,
+ SENINF_MUX5,
+ SENINF_MUX6,
+ SENINF_MUX7,
+ SENINF_MUX8,
+ SENINF_MUX9,
+ SENINF_MUX10,
+ SENINF_MUX11,
+ SENINF_MUX12,
+ SENINF_MUX13,
+ SENINF_MUX_NUM,
+ SENINF_MUX_ERROR = -1,
+};
+
+enum SENINF_CAM_MUX_ENUM {
+ SENINF_CAM_MUX0,
+ SENINF_CAM_MUX1,
+ SENINF_CAM_MUX2,
+ SENINF_CAM_MUX3,
+ SENINF_CAM_MUX4,
+ SENINF_CAM_MUX5,
+ SENINF_CAM_MUX6,
+ SENINF_CAM_MUX7,
+ SENINF_CAM_MUX8,
+ SENINF_CAM_MUX9,
+ SENINF_CAM_MUX10,
+ SENINF_CAM_MUX11,
+ SENINF_CAM_MUX12,
+ SENINF_CAM_MUX13,
+ SENINF_CAM_MUX14,
+ SENINF_CAM_MUX15,
+ SENINF_CAM_MUX_NUM,
+ SENINF_CAM_MUX_ERR = 0xff
+};
+
+/* 0:CSI2(2.5G), 3: parallel, 8:NCSI2(1.5G) */
+enum SENINF_SOURCE_ENUM {
+ CSI2 = 0x0,
+ TEST_MODEL = 0x1,
+ CCIR656 = 0x2,
+ PARALLEL_SENSOR = 0x3,
+ SERIAL_SENSOR = 0x4,
+ HD_TV = 0x5,
+ EXT_CSI2_OUT1 = 0x6,
+ EXT_CSI2_OUT2 = 0x7,
+ MIPI_SENSOR = 0x8,
+ VIRTUAL_CHANNEL_1 = 0x9,
+ VIRTUAL_CHANNEL_2 = 0xA,
+ VIRTUAL_CHANNEL_3 = 0xB,
+ VIRTUAL_CHANNEL_4 = 0xC,
+ VIRTUAL_CHANNEL_5 = 0xD,
+ VIRTUAL_CHANNEL_6 = 0xE,
+};
+
+enum SENINF_CSI2_ENUM {
+ CSI2_1_5G = 0x0,
+ CSI2_2_5G = 0x1,
+ CSI2_2_5G_CPHY = 0x2,
+};
+
+enum TG_FORMAT_ENUM {
+ FMT_RAW_8BIT = 0x0,
+ FMT_RAW_10BIT = 0x1,
+ FMT_RAW_12BIT = 0x2,
+ FMT_YUV422 = 0x3,
+ FMT_RAW_14BIT = 0x4,
+ FMT_RGB565_MIPI = 0x5,
+ FMT_RGB888_MIPI = 0x6,
+ FMT_JPEG = 0x7
+};
+
+enum {
+ CLK_CAM_SENINF = 0,
+ CLK_TOP_SENINF,
+ CLK_TOP_SENINF1,
+ CLK_TOP_SENINF2,
+ CLK_TOP_SENINF3,
+ CLK_TOP_SENINF4,
+ CLK_TOP_SENINF5,
+ CLK_TOP_SENINF_END,
+ CLK_TOP_CAMTM = CLK_TOP_SENINF_END,
+ CLK_MAXCNT,
+};
+
+#define SENINF_CLK_NAMES \
+ "clk_cam_seninf", \
+ "clk_top_seninf", \
+ "clk_top_seninf1", \
+ "clk_top_seninf2", \
+ "clk_top_seninf3", \
+ "clk_top_seninf4", \
+ "clk_top_seninf5", \
+ "clk_top_camtm", \
+
+#endif /* __MTK_CAM_SENINF_DEF_H__ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
new file mode 100644
index 000000000000..a8fb48070304
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
@@ -0,0 +1,1741 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2022 MediaTek Inc.
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/of_graph.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/nvmem-consumer.h>
+
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-device.h>
+
+#include "mtk_cam.h"
+#include "mtk_cam-seninf-def.h"
+#include "mtk_cam-seninf.h"
+#include "mtk_cam-seninf-hw.h"
+#include "mtk_cam-seninf-route.h"
+#include "kd_imgsensor_define_v4l2.h"
+
+#define sd_to_ctx(__sd) container_of(__sd, struct seninf_ctx, subdev)
+#define notifier_to_ctx(__n) container_of(__n, struct seninf_ctx, notifier)
+#define ctrl_hdl_to_ctx(__h) container_of(__h, struct seninf_ctx, ctrl_handler)
+
+static const char * const csi_port_names[] = {
+ SENINF_CSI_PORT_NAMES
+};
+
+static const char * const clk_names[] = {
+ SENINF_CLK_NAMES
+};
+
+static const char * const set_reg_names[] = {
+ SET_REG_KEYS_NAMES
+};
+
+static ssize_t status_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return mtk_cam_seninf_show_status(dev, attr, buf);
+}
+
+static DEVICE_ATTR_RO(status);
+
+static ssize_t err_status_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return mtk_cam_seninf_show_err_status(dev, attr, buf);
+}
+
+static DEVICE_ATTR_RO(err_status);
+
+static ssize_t debug_ops_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += snprintf(buf + len, PAGE_SIZE - len, "This is debug ops message\n");
+
+ return len;
+}
+
+enum REG_OPS_CMD {
+ REG_OPS_CMD_ID,
+ REG_OPS_CMD_CSI,
+ REG_OPS_CMD_RG,
+ REG_OPS_CMD_VAL,
+ REG_OPS_CMD_MAX_NUM,
+};
+
+static ssize_t debug_ops_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ char delim[] = " ";
+ char csi_names[20];
+ char *token = NULL;
+ char *sbuf = kcalloc(count + 1, sizeof(char), GFP_KERNEL);
+ char *s = sbuf;
+ int ret;
+ char *arg[REG_OPS_CMD_MAX_NUM];
+ struct seninf_core *core = dev_get_drvdata(dev);
+ struct seninf_ctx *ctx;
+ int csi_port = -1;
+ int rg_idx = -1;
+ u32 val, i, num_para = 0;
+
+ if (!sbuf)
+ goto ERR_DEBUG_OPS_STORE;
+
+ memcpy(sbuf, buf, count);
+
+ token = strsep(&s, delim);
+ while (token && num_para < REG_OPS_CMD_MAX_NUM) {
+ if (strlen(token)) {
+ arg[num_para] = token;
+ num_para++;
+ }
+
+ token = strsep(&s, delim);
+ }
+
+ if (num_para != REG_OPS_CMD_MAX_NUM) {
+ dev_info(dev, "Wrong command parameter number\n");
+ goto ERR_DEBUG_OPS_STORE;
+ }
+
+ if (strncmp("SET_REG", arg[REG_OPS_CMD_ID], sizeof("SET_REG")) == 0) {
+ for (i = 0; i < REG_KEY_MAX_NUM; i++) {
+ if (!strcasecmp(arg[REG_OPS_CMD_RG], set_reg_names[i]))
+ rg_idx = i;
+ }
+ if (rg_idx < 0)
+ goto ERR_DEBUG_OPS_STORE;
+
+ ret = kstrtouint(arg[REG_OPS_CMD_VAL], 0, &val);
+ if (ret)
+ goto ERR_DEBUG_OPS_STORE;
+
+ for (i = 0; i < CSI_PORT_MAX_NUM; i++) {
+ memset(csi_names, 0, ARRAY_SIZE(csi_names));
+ snprintf(csi_names, 10, "csi-%s", csi_port_names[i]);
+ if (!strcasecmp(arg[REG_OPS_CMD_CSI], csi_names))
+ csi_port = i;
+ }
+
+ if (csi_port < 0)
+ goto ERR_DEBUG_OPS_STORE;
+
+ /* reg call */
+ mutex_lock(&core->mutex);
+
+ list_for_each_entry(ctx, &core->list, list) {
+ if (csi_port == ctx->port)
+ mtk_cam_seninf_set_reg(ctx, rg_idx, val);
+ }
+
+ mutex_unlock(&core->mutex);
+ }
+
+ERR_DEBUG_OPS_STORE:
+
+ kfree(sbuf);
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(debug_ops);
+
+static int seninf_core_pm_runtime_enable(struct seninf_core *core)
+{
+ int i, ret;
+
+ core->pm_domain_cnt = of_count_phandle_with_args(core->dev->of_node,
+ "power-domains",
+ "#power-domain-cells");
+ if (core->pm_domain_cnt == 1) {
+ pm_runtime_enable(core->dev);
+ } else if (core->pm_domain_cnt > 1) {
+ core->pm_domain_devs =
+ devm_kcalloc(core->dev, core->pm_domain_cnt,
+ sizeof(*core->pm_domain_devs), GFP_KERNEL);
+
+ if (!core->pm_domain_devs)
+ return -ENOMEM;
+
+ for (i = 0; i < core->pm_domain_cnt; i++) {
+ core->pm_domain_devs[i] =
+ dev_pm_domain_attach_by_id(core->dev, i);
+
+ if (IS_ERR(core->pm_domain_devs[i])) {
+ ret = PTR_ERR(core->pm_domain_devs[i]);
+
+ dev_info(core->dev,
+ "%s: fail to probe pm id: %d (%d)\n",
+ __func__, i, ret);
+
+ goto detach_pm;
+ }
+ }
+ }
+
+ return 0;
+
+detach_pm:
+ for (--i; i >= 0; i--)
+ dev_pm_domain_detach(core->pm_domain_devs[i], true);
+
+ return ret;
+}
+
+static int seninf_core_pm_runtime_disable(struct seninf_core *core)
+{
+ int i;
+
+ if (core->pm_domain_cnt == 1) {
+ pm_runtime_disable(core->dev);
+ } else {
+ if (!core->pm_domain_devs)
+ return -EINVAL;
+
+ for (i = 0; i < core->pm_domain_cnt; i++) {
+ if (core->pm_domain_devs[i])
+ dev_pm_domain_detach(core->pm_domain_devs[i], 1);
+ }
+ }
+
+ return 0;
+}
+
+static int seninf_core_pm_runtime_get_sync(struct seninf_core *core)
+{
+ int ret, i;
+
+ /* for one pm_domain */
+ if (core->pm_domain_cnt == 1) {
+ ret = pm_runtime_resume_and_get(core->dev);
+ if (ret < 0) {
+ dev_info(core->dev, "fail to resume seninf_core\n");
+ return ret;
+ }
+
+ return 0;
+ }
+
+ if (!core->pm_domain_devs)
+ return -EINVAL;
+
+ /* more than one pm_domain */
+ for (i = 0; i < core->pm_domain_cnt; i++) {
+ if (core->pm_domain_devs[i]) {
+ ret = pm_runtime_resume_and_get(core->pm_domain_devs[i]);
+ if (ret < 0) {
+ dev_info(core->dev,
+ "fail to resume pm_domain_devs(%d)\n", i);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int seninf_core_pm_runtime_put(struct seninf_core *core)
+{
+ int i;
+
+ if (core->pm_domain_cnt == 1) {
+ pm_runtime_put_sync(core->dev);
+ } else {
+ if (!core->pm_domain_devs || core->pm_domain_cnt < 1)
+ return -EINVAL;
+
+ for (i = core->pm_domain_cnt - 1; i >= 0; i--) {
+ if (core->pm_domain_devs[i])
+ pm_runtime_put_sync(core->pm_domain_devs[i]);
+ }
+ }
+
+ return 0;
+}
+
+static irqreturn_t mtk_irq_seninf(int irq, void *data)
+{
+ mtk_cam_seninf_irq_handler(irq, data);
+ return IRQ_HANDLED;
+}
+
+static int get_seninf_cfg(struct device *dev, struct seninf_core *core)
+{
+ int ret;
+ const char *ver;
+
+ ret = of_property_read_string(dev->of_node, "mtk_csi_phy_ver", &ver);
+ if (ret) {
+ dev_err(dev,
+ "Fail to get mtk_csi_phy_ver property (err=%d)\n", ret);
+
+ return ret;
+ }
+
+ if (!strcasecmp(ver, MTK_CSI_PHY_VERSIONS)) {
+ dev_info(dev, "%s: mtk_csi_phy_ver = %s\n", __func__, ver);
+
+ of_property_read_u32(dev->of_node, "seninf_num",
+ &g_seninf_cfg->seninf_num);
+ of_property_read_u32(dev->of_node, "mux_num",
+ &g_seninf_cfg->mux_num);
+ of_property_read_u32(dev->of_node, "cam_mux_num",
+ &g_seninf_cfg->cam_mux_num);
+ of_property_read_u32(dev->of_node, "pref_mux_num",
+ &g_seninf_cfg->pref_mux_num);
+
+ dev_info(dev,
+ "%s: seninf_num = %d, mux_num = %d, cam_mux_num = %d, pref_mux_num =%d\n",
+ __func__,
+ g_seninf_cfg->seninf_num,
+ g_seninf_cfg->mux_num,
+ g_seninf_cfg->cam_mux_num,
+ g_seninf_cfg->pref_mux_num);
+
+ return 0;
+ }
+
+ dev_err(dev, "DTS seninf config not correct.\n");
+
+ return -1;
+}
+
+static int seninf_core_probe(struct platform_device *pdev)
+{
+ int i, ret, irq;
+ struct resource *res;
+ struct seninf_core *core;
+ struct device *dev = &pdev->dev;
+
+ core = devm_kzalloc(&pdev->dev, sizeof(*core), GFP_KERNEL);
+ if (!core)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, core);
+ core->dev = dev;
+ mutex_init(&core->mutex);
+ INIT_LIST_HEAD(&core->list);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
+ core->reg_if = devm_ioremap_resource(dev, res);
+ if (IS_ERR(core->reg_if))
+ return PTR_ERR(core->reg_if);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ana-rx");
+ core->reg_ana = devm_ioremap_resource(dev, res);
+ if (IS_ERR(core->reg_ana))
+ return PTR_ERR(core->reg_ana);
+
+ ret = get_seninf_cfg(dev, core);
+ if (ret) {
+ dev_err(dev, "failed to get seninf ops\n");
+ return ret;
+ }
+ mtk_cam_seninf_init_res(core);
+
+ spin_lock_init(&core->spinlock_irq);
+ irq = platform_get_irq(pdev, 0);
+ if (!irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -ENODEV;
+ }
+
+ ret = devm_request_irq(dev, irq, mtk_irq_seninf, 0,
+ dev_name(dev), core);
+ if (ret) {
+ dev_err(dev, "failed to request irq=%d\n", irq);
+ return ret;
+ }
+ dev_dbg(dev, "registered irq=%d\n", irq);
+
+ /* default platform properties */
+ core->cphy_settle_delay_dt = SENINF_CPHY_SETTLE_DELAY_DT;
+ core->dphy_settle_delay_dt = SENINF_DPHY_SETTLE_DELAY_DT;
+ core->settle_delay_ck = SENINF_SETTLE_DELAY_CK;
+ core->hs_trail_parameter = SENINF_HS_TRAIL_PARAMETER;
+
+ /* read platform properties from device tree */
+ of_property_read_u32(dev->of_node, "cphy_settle_delay_dt",
+ &core->cphy_settle_delay_dt);
+ of_property_read_u32(dev->of_node, "dphy_settle_delay_dt",
+ &core->dphy_settle_delay_dt);
+ of_property_read_u32(dev->of_node, "settle_delay_ck",
+ &core->settle_delay_ck);
+ of_property_read_u32(dev->of_node, "hs_trail_parameter",
+ &core->hs_trail_parameter);
+
+ core->dfs.cnt = 0;
+ core->dfs.reg = NULL;
+
+ ret = seninf_core_pm_runtime_enable(core);
+ if (ret) {
+ dev_info(dev, "failed to enable seninf_core_pm_runtime\n");
+ return ret;
+ }
+
+ for (i = 0; i < CLK_MAXCNT; i++) {
+ core->clk[i] = devm_clk_get(dev, clk_names[i]);
+ if (IS_ERR(core->clk[i])) {
+ dev_info(dev, "failed to get %s\n", clk_names[i]);
+ core->clk[i] = NULL;
+ /* ignore not define seninf */
+ }
+ }
+
+ ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+ if (ret) {
+ dev_info(dev, "%s: failed to create sub devices\n", __func__);
+ return ret;
+ }
+
+ ret = device_create_file(dev, &dev_attr_status);
+ if (ret)
+ dev_info(dev, "failed to create sysfs status\n");
+
+ ret = device_create_file(dev, &dev_attr_debug_ops);
+ if (ret)
+ dev_info(dev, "failed to create sysfs debug ops\n");
+
+ ret = device_create_file(dev, &dev_attr_err_status);
+ if (ret)
+ dev_info(dev, "failed to create sysfs status\n");
+
+ dev_dbg(dev, "camsys | start %s\n", __func__);
+
+ return 0;
+}
+
+static void seninf_core_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct seninf_core *core = dev_get_drvdata(dev);
+
+ device_remove_file(dev, &dev_attr_status);
+ device_remove_file(dev, &dev_attr_debug_ops);
+ device_remove_file(dev, &dev_attr_err_status);
+ of_platform_depopulate(dev);
+ seninf_core_pm_runtime_disable(core);
+
+ dev_dbg(dev, "camsys | start %s\n", __func__);
+}
+
+static const struct of_device_id seninf_core_of_match[] = {
+ { .compatible = "mediatek,seninf-core" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, seninf_core_of_match);
+
+struct platform_driver seninf_core_pdrv = {
+ .probe = seninf_core_probe,
+ .remove = seninf_core_remove,
+ .driver = {
+ .name = "seninf-core",
+ .of_match_table = seninf_core_of_match,
+ },
+};
+
+static int get_csi_port(struct device *dev, int *port)
+{
+ int i, ret;
+ const char *name;
+
+ ret = of_property_read_string(dev->of_node, "csi-port", &name);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < CSI_PORT_MAX_NUM; i++) {
+ if (!strcasecmp(name, csi_port_names[i])) {
+ *port = i;
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+static int seninf_subscribe_event(struct v4l2_subdev *sd,
+ struct v4l2_fh *fh,
+ struct v4l2_event_subscription *sub)
+{
+ switch (sub->type) {
+ case V4L2_EVENT_CTRL:
+ return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
+ default:
+ return -EINVAL;
+ }
+}
+
+static void init_fmt(struct seninf_ctx *ctx)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ctx->fmt); i++) {
+ ctx->fmt[i].format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
+ ctx->fmt[i].format.width = DEFAULT_WIDTH;
+ ctx->fmt[i].format.height = DEFAULT_HEIGHT;
+ ctx->fmt[i].format.field = V4L2_FIELD_NONE;
+ ctx->fmt[i].format.colorspace = V4L2_COLORSPACE_SRGB;
+ ctx->fmt[i].format.xfer_func = V4L2_XFER_FUNC_DEFAULT;
+ ctx->fmt[i].format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ ctx->fmt[i].format.quantization = V4L2_QUANTIZATION_DEFAULT;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ctx->vcinfo.vc); i++)
+ ctx->vcinfo.vc[i].pixel_mode = SENINF_DEF_PIXEL_MODE;
+}
+
+static int dev_read_csi_efuse(struct seninf_ctx *ctx)
+{
+ struct nvmem_cell *cell;
+ size_t len = 0;
+ u32 *buf;
+
+ ctx->m_csi_efuse = 0x00000000;
+
+ cell = nvmem_cell_get(ctx->dev, "rg_csi");
+ dev_info(ctx->dev, "ctx->port = %d\n", ctx->port);
+ if (IS_ERR(cell)) {
+ if (PTR_ERR(cell) == -EPROBE_DEFER) {
+ dev_info(ctx->dev,
+ "read csi efuse returned with error cell %d\n",
+ -EPROBE_DEFER - EPROBE_DEFER);
+ return PTR_ERR(cell);
+ }
+ dev_info(ctx->dev,
+ "read csi efuse returned with error cell %d\n", -1);
+ return -1;
+ }
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+ if (IS_ERR(buf)) {
+ dev_info(ctx->dev, "read csi efuse returned with error buf\n");
+ return PTR_ERR(buf);
+ }
+ ctx->m_csi_efuse = *buf;
+ kfree(buf);
+ dev_info(ctx->dev, "Efuse Data: 0x%08x\n", ctx->m_csi_efuse);
+
+ return 0;
+}
+
+static const struct v4l2_mbus_framefmt fmt_default = {
+ .code = MEDIA_BUS_FMT_SBGGR10_1X10,
+ .width = DEFAULT_WIDTH,
+ .height = DEFAULT_HEIGHT,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .xfer_func = V4L2_XFER_FUNC_DEFAULT,
+ .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
+ .quantization = V4L2_QUANTIZATION_DEFAULT,
+};
+
+static int mtk_cam_seninf_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state)
+{
+ struct v4l2_mbus_framefmt *mf;
+ unsigned int i;
+
+ for (i = 0; i < sd->entity.num_pads; i++) {
+ mf = v4l2_subdev_state_get_format(sd_state, i);
+ *mf = fmt_default;
+ }
+
+ return 0;
+}
+
+static int mtk_cam_seninf_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+ struct v4l2_mbus_framefmt *format;
+ char sink_format_changed = 0;
+
+ if (fmt->pad < PAD_SINK || fmt->pad >= PAD_MAXCNT)
+ return -EINVAL;
+
+ format = &ctx->fmt[fmt->pad].format;
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
+
+ dev_dbg(ctx->dev,
+ "s_fmt pad %d code/res 0x%x/%dx%d which %d=> 0x%x/%dx%d\n",
+ fmt->pad,
+ fmt->format.code,
+ fmt->format.width,
+ fmt->format.height,
+ fmt->which,
+ format->code,
+ format->width,
+ format->height);
+ } else {
+ /* Update vcinfo once the SINK format changed */
+ if (fmt->pad == PAD_SINK)
+ sink_format_changed = 1;
+
+ format->code = fmt->format.code;
+ format->width = fmt->format.width;
+ format->height = fmt->format.height;
+
+ if (sink_format_changed && !ctx->is_test_model)
+ mtk_cam_seninf_get_vcinfo(ctx);
+
+ dev_info(ctx->dev,
+ "s_fmt pad %d code/res 0x%x/%dx%d which %d=> 0x%x/%dx%d\n",
+ fmt->pad,
+ fmt->format.code,
+ fmt->format.width,
+ fmt->format.height,
+ fmt->which,
+ format->code,
+ format->width,
+ format->height);
+ }
+
+ return 0;
+}
+
+static int mtk_cam_seninf_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+ struct v4l2_mbus_framefmt *format;
+
+ if (fmt->pad < PAD_SINK || fmt->pad >= PAD_MAXCNT)
+ return -EINVAL;
+
+ format = &ctx->fmt[fmt->pad].format;
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ fmt->format = *v4l2_subdev_state_get_format(sd_state, fmt->pad);
+ } else {
+ fmt->format.code = format->code;
+ fmt->format.width = format->width;
+ fmt->format.height = format->height;
+ fmt->format.field = format->field;
+ fmt->format.colorspace = format->colorspace;
+ fmt->format.xfer_func = format->xfer_func;
+ fmt->format.ycbcr_enc = format->ycbcr_enc;
+ fmt->format.quantization = format->quantization;
+ }
+
+ return 0;
+}
+
+static int set_test_model(struct seninf_ctx *ctx, char enable)
+{
+ struct seninf_vc *vc[] = { NULL, NULL, NULL, NULL, NULL };
+ int i = 0, ret = 0, vc_used = 0;
+ struct seninf_mux *mux;
+ int pref_idx[] = { 0, 1, 2, 3, 4 };
+
+ if (ctx->is_test_model == 1) {
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
+ } else if (ctx->is_test_model == 2) {
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW1);
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW2);
+ } else if (ctx->is_test_model == 3) {
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
+ vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_PDAF0);
+ } else {
+ dev_info(ctx->dev, "testmodel%d invalid\n", ctx->is_test_model);
+ return -1;
+ }
+
+ for (; i < vc_used; ++i) {
+ if (!vc[i]) {
+ dev_info(ctx->dev, "vc not found\n");
+ return -1;
+ }
+ }
+
+ if (enable) {
+ ret = pm_runtime_resume_and_get(ctx->dev);
+ if (ret < 0) {
+ dev_info(ctx->dev, "failed at pm_runtime_resume_and_get\n");
+ return ret;
+ }
+
+ if (ctx->core->clk[CLK_TOP_CAMTM])
+ ret = clk_prepare_enable(ctx->core->clk[CLK_TOP_CAMTM]);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < vc_used; ++i) {
+ mux = mtk_cam_seninf_mux_get_pref(ctx,
+ pref_idx,
+ ARRAY_SIZE(pref_idx));
+ if (!mux)
+ return -EBUSY;
+ vc[i]->mux = mux->idx;
+ vc[i]->cam = ctx->pad2cam[vc[i]->out_pad];
+ vc[i]->enable = 1;
+
+ dev_info(ctx->dev,
+ "test mode mux %d, cam %d, pixel mode %d\n",
+ vc[i]->mux, vc[i]->cam, vc[i]->pixel_mode);
+
+ mtk_cam_seninf_set_test_model(ctx, vc[i]->mux,
+ vc[i]->cam,
+ vc[i]->pixel_mode);
+
+ if (vc[i]->out_pad == PAD_SRC_PDAF0)
+ mdelay(40);
+ else
+ usleep_range(40, 60);
+ }
+ } else {
+ mtk_cam_seninf_set_idle(ctx);
+ mtk_cam_seninf_release_mux(ctx);
+
+ if (ctx->core->clk[CLK_TOP_CAMTM])
+ clk_disable_unprepare(ctx->core->clk[CLK_TOP_CAMTM]);
+
+ pm_runtime_put_sync(ctx->dev);
+ }
+
+ ctx->streaming = enable;
+
+ return 0;
+}
+
+static int config_hw(struct seninf_ctx *ctx)
+{
+ int i, intf, skip_mux_ctrl;
+ int hs_pol, vs_pol, vc_sel, dt_sel, dt_en;
+ struct seninf_vcinfo *vcinfo;
+ struct seninf_vc *vc;
+ struct seninf_mux *mux, *mux_by_grp[SENINF_VC_MAXCNT] = { 0 };
+
+ intf = ctx->seninf_idx;
+ vcinfo = &ctx->vcinfo;
+
+ mtk_cam_seninf_reset(ctx, intf);
+
+ mtk_cam_seninf_set_vc(ctx, intf, vcinfo);
+
+ mtk_cam_seninf_set_csi_mipi(ctx);
+
+ /* should set false */
+ hs_pol = 0;
+ vs_pol = 0;
+
+ for (i = 0; i < vcinfo->cnt; i++) {
+ vc = &vcinfo->vc[i];
+
+ /* alloc mux by group */
+ if (mux_by_grp[vc->group]) {
+ mux = mux_by_grp[vc->group];
+ skip_mux_ctrl = 1;
+ } else {
+ int pref_idx[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
+ mux_by_grp[vc->group] =
+ mtk_cam_seninf_mux_get_pref(ctx,
+ pref_idx,
+ g_seninf_cfg->pref_mux_num);
+ mux = mux_by_grp[vc->group];
+ skip_mux_ctrl = 0;
+ }
+
+ if (!mux) {
+ mtk_cam_seninf_release_mux(ctx);
+ return -EBUSY;
+ }
+
+ vc->mux = mux->idx;
+ vc->cam = ctx->pad2cam[vc->out_pad];
+
+ if (!skip_mux_ctrl) {
+ mtk_cam_seninf_mux(ctx, vc->mux);
+ mtk_cam_seninf_set_mux_ctrl(ctx, vc->mux,
+ hs_pol, vs_pol,
+ MIPI_SENSOR + vc->group,
+ vc->pixel_mode);
+
+ mtk_cam_seninf_set_top_mux_ctrl(ctx, vc->mux, intf);
+
+ /* disable mtk_cam_seninf_set_mux_crop length limit */
+ }
+ dev_info(ctx->dev, "ctx->pad2cam[%d] %d vc->out_pad %d vc->cam %d, i %d",
+ vc->out_pad, ctx->pad2cam[vc->out_pad], vc->out_pad, vc->cam, i);
+
+ if (vc->cam != 0xff) {
+ vc_sel = vc->vc;
+ dt_sel = vc->dt;
+ dt_en = !!dt_sel;
+
+ /* CMD_SENINF_FINALIZE_CAM_MUX */
+ mtk_cam_seninf_set_cammux_vc(ctx, vc->cam,
+ vc_sel, dt_sel,
+ dt_en, dt_en);
+ mtk_cam_seninf_set_cammux_src(ctx, vc->mux, vc->cam,
+ vc->exp_hsize,
+ vc->exp_vsize);
+ mtk_cam_seninf_set_cammux_chk_pixel_mode(ctx,
+ vc->cam,
+ vc->pixel_mode);
+ mtk_cam_seninf_cammux(ctx, vc->cam);
+
+ dev_info(ctx->dev, "vc[%d] pad %d intf %d mux %d cam %d\n",
+ i, vc->out_pad, intf, vc->mux, vc->cam);
+ } else {
+ dev_info(ctx->dev,
+ "not set camtg yet, vc[%d] pad %d intf %d mux %d cam %d\n",
+ i, vc->out_pad, intf, vc->mux, vc->cam);
+ }
+ }
+ return 0;
+}
+
+static int calc_buffered_pixel_rate(struct device *dev,
+ s64 width, s64 height,
+ s64 hblank, s64 vblank,
+ int fps_n, int fps_d, s64 *result)
+{
+ s64 orig_pixel_rate = *result;
+ u64 buffered_pixel_rate, pclk, k;
+
+ if (fps_d == 0 || width == 0 || hblank == 0 || ISP_CLK_LOW == 0) {
+ dev_info(dev,
+ "Prevent divided by 0, fps_d= %d, w= %llu, h= %llu, ISP_CLK= %d\n",
+ fps_d, width, hblank, ISP_CLK_LOW);
+ return 0;
+ }
+
+ /* calculate pclk */
+ pclk = (width + hblank) * (height + vblank) * fps_n;
+ do_div(pclk, fps_d);
+
+ /* calculate buffered pixel_rate */
+ buffered_pixel_rate = orig_pixel_rate * width;
+ k = HW_BUF_EFFECT * orig_pixel_rate;
+ do_div(k, ISP_CLK_LOW);
+ do_div(buffered_pixel_rate, (width + hblank - k));
+ *result = buffered_pixel_rate;
+
+ dev_info(dev,
+ "%s: w %lld h %lld hb %lld vb %lld fps %d/%d pclk %lld->%lld orig %lld k %lld hbe %d\n",
+ __func__, width, height, hblank, vblank,
+ fps_n, fps_d, pclk, buffered_pixel_rate, orig_pixel_rate, k, HW_BUF_EFFECT);
+
+ return 0;
+}
+
+static int get_buffered_pixel_rate(struct seninf_ctx *ctx,
+ struct v4l2_subdev *sd, int sd_pad_idx,
+ s64 *result)
+{
+ int ret;
+ struct v4l2_ctrl *ctrl;
+ struct v4l2_subdev_format fmt;
+ struct v4l2_subdev_frame_interval fi;
+ s64 width, height, hblank, vblank;
+
+ fmt.pad = sd_pad_idx;
+ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
+ if (ret) {
+ dev_info(ctx->dev, "no get_fmt in %s\n", sd->name);
+ return ret;
+ }
+
+ width = fmt.format.width;
+ height = fmt.format.height;
+
+ memset(&fi, 0, sizeof(fi));
+ fi.pad = sd_pad_idx;
+ ret = v4l2_subdev_call_state_active(sd, pad, get_frame_interval, &fi);
+ if (ret) {
+ dev_info(ctx->dev, "no get_frame_interval in %s\n", sd->name);
+ return ret;
+ }
+
+ ctrl = v4l2_ctrl_find(sd->ctrl_handler, V4L2_CID_HBLANK);
+ if (!ctrl) {
+ dev_info(ctx->dev, "no hblank in %s\n", sd->name);
+ return -EINVAL;
+ }
+
+ hblank = v4l2_ctrl_g_ctrl(ctrl);
+
+ ctrl = v4l2_ctrl_find(sd->ctrl_handler, V4L2_CID_VBLANK);
+ if (!ctrl) {
+ dev_info(ctx->dev, "no vblank in %s\n", sd->name);
+ return -EINVAL;
+ }
+
+ vblank = v4l2_ctrl_g_ctrl(ctrl);
+
+ /* update fps */
+ ctx->fps_n = fi.interval.denominator;
+ ctx->fps_d = fi.interval.numerator;
+
+ return calc_buffered_pixel_rate(ctx->dev, width, height, hblank, vblank,
+ ctx->fps_n, ctx->fps_d, result);
+}
+
+static int get_pixel_rate(struct seninf_ctx *ctx, struct v4l2_subdev *sd,
+ s64 *result)
+{
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_find(sd->ctrl_handler, V4L2_CID_PIXEL_RATE);
+ if (!ctrl) {
+ dev_info(ctx->dev, "no pixel rate in subdev %s\n", sd->name);
+ return -EINVAL;
+ }
+
+ *result = v4l2_ctrl_g_ctrl_int64(ctrl);
+
+ return 0;
+}
+
+int update_isp_clk(struct seninf_ctx *ctx)
+{
+ int i, pixelmode;
+ struct seninf_dfs *dfs = &ctx->core->dfs;
+ s64 pixel_rate = -1;
+ u64 dfs_freq;
+ struct seninf_vc *vc;
+ int ret = 0;
+
+ if (!dfs->cnt) {
+ dev_info(ctx->dev, "dfs not ready.\n");
+ return ret;
+ }
+
+ vc = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
+ if (!vc) {
+ dev_info(ctx->dev, "failed to get vc\n");
+ return -1;
+ }
+ dev_info(ctx->dev,
+ "%s dfs->cnt %d pixel mode %d customized_pixel_rate %lld, buffered_pixel_rate %lld mipi_pixel_rate %lld\n",
+ __func__, dfs->cnt, vc->pixel_mode, ctx->customized_pixel_rate,
+ ctx->buffered_pixel_rate, ctx->mipi_pixel_rate);
+
+ /* Use SensorPixelrate */
+ if (ctx->customized_pixel_rate) {
+ pixel_rate = ctx->customized_pixel_rate;
+ } else if (ctx->buffered_pixel_rate) {
+ pixel_rate = ctx->buffered_pixel_rate;
+ } else if (ctx->mipi_pixel_rate) {
+ pixel_rate = ctx->mipi_pixel_rate;
+ } else {
+ dev_info(ctx->dev, "failed to get pixel_rate\n");
+ return -EINVAL;
+ }
+
+ pixelmode = vc->pixel_mode;
+ for (i = 0; i < dfs->cnt; i++) {
+ dfs_freq = dfs->freqs[i];
+ dfs_freq = dfs_freq * (100 - SENINF_CLK_MARGIN_IN_PERCENT);
+ do_div(dfs_freq, 100);
+ if ((dfs_freq << pixelmode) >= pixel_rate)
+ break;
+ }
+
+ if (i == dfs->cnt) {
+ dev_info(ctx->dev, "mux is overrun. please adjust pixelmode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int debug_err_detect_initialize(struct seninf_ctx *ctx)
+{
+ struct seninf_core *core;
+ struct seninf_ctx *ctx_;
+
+ core = dev_get_drvdata(ctx->dev->parent);
+
+ core->csi_irq_en_flag = 0;
+
+ list_for_each_entry(ctx_, &core->list, list) {
+ ctx_->data_not_enough_flag = 0;
+ ctx_->err_lane_resync_flag = 0;
+ ctx_->crc_err_flag = 0;
+ ctx_->ecc_err_double_flag = 0;
+ ctx_->ecc_err_corrected_flag = 0;
+ ctx_->fifo_overrun_flag = 0;
+ ctx_->size_err_flag = 0;
+ ctx_->data_not_enough_cnt = 0;
+ ctx_->err_lane_resync_cnt = 0;
+ ctx_->crc_err_cnt = 0;
+ ctx_->ecc_err_double_cnt = 0;
+ ctx_->ecc_err_corrected_cnt = 0;
+ ctx_->fifo_overrun_cnt = 0;
+ ctx_->size_err_cnt = 0;
+ }
+
+ return 0;
+}
+
+static int seninf_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ int ret;
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+
+ if (ctx->streaming == enable)
+ return 0;
+
+ if (ctx->is_test_model)
+ return set_test_model(ctx, enable);
+
+ if (!ctx->sensor_sd) {
+ dev_info(ctx->dev, "no sensor\n");
+ return -EFAULT;
+ }
+
+ if (enable) {
+ debug_err_detect_initialize(ctx);
+
+ get_pixel_rate(ctx, ctx->sensor_sd, &ctx->mipi_pixel_rate);
+
+ ctx->buffered_pixel_rate = ctx->mipi_pixel_rate;
+ get_buffered_pixel_rate(ctx, ctx->sensor_sd,
+ ctx->sensor_pad_idx,
+ &ctx->buffered_pixel_rate);
+
+ ret = pm_runtime_resume_and_get(ctx->dev);
+ if (ret < 0) {
+ dev_info(ctx->dev,
+ "%s pm_runtime_resume_and_get ret %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ update_isp_clk(ctx);
+
+ ret = config_hw(ctx);
+ if (ret) {
+ dev_info(ctx->dev, "config_seninf_hw ret %d\n", ret);
+ return ret;
+ }
+
+ /* middleware control sensor fsync after set cam-mux */
+
+ ret = v4l2_subdev_call(ctx->sensor_sd, video, s_stream, 1);
+ if (ret) {
+ dev_info(ctx->dev, "sensor stream-on ret %d\n", ret);
+ return ret;
+ }
+
+ } else {
+ ret = v4l2_subdev_call(ctx->sensor_sd, video, s_stream, 0);
+ if (ret) {
+ dev_info(ctx->dev, "sensor stream-off ret %d\n", ret);
+ return ret;
+ }
+
+ mtk_cam_seninf_set_idle(ctx);
+ mtk_cam_seninf_release_mux(ctx);
+
+ mtk_cam_seninf_poweroff(ctx);
+ pm_runtime_put_sync(ctx->dev);
+ }
+
+ ctx->streaming = enable;
+ return 0;
+}
+
+static const struct v4l2_subdev_pad_ops seninf_subdev_pad_ops = {
+ .link_validate = mtk_cam_link_validate,
+ .set_fmt = mtk_cam_seninf_set_fmt,
+ .get_fmt = mtk_cam_seninf_get_fmt,
+};
+
+static const struct v4l2_subdev_video_ops seninf_subdev_video_ops = {
+ .s_stream = seninf_s_stream,
+};
+
+static const struct v4l2_subdev_core_ops seninf_subdev_core_ops = {
+ .subscribe_event = seninf_subscribe_event,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_internal_ops seninf_subdev_internal_ops = {
+ .init_state = mtk_cam_seninf_init_state,
+};
+
+static const struct v4l2_subdev_ops seninf_subdev_ops = {
+ .core = &seninf_subdev_core_ops,
+ .video = &seninf_subdev_video_ops,
+ .pad = &seninf_subdev_pad_ops,
+};
+
+static int seninf_link_setup(struct media_entity *entity,
+ const struct media_pad *local,
+ const struct media_pad *remote, u32 flags)
+{
+ struct v4l2_subdev *sd;
+ struct seninf_ctx *ctx;
+
+ sd = media_entity_to_v4l2_subdev(entity);
+ if (!sd)
+ return -EINVAL;
+ ctx = v4l2_get_subdevdata(sd);
+ if (!ctx)
+ return -EINVAL;
+
+ if (local->flags & MEDIA_PAD_FL_SOURCE) {
+ if (flags & MEDIA_LNK_FL_ENABLED) {
+ if (!mtk_cam_seninf_get_vc_by_pad(ctx, local->index)) {
+ dev_info(ctx->dev,
+ "%s enable link w/o vc_info pad idex %d\n",
+ __func__, local->index);
+ }
+ }
+ } else {
+ /* Update vcinfo once the link becomes enabled */
+ if (flags & MEDIA_LNK_FL_ENABLED) {
+ ctx->sensor_sd =
+ media_entity_to_v4l2_subdev(remote->entity);
+ ctx->sensor_pad_idx = remote->index;
+ mtk_cam_seninf_get_vcinfo(ctx);
+ }
+ }
+
+ return 0;
+}
+
+static const struct media_entity_operations seninf_media_ops = {
+ .link_setup = seninf_link_setup,
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+struct sensor_async_subdev {
+ struct v4l2_async_connection asc;
+ u32 port;
+ u32 bus_type;
+ u32 lanes;
+};
+
+static int seninf_notifier_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_connection *asc)
+{
+ struct seninf_ctx *ctx = notifier_to_ctx(notifier);
+ struct sensor_async_subdev *s_asd =
+ container_of(asc, struct sensor_async_subdev, asc);
+ int ret;
+
+ dev_info(ctx->dev, "[%s] %s bounded, bus_type:%d, lanes:%d\n",
+ __func__, sd->entity.name, s_asd->bus_type, s_asd->lanes);
+
+ ctx->is_cphy = (s_asd->bus_type == V4L2_MBUS_CSI2_CPHY);
+ ctx->num_data_lanes = s_asd->lanes;
+
+ ret = media_create_pad_link(&sd->entity, 0, &ctx->subdev.entity, 0, 0);
+ if (ret) {
+ dev_info(ctx->dev, "failed to create link for %s\n",
+ sd->entity.name);
+ return ret;
+ }
+
+ ret = v4l2_device_register_subdev_nodes(ctx->subdev.v4l2_dev);
+ if (ret) {
+ dev_info(ctx->dev, "failed to create subdev nodes\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void seninf_notifier_unbind(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_connection *asc)
+{
+ struct seninf_ctx *ctx = notifier_to_ctx(notifier);
+
+ dev_info(ctx->dev, "%s is unbounded\n", sd->entity.name);
+}
+
+static const struct v4l2_async_notifier_operations seninf_async_ops = {
+ .bound = seninf_notifier_bound,
+ .unbind = seninf_notifier_unbind,
+};
+
+/* Update vcinfo once test_model switches */
+static int seninf_test_pattern(struct seninf_ctx *ctx, u32 pattern)
+{
+ switch (pattern) {
+ case 0:
+ if (ctx->streaming)
+ return -EBUSY;
+ ctx->is_test_model = 0;
+ mtk_cam_seninf_get_vcinfo(ctx);
+ dev_info(ctx->dev, "test pattern off\n");
+ break;
+ case 1: /* 1 RAW only */
+ case 2: /* 3 Stagger expo */
+ case 3: /* 1 RAW and 1 PD */
+ if (ctx->streaming)
+ return -EBUSY;
+ ctx->is_test_model = pattern;
+ mtk_cam_seninf_get_vcinfo_test(ctx);
+ dev_info(ctx->dev, "test pattern on\n");
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mtk_cam_seninf_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct seninf_ctx *ctx = ctrl_hdl_to_ctx(ctrl->handler);
+ int ret = -EINVAL;
+
+ switch (ctrl->id) {
+ case V4L2_CID_TEST_PATTERN:
+ ret = seninf_test_pattern(ctx, ctrl->val);
+ break;
+ default:
+ ret = 0;
+ dev_info(ctx->dev, "%s Unhandled id:0x%x, val:0x%x\n",
+ __func__, ctrl->id, ctrl->val);
+ break;
+ }
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops seninf_ctrl_ops = {
+ .s_ctrl = mtk_cam_seninf_set_ctrl,
+};
+
+static int seninf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+
+ mutex_lock(&ctx->mutex);
+ ctx->open_refcnt++;
+
+ if (ctx->open_refcnt == 1)
+ dev_info(ctx->dev, "%s open_refcnt %d\n",
+ __func__, ctx->open_refcnt);
+
+ mutex_unlock(&ctx->mutex);
+
+ return 0;
+}
+
+static int seninf_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+
+ mutex_lock(&ctx->mutex);
+ ctx->open_refcnt--;
+
+ if (!ctx->open_refcnt) {
+ dev_info(ctx->dev, "%s open_refcnt %d\n",
+ __func__, ctx->open_refcnt);
+ if (ctx->streaming)
+ seninf_s_stream(&ctx->subdev, 0);
+ }
+
+ mutex_unlock(&ctx->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_internal_ops seninf_internal_ops = {
+ .open = seninf_open,
+ .close = seninf_close,
+};
+
+static const char *const seninf_test_pattern_menu[] = {
+ "Disabled",
+ "generate_test_pattern",
+ "generate_test_pattern_stagger",
+ "generate_test_pattern_pd",
+};
+
+static int seninf_initialize_controls(struct seninf_ctx *ctx)
+{
+ struct v4l2_ctrl_handler *handler;
+ int ret;
+
+ handler = &ctx->ctrl_handler;
+ ret = v4l2_ctrl_handler_init(handler, 2);
+ if (ret)
+ return ret;
+ v4l2_ctrl_new_std_menu_items(handler, &seninf_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(seninf_test_pattern_menu) - 1,
+ 0, 0, seninf_test_pattern_menu);
+
+ if (handler->error) {
+ ret = handler->error;
+ dev_info(ctx->dev, "Failed to init controls(%d)\n", ret);
+ goto err_free_handler;
+ }
+
+ ctx->subdev.ctrl_handler = handler;
+ return 0;
+
+err_free_handler:
+ v4l2_ctrl_handler_free(handler);
+
+ return ret;
+}
+
+static int seninf_parse_endpoint(struct device *dev,
+ struct v4l2_fwnode_endpoint *vep,
+ struct sensor_async_subdev *s_asd)
+{
+ struct fwnode_handle *remote_hnd;
+
+ s_asd->port = vep->base.port;
+ s_asd->bus_type = vep->bus_type;
+ s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
+
+ dev_dbg(dev, "Got local node port:%d type:%d lanes:%d\n",
+ vep->base.port, vep->bus_type,
+ vep->bus.mipi_csi2.num_data_lanes);
+
+ /* check if sensor endpoint assign mipi lane nums */
+ remote_hnd = fwnode_graph_get_remote_endpoint(vep->base.local_fwnode);
+ if (remote_hnd) {
+ u32 remote_bus = 0, remote_lanes = 0;
+
+ fwnode_property_read_u32(remote_hnd, "bus-type", &remote_bus);
+ if (remote_bus == V4L2_FWNODE_BUS_TYPE_CSI2_DPHY)
+ s_asd->bus_type = V4L2_MBUS_CSI2_DPHY;
+ else if (remote_bus == V4L2_FWNODE_BUS_TYPE_CSI2_CPHY)
+ s_asd->bus_type = V4L2_MBUS_CSI2_CPHY;
+
+ remote_lanes =
+ fwnode_property_count_u32(remote_hnd, "data-lanes");
+ if (remote_lanes > 0 &&
+ remote_lanes <= vep->bus.mipi_csi2.num_data_lanes)
+ s_asd->lanes = remote_lanes;
+
+ fwnode_handle_put(remote_hnd);
+ dev_dbg(dev, "Got remote node lanes:%d\n", remote_lanes);
+ }
+
+ return 0;
+}
+
+static int seninf_parse_fwnode(struct device *dev,
+ struct v4l2_async_notifier *notifier)
+{
+ struct fwnode_handle *fwnode = NULL;
+ struct v4l2_fwnode_endpoint vep = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY, /* CDPHY only */
+ };
+ int ret = 0;
+
+ fwnode_graph_for_each_endpoint(dev_fwnode(dev), fwnode) {
+ struct sensor_async_subdev *s_asd;
+
+ ret = v4l2_fwnode_endpoint_parse(fwnode, &vep);
+ if (ret) {
+ dev_err(dev, "failed to parse v4l2 fwnode endpoint\n");
+ break;
+ }
+
+ if (vep.bus_type != V4L2_MBUS_CSI2_DPHY &&
+ vep.bus_type != V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Got unsupported endpoint:%d, bus:%d\n",
+ vep.base.port, vep.bus_type);
+ continue;
+ }
+
+ s_asd = v4l2_async_nf_add_fwnode_remote(notifier, fwnode,
+ struct sensor_async_subdev);
+ if (IS_ERR(s_asd)) {
+ ret = PTR_ERR(s_asd);
+ break;
+ }
+
+ ret = seninf_parse_endpoint(dev, &vep, s_asd);
+ if (ret < 0)
+ break;
+ }
+
+ if (fwnode)
+ fwnode_handle_put(fwnode);
+
+ return ret;
+}
+
+static int register_subdev(struct seninf_ctx *ctx)
+{
+ int i, ret;
+ struct v4l2_subdev *sd = &ctx->subdev;
+ struct device *dev = ctx->dev;
+ struct media_pad *pads = ctx->pads;
+ struct v4l2_async_notifier *notifier = &ctx->notifier;
+
+ v4l2_subdev_init(sd, &seninf_subdev_ops);
+ sd->internal_ops = &seninf_subdev_internal_ops;
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS;
+ sd->dev = dev;
+
+ if (strlen(dev->of_node->name) > 16)
+ snprintf(sd->name, sizeof(sd->name), "%s-%s",
+ dev_driver_string(dev), &dev->of_node->name[16]);
+ else
+ snprintf(sd->name, sizeof(sd->name), "%s-%s",
+ dev_driver_string(dev), csi_port_names[ctx->port]);
+
+ v4l2_set_subdevdata(sd, ctx);
+
+ sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
+ sd->entity.ops = &seninf_media_ops;
+ sd->internal_ops = &seninf_internal_ops;
+
+ pads[PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+ for (i = PAD_SRC_RAW0; i < PAD_MAXCNT; i++)
+ pads[i].flags = MEDIA_PAD_FL_SOURCE;
+
+ for (i = 0; i < PAD_MAXCNT; i++)
+ ctx->pad2cam[i] = 0xff;
+
+ ret = media_entity_pads_init(&sd->entity, PAD_MAXCNT, pads);
+ if (ret < 0) {
+ dev_info(dev, "failed to init pads\n");
+ return ret;
+ }
+
+ /* register seninf as mtk_cam async child */
+ ret = v4l2_async_register_subdev(sd);
+ if (ret < 0) {
+ dev_info(dev, "failed to register subdev\n");
+ return ret;
+ }
+
+ /* register seninf as sensor async parent */
+ v4l2_async_subdev_nf_init(notifier, sd);
+ ret = seninf_parse_fwnode(dev, notifier);
+ if (ret < 0)
+ dev_info(dev, "no endpoint\n");
+
+ notifier->ops = &seninf_async_ops;
+ ret = v4l2_async_nf_register(notifier);
+ if (ret < 0) {
+ dev_info(dev, "failed to register notifier\n");
+ goto err_unregister_subdev;
+ }
+
+ return 0;
+
+err_unregister_subdev:
+ v4l2_device_unregister_subdev(sd);
+ v4l2_async_nf_cleanup(notifier);
+
+ return ret;
+}
+
+static void unregister_subdev(struct seninf_ctx *ctx)
+{
+ struct v4l2_subdev *sd = &ctx->subdev;
+
+ v4l2_async_nf_unregister(&ctx->notifier);
+ v4l2_async_nf_cleanup(&ctx->notifier);
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+}
+
+static int seninf_probe(struct platform_device *pdev)
+{
+ int ret, port;
+ struct seninf_ctx *ctx;
+ struct device *dev = &pdev->dev;
+ struct seninf_core *core;
+
+ if (!dev->parent)
+ return -EPROBE_DEFER;
+
+ /* get mtk seninf_core */
+ core = dev_get_drvdata(dev->parent);
+ if (!core)
+ return -EPROBE_DEFER;
+
+ /* init seninf_csi ctx */
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, ctx);
+ ctx->dev = dev;
+ ctx->core = core;
+ list_add(&ctx->list, &core->list);
+ INIT_LIST_HEAD(&ctx->list_mux);
+ INIT_LIST_HEAD(&ctx->list_cam_mux);
+
+ ctx->open_refcnt = 0;
+ mutex_init(&ctx->mutex);
+
+ ret = get_csi_port(dev, &port);
+ if (ret) {
+ dev_info(dev, "get_csi_port ret %d\n", ret);
+ return ret;
+ }
+
+ mtk_cam_seninf_init_iomem(ctx, core->reg_if, core->reg_ana);
+ mtk_cam_seninf_init_port(ctx, port);
+ init_fmt(ctx);
+
+ /* platform properties */
+ ctx->cphy_settle_delay_dt = ctx->core->cphy_settle_delay_dt;
+ ctx->dphy_settle_delay_dt = ctx->core->dphy_settle_delay_dt;
+ ctx->settle_delay_ck = ctx->core->settle_delay_ck;
+ ctx->hs_trail_parameter = ctx->core->hs_trail_parameter;
+
+ of_property_read_u32(dev->of_node, "cphy_settle_delay_dt",
+ &ctx->cphy_settle_delay_dt);
+ of_property_read_u32(dev->of_node, "dphy_settle_delay_dt",
+ &ctx->dphy_settle_delay_dt);
+ of_property_read_u32(dev->of_node, "settle_delay_ck",
+ &ctx->settle_delay_ck);
+ of_property_read_u32(dev->of_node, "hs_trail_parameter",
+ &ctx->hs_trail_parameter);
+
+ dev_info(dev,
+ "seninf d_settlte/d_settle_ck/d_trail/c_settle= 0x%x/0x%x/0x%x/0x%x\n",
+ ctx->dphy_settle_delay_dt,
+ ctx->settle_delay_ck,
+ ctx->hs_trail_parameter,
+ ctx->cphy_settle_delay_dt);
+
+ ret = dev_read_csi_efuse(ctx);
+ if (ret < 0)
+ dev_info(dev, "Failed to read efuse data\n");
+
+ ret = seninf_initialize_controls(ctx);
+ if (ret) {
+ dev_info(dev, "Failed to initialize controls\n");
+ return ret;
+ }
+
+ /* bind seninf_csi to mtkcam */
+ ret = register_subdev(ctx);
+ if (ret < 0) {
+ dev_err(dev, "register_subdev failed\n");
+ goto err_free_handler;
+ }
+
+ pm_runtime_enable(dev);
+
+ dev_info(dev, "%s: port=%d\n", __func__, ctx->port);
+
+ dev_info(dev, "camsys | [%s] success\n", __func__);
+
+ return 0;
+
+err_free_handler:
+ v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+
+ return ret;
+}
+
+static int runtime_suspend(struct device *dev)
+{
+ int i;
+ struct seninf_ctx *ctx = dev_get_drvdata(dev);
+ struct seninf_core *core = ctx->core;
+
+ mutex_lock(&core->mutex);
+
+ core->refcnt--;
+ if (core->refcnt == 0) {
+ i = CLK_TOP_SENINF_END;
+ do {
+ i--;
+ if (ctx->core->clk[i])
+ clk_disable_unprepare(ctx->core->clk[i]);
+ } while (i);
+ seninf_core_pm_runtime_put(core);
+ }
+
+ mutex_unlock(&core->mutex);
+
+ return 0;
+}
+
+static int runtime_resume(struct device *dev)
+{
+ u32 i;
+ int ret;
+
+ struct seninf_ctx *ctx = dev_get_drvdata(dev);
+ struct seninf_core *core = ctx->core;
+
+ mutex_lock(&core->mutex);
+
+ core->refcnt++;
+
+ if (core->refcnt == 1) {
+ ret = seninf_core_pm_runtime_get_sync(core);
+ if (ret < 0) {
+ dev_info(dev, "seninf_core_pm_runtime_get_sync failed\n");
+ return ret;
+ }
+
+ for (i = 0; i < CLK_TOP_SENINF_END; i++) {
+ if (core->clk[i])
+ ret = clk_prepare_enable(core->clk[i]);
+ if (ret)
+ dev_dbg(dev, "%s: clk seninf%d is empty\n",
+ __func__, i);
+ }
+ mtk_cam_seninf_disable_all_mux(ctx);
+ mtk_cam_seninf_disable_all_cammux(ctx);
+ }
+
+ mutex_unlock(&core->mutex);
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm_ops = {
+ SET_RUNTIME_PM_OPS(runtime_suspend, runtime_resume, NULL)
+};
+
+static void seninf_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct seninf_ctx *ctx = dev_get_drvdata(dev);
+
+ if (ctx->streaming) {
+ mtk_cam_seninf_set_idle(ctx);
+ mtk_cam_seninf_release_mux(ctx);
+ }
+
+ pm_runtime_disable(ctx->dev);
+
+ unregister_subdev(ctx);
+
+ v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+
+ mutex_destroy(&ctx->mutex);
+
+ dev_dbg(dev, "camsys | start %s\n", __func__);
+}
+
+static const struct of_device_id seninf_of_match[] = {
+ { .compatible = "mediatek,seninf" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, seninf_of_match);
+
+static int seninf_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+ return 0;
+}
+
+static int seninf_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+
+struct platform_driver seninf_pdrv = {
+ .probe = seninf_probe,
+ .remove = seninf_remove,
+ .suspend = seninf_suspend,
+ .resume = seninf_resume,
+ .driver = {
+ .name = "seninf",
+ .of_match_table = seninf_of_match,
+ .pm = &pm_ops,
+ },
+};
+
+int mtk_cam_seninf_calc_pixelrate(struct device *dev, s64 width, s64 height,
+ s64 hblank, s64 vblank,
+ int fps_n, int fps_d,
+ s64 sensor_pixel_rate)
+{
+ int ret;
+ s64 p_pixel_rate = sensor_pixel_rate;
+
+ ret = calc_buffered_pixel_rate(dev, width, height, hblank, vblank,
+ fps_n, fps_d, &p_pixel_rate);
+ if (ret)
+ return sensor_pixel_rate;
+
+ return p_pixel_rate;
+}
+
+int mtk_cam_seninf_get_pixelrate(struct v4l2_subdev *sd, s64 *p_pixel_rate)
+{
+ int ret;
+ s64 pixel_rate = -1;
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+
+ if (!ctx->sensor_sd) {
+ dev_info(ctx->dev, "no sensor\n");
+ return -EFAULT;
+ }
+
+ ret = get_buffered_pixel_rate(ctx,
+ ctx->sensor_sd, ctx->sensor_pad_idx,
+ &pixel_rate);
+ if (ret)
+ get_pixel_rate(ctx, ctx->sensor_sd, &pixel_rate);
+
+ if (pixel_rate <= 0) {
+ dev_info(ctx->dev, "failed to get pixel_rate\n");
+ return -EINVAL;
+ }
+
+ *p_pixel_rate = pixel_rate;
+
+ return 0;
+}
+
+int mtk_cam_seninf_dump(struct v4l2_subdev *sd)
+{
+ int ret = 0;
+ struct seninf_ctx *ctx = sd_to_ctx(sd);
+
+ ret = pm_runtime_resume_and_get(ctx->dev);
+ if (ret < 0) {
+ dev_info(ctx->dev, "%s pm_runtime_resume_and_get ret %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ if (ctx->streaming) {
+ ret = mtk_cam_seninf_debug(sd_to_ctx(sd));
+ /* user may call sensor ESD_RESET_SUPPORT */
+ } else {
+ dev_info(ctx->dev, "%s should not dump during stream off\n",
+ __func__);
+ }
+
+ pm_runtime_put_sync(ctx->dev);
+ return ret;
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
new file mode 100644
index 000000000000..117ae208cf4b
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_DRV_H
+#define __MTK_CAM_SENINF_DRV_H
+
+#include "mtk_cam-seninf.h"
+
+extern struct platform_driver seninf_core_pdrv;
+extern struct platform_driver seninf_pdrv;
+
+int update_isp_clk(struct seninf_ctx *ctx);
+
+#endif /*__MTK_CAM_SENINF_DRV_H */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
new file mode 100644
index 000000000000..535112f318b7
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_HW_H__
+#define __MTK_CAM_SENINF_HW_H__
+
+enum SET_REG_KEYS {
+ REG_KEY_MIN = 0,
+ REG_KEY_SETTLE_CK = REG_KEY_MIN,
+ REG_KEY_SETTLE_DT,
+ REG_KEY_HS_TRAIL_EN,
+ REG_KEY_HS_TRAIL_PARAM,
+ REG_KEY_CSI_IRQ_STAT,
+ REG_KEY_CSI_RESYNC_CYCLE,
+ REG_KEY_MUX_IRQ_STAT,
+ REG_KEY_CAMMUX_IRQ_STAT,
+ REG_KEY_CAMMUX_VSYNC_IRQ_EN,
+ REG_KEY_CSI_IRQ_EN,
+ REG_KEY_MAX_NUM
+};
+
+#define SET_REG_KEYS_NAMES \
+ "RG_SETTLE_CK", \
+ "RG_SETTLE_DT", \
+ "RG_HS_TRAIL_EN", \
+ "RG_HS_TRAIL_PARAM", \
+ "RG_CSI_IRQ_STAT", \
+ "RG_CSI_RESYNC_CYCLE", \
+ "RG_MUX_IRQ_STAT", \
+ "RG_CAMMUX_IRQ_STAT", \
+ "REG_VSYNC_IRQ_EN", \
+ "RG_CSI_IRQ_EN", \
+
+struct mtk_cam_seninf_mux_meter {
+ u32 width;
+ u32 height;
+ u32 h_valid;
+ u32 h_blank;
+ u32 v_valid;
+ u32 v_blank;
+ s64 mipi_pixel_rate;
+ s64 vb_in_us;
+ s64 hb_in_us;
+ s64 line_time_in_us;
+};
+
+struct mtk_cam_seninf_cfg {
+ unsigned int seninf_num;
+ unsigned int mux_num;
+ unsigned int cam_mux_num;
+ unsigned int pref_mux_num;
+};
+
+extern struct mtk_cam_seninf_cfg *g_seninf_cfg;
+
+int mtk_cam_seninf_init_iomem(struct seninf_ctx *ctx, void __iomem *if_base,
+ void __iomem *ana_base);
+int mtk_cam_seninf_init_port(struct seninf_ctx *ctx, int port);
+int mtk_cam_seninf_is_cammux_used(struct seninf_ctx *ctx, int cam_mux);
+int mtk_cam_seninf_cammux(struct seninf_ctx *ctx, int cam_mux);
+int mtk_cam_seninf_disable_cammux(struct seninf_ctx *ctx, int cam_mux);
+int mtk_cam_seninf_disable_all_cammux(struct seninf_ctx *ctx);
+int mtk_cam_seninf_set_top_mux_ctrl(struct seninf_ctx *ctx, int mux_idx,
+ int seninf_src);
+int mtk_cam_seninf_get_top_mux_ctrl(struct seninf_ctx *ctx, int mux_idx);
+int mtk_cam_seninf_get_cammux_ctrl(struct seninf_ctx *ctx, int cam_mux);
+u32 mtk_cam_seninf_get_cammux_res(struct seninf_ctx *ctx, int cam_mux);
+int mtk_cam_seninf_set_cammux_vc(struct seninf_ctx *ctx, int cam_mux,
+ int vc_sel, int dt_sel, int vc_en,
+ int dt_en);
+int mtk_cam_seninf_set_cammux_src(struct seninf_ctx *ctx, int src,
+ int target, int exp_hsize, int exp_vsize);
+int mtk_cam_seninf_set_vc(struct seninf_ctx *ctx, u32 seninf_idx,
+ struct seninf_vcinfo *vcinfo);
+int mtk_cam_seninf_set_mux_ctrl(struct seninf_ctx *ctx, u32 mux, int hs_pol,
+ int vs_pol, int src_sel, int pixel_mode);
+int mtk_cam_seninf_set_mux_crop(struct seninf_ctx *ctx, u32 mux, int start_x,
+ int end_x, int enable);
+int mtk_cam_seninf_is_mux_used(struct seninf_ctx *ctx, u32 mux);
+int mtk_cam_seninf_mux(struct seninf_ctx *ctx, u32 mux);
+int mtk_cam_seninf_disable_mux(struct seninf_ctx *ctx, u32 mux);
+int mtk_cam_seninf_disable_all_mux(struct seninf_ctx *ctx);
+int mtk_cam_seninf_set_cammux_chk_pixel_mode(struct seninf_ctx *ctx,
+ int cam_mux, int pixel_mode);
+int mtk_cam_seninf_set_test_model(struct seninf_ctx *ctx, int mux, int cam_mux,
+ int pixel_mode);
+int mtk_cam_seninf_set_csi_mipi(struct seninf_ctx *ctx);
+int mtk_cam_seninf_poweroff(struct seninf_ctx *ctx);
+int mtk_cam_seninf_reset(struct seninf_ctx *ctx, u32 seninf_idx);
+int mtk_cam_seninf_set_idle(struct seninf_ctx *ctx);
+int mtk_cam_seninf_get_mux_meter(struct seninf_ctx *ctx, u32 mux,
+ struct mtk_cam_seninf_mux_meter *meter);
+ssize_t mtk_cam_seninf_show_status(struct device *dev,
+ struct device_attribute *attr, char *buf);
+int mtk_cam_seninf_switch_to_cammux_inner_page(struct seninf_ctx *ctx,
+ bool inner);
+int mtk_cam_seninf_set_cammux_next_ctrl(struct seninf_ctx *ctx, int src,
+ int target);
+int mtk_cam_seninf_update_mux_pixel_mode(struct seninf_ctx *ctx, u32 mux,
+ int pixel_mode);
+int mtk_cam_seninf_irq_handler(int irq, void *data);
+int mtk_cam_seninf_set_sw_cfg_busy(struct seninf_ctx *ctx, bool enable,
+ int index);
+int mtk_cam_seninf_set_cam_mux_dyn_en(struct seninf_ctx *ctx, bool enable,
+ int cam_mux, int index);
+int mtk_cam_seninf_reset_cam_mux_dyn_en(struct seninf_ctx *ctx, int index);
+int mtk_cam_seninf_enable_global_drop_irq(struct seninf_ctx *ctx, bool enable,
+ int index);
+int mtk_cam_seninf_enable_cam_mux_vsync_irq(struct seninf_ctx *ctx, bool enable,
+ int cam_mux);
+int mtk_cam_seninf_disable_all_cam_mux_vsync_irq(struct seninf_ctx *ctx);
+int mtk_cam_seninf_debug(struct seninf_ctx *ctx);
+int mtk_cam_seninf_set_reg(struct seninf_ctx *ctx, u32 key, u32 val);
+ssize_t mtk_cam_seninf_show_err_status(struct device *dev,
+ struct device_attribute *attr,
+ char *buf);
+
+#endif /* __MTK_CAM_SENINF_HW_H__ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
new file mode 100644
index 000000000000..2960ea0afd8d
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_IF_H__
+#define __MTK_CAM_SENINF_IF_H__
+
+int mtk_cam_seninf_get_pixelmode(struct v4l2_subdev *sd, int pad_id,
+ int *pixelmode);
+
+int mtk_cam_seninf_set_pixelmode(struct v4l2_subdev *sd, int pad_id,
+ int pixelmode);
+
+int mtk_cam_seninf_set_camtg(struct v4l2_subdev *sd, int pad_id, int camtg);
+
+int mtk_cam_seninf_get_pixelrate(struct v4l2_subdev *sd, s64 *pixelrate);
+
+int mtk_cam_seninf_calc_pixelrate(struct device *dev, s64 width, s64 height,
+ s64 hblank, s64 vblank, int fps_n, int fps_d,
+ s64 sensor_pixel_rate);
+
+int mtk_cam_seninf_dump(struct v4l2_subdev *sd);
+
+unsigned int mtk_cam_seninf_get_vc_feature(struct v4l2_subdev *sd,
+ unsigned int pad);
+
+#endif /* __MTK_CAM_SENINF_IF_H__ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
new file mode 100644
index 000000000000..65f3ec058fba
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_REGS_H__
+#define __MTK_CAM_SENINF_REGS_H__
+
+#define SENINF_BITS(base, reg, field, val) \
+ do { \
+ u32 __iomem *__p = (base) + (reg); \
+ u32 __v = readl(__p); \
+ __v &= ~field##_MASK; \
+ __v |= (((val) << field##_SHIFT) & field##_MASK); \
+ writel(__v, __p); \
+ } while (0)
+
+#define SENINF_READ_BITS(base, reg, field) \
+ ({ \
+ u32 __iomem *__p = (base) + (reg); \
+ u32 __v = readl(__p); \
+ __v &= field##_MASK; \
+ __v >>= field##_SHIFT; \
+ __v; \
+ })
+
+#define SENINF_READ_REG(base, reg) \
+ ({ \
+ u32 __iomem *__p = (base) + (reg); \
+ u32 __v = readl(__p); \
+ __v; \
+ })
+
+#define SENINF_WRITE_REG(base, reg, val) \
+ do { \
+ u32 __iomem *__p = (base) + (reg); \
+ writel(val, __p); \
+ } while (0)
+
+#endif /* __MTK_CAM_SENINF_REGS_H__ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
new file mode 100644
index 000000000000..cda62fb7fb84
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2022 MediaTek Inc.
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/of_graph.h>
+#include <linux/of_device.h>
+
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-device.h>
+
+#include "mtk_cam-seninf.h"
+#include "mtk_cam-seninf-route.h"
+#include "mtk_cam-seninf-if.h"
+#include "mtk_cam-seninf-hw.h"
+#include "mtk_cam-seninf-drv.h"
+#include "kd_imgsensor_define_v4l2.h"
+
+#define to_std_fmt_code(code) \
+ ((code) & 0xFFFF)
+
+void mtk_cam_seninf_init_res(struct seninf_core *core)
+{
+ int i;
+
+ INIT_LIST_HEAD(&core->list_mux);
+ for (i = 0; i < g_seninf_cfg->mux_num; i++) {
+ core->mux[i].idx = i;
+ list_add_tail(&core->mux[i].list, &core->list_mux);
+ }
+}
+
+struct seninf_mux *mtk_cam_seninf_mux_get(struct seninf_ctx *ctx)
+{
+ struct seninf_core *core = ctx->core;
+ struct seninf_mux *ent = NULL;
+
+ mutex_lock(&core->mutex);
+
+ if (!list_empty(&core->list_mux)) {
+ ent = list_first_entry(&core->list_mux,
+ struct seninf_mux, list);
+ list_move_tail(&ent->list, &ctx->list_mux);
+ }
+
+ mutex_unlock(&core->mutex);
+
+ return ent;
+}
+
+struct seninf_mux *mtk_cam_seninf_mux_get_pref(struct seninf_ctx *ctx,
+ int *pref_idx, int pref_cnt)
+{
+ int i;
+ struct seninf_core *core = ctx->core;
+ struct seninf_mux *ent = NULL;
+
+ mutex_lock(&core->mutex);
+
+ list_for_each_entry(ent, &core->list_mux, list) {
+ for (i = 0; i < pref_cnt; i++) {
+ if (ent->idx == pref_idx[i]) {
+ list_move_tail(&ent->list, &ctx->list_mux);
+ mutex_unlock(&core->mutex);
+ return ent;
+ }
+ }
+ }
+
+ mutex_unlock(&core->mutex);
+
+ return mtk_cam_seninf_mux_get(ctx);
+}
+
+void mtk_cam_seninf_mux_put(struct seninf_ctx *ctx, struct seninf_mux *mux)
+{
+ struct seninf_core *core = ctx->core;
+
+ mutex_lock(&core->mutex);
+ list_move_tail(&mux->list, &core->list_mux);
+ mutex_unlock(&core->mutex);
+}
+
+void mtk_cam_seninf_get_vcinfo_test(struct seninf_ctx *ctx)
+{
+ struct seninf_vcinfo *vcinfo = &ctx->vcinfo;
+ struct seninf_vc *vc;
+
+ vcinfo->cnt = 0;
+
+ if (ctx->is_test_model == 1) {
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_RAW_DATA;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+ } else if (ctx->is_test_model == 2) {
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_STAGGER_NE;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_STAGGER_ME;
+ vc->out_pad = PAD_SRC_RAW1;
+ vc->group = 0;
+
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_STAGGER_SE;
+ vc->out_pad = PAD_SRC_RAW2;
+ vc->group = 0;
+ } else if (ctx->is_test_model == 3) {
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_RAW_DATA;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x30;
+ vc->feature = VC_PDAF_STATS;
+ vc->out_pad = PAD_SRC_PDAF0;
+ vc->group = 0;
+ }
+}
+
+struct seninf_vc *mtk_cam_seninf_get_vc_by_pad(struct seninf_ctx *ctx, int idx)
+{
+ int i;
+ struct seninf_vcinfo *vcinfo = &ctx->vcinfo;
+
+ for (i = 0; i < vcinfo->cnt; i++) {
+ if (vcinfo->vc[i].out_pad == idx)
+ return &vcinfo->vc[i];
+ }
+
+ return NULL;
+}
+
+unsigned int mtk_cam_seninf_get_vc_feature(struct v4l2_subdev *sd,
+ unsigned int pad)
+{
+ struct seninf_vc *pvc = NULL;
+ struct seninf_ctx *ctx = container_of(sd, struct seninf_ctx, subdev);
+
+ pvc = mtk_cam_seninf_get_vc_by_pad(ctx, pad);
+ if (pvc)
+ return pvc->feature;
+
+ return VC_NONE;
+}
+
+int mtk_cam_seninf_get_vcinfo(struct seninf_ctx *ctx)
+{
+ struct seninf_vcinfo *vcinfo = &ctx->vcinfo;
+ struct seninf_vc *vc;
+
+ if (!ctx->sensor_sd)
+ return -EINVAL;
+
+ vcinfo->cnt = 0;
+
+ switch (to_std_fmt_code(ctx->fmt[PAD_SINK].format.code)) {
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2a;
+ vc->feature = VC_RAW_DATA;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+ break;
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2b;
+ vc->feature = VC_RAW_DATA;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+ break;
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ vc = &vcinfo->vc[vcinfo->cnt++];
+ vc->vc = 0;
+ vc->dt = 0x2c;
+ vc->feature = VC_RAW_DATA;
+ vc->out_pad = PAD_SRC_RAW0;
+ vc->group = 0;
+ break;
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+void mtk_cam_seninf_release_mux(struct seninf_ctx *ctx)
+{
+ struct seninf_mux *ent, *tmp;
+
+ list_for_each_entry_safe(ent, tmp, &ctx->list_mux, list) {
+ mtk_cam_seninf_mux_put(ctx, ent);
+ }
+}
+
+int mtk_cam_seninf_is_di_enabled(struct seninf_ctx *ctx, u8 ch, u8 dt)
+{
+ int i;
+ struct seninf_vc *vc;
+
+ for (i = 0; i < ctx->vcinfo.cnt; i++) {
+ vc = &ctx->vcinfo.vc[i];
+ if (vc->vc == ch && vc->dt == dt) {
+ if (media_pad_remote_pad_first(&ctx->pads[vc->out_pad]))
+ return 1;
+
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
+int mtk_cam_seninf_get_pixelmode(struct v4l2_subdev *sd,
+ int pad_id, int *pixel_mode)
+{
+ struct seninf_ctx *ctx = container_of(sd, struct seninf_ctx, subdev);
+ struct seninf_vc *vc;
+
+ vc = mtk_cam_seninf_get_vc_by_pad(ctx, pad_id);
+ if (!vc) {
+ pr_info("%s: invalid pad=%d\n", __func__, pad_id);
+ return -1;
+ }
+
+ *pixel_mode = vc->pixel_mode;
+
+ return 0;
+}
+
+int mtk_cam_seninf_set_pixelmode(struct v4l2_subdev *sd,
+ int pad_id, int pixel_mode)
+{
+ struct seninf_ctx *ctx = container_of(sd, struct seninf_ctx, subdev);
+ struct seninf_vc *vc;
+
+ vc = mtk_cam_seninf_get_vc_by_pad(ctx, pad_id);
+ if (!vc) {
+ pr_info("%s: invalid pad=%d\n", __func__, pad_id);
+ return -1;
+ }
+
+ vc->pixel_mode = pixel_mode;
+ if (ctx->streaming) {
+ update_isp_clk(ctx);
+ mtk_cam_seninf_update_mux_pixel_mode(ctx, vc->mux, pixel_mode);
+ }
+
+ return 0;
+}
+
+static int _mtk_cam_seninf_set_camtg(struct v4l2_subdev *sd,
+ int pad_id, int camtg, bool disable_last)
+{
+ int old_camtg;
+ struct seninf_ctx *ctx = container_of(sd, struct seninf_ctx, subdev);
+ struct seninf_vc *vc;
+
+ if (pad_id < PAD_SRC_RAW0 || pad_id >= PAD_MAXCNT)
+ return -EINVAL;
+
+ vc = mtk_cam_seninf_get_vc_by_pad(ctx, pad_id);
+ if (!vc)
+ return -EINVAL;
+
+ ctx->pad2cam[pad_id] = camtg;
+
+ /* change cam-mux while streaming */
+ if (ctx->streaming && vc->cam != camtg) {
+ if (camtg == 0xff) {
+ old_camtg = vc->cam;
+ vc->cam = 0xff;
+ mtk_cam_seninf_switch_to_cammux_inner_page(ctx, true);
+ mtk_cam_seninf_set_cammux_next_ctrl(ctx, 0x1f, old_camtg);
+ mtk_cam_seninf_disable_cammux(ctx, old_camtg);
+ } else {
+ /* disable old */
+ old_camtg = vc->cam;
+ /* enable new */
+ vc->cam = camtg;
+ mtk_cam_seninf_switch_to_cammux_inner_page(ctx, true);
+ mtk_cam_seninf_set_cammux_next_ctrl(ctx, 0x1f, vc->cam);
+
+ mtk_cam_seninf_switch_to_cammux_inner_page(ctx, false);
+
+ mtk_cam_seninf_set_cammux_vc(ctx, vc->cam,
+ vc->vc, vc->dt,
+ !!vc->dt, !!vc->dt);
+ mtk_cam_seninf_set_cammux_src(ctx, vc->mux, vc->cam,
+ vc->exp_hsize,
+ vc->exp_vsize);
+ mtk_cam_seninf_set_cammux_chk_pixel_mode(ctx,
+ vc->cam,
+ vc->pixel_mode);
+ if (old_camtg != 0xff && disable_last) {
+ /* disable old in next sof */
+ mtk_cam_seninf_disable_cammux(ctx, old_camtg);
+ }
+ mtk_cam_seninf_cammux(ctx, vc->cam); /* enable in next sof */
+ mtk_cam_seninf_switch_to_cammux_inner_page(ctx, true);
+ mtk_cam_seninf_set_cammux_next_ctrl(ctx, vc->mux, vc->cam);
+ if (old_camtg != 0xff && disable_last)
+ mtk_cam_seninf_set_cammux_next_ctrl(ctx,
+ vc->mux,
+ old_camtg);
+
+ /* user control sensor fsync after change cam-mux */
+ }
+
+ dev_info(ctx->dev, "%s: pad %d mux %d cam %d -> %d\n",
+ __func__, vc->out_pad, vc->mux, old_camtg, vc->cam);
+ } else {
+ dev_info(ctx->dev, "%s: pad_id %d, camtg %d, ctx->streaming %d, vc->cam %d\n",
+ __func__, pad_id, camtg, ctx->streaming, vc->cam);
+ }
+
+ return 0;
+}
+
+int mtk_cam_seninf_set_camtg(struct v4l2_subdev *sd, int pad_id, int camtg)
+{
+ return _mtk_cam_seninf_set_camtg(sd, pad_id, camtg, true);
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
new file mode 100644
index 000000000000..99f6c6e7818d
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_ROUTE_H__
+#define __MTK_CAM_SENINF_ROUTE_H__
+
+#define MAX_MUX_CHANNEL 4
+
+void mtk_cam_seninf_init_res(struct seninf_core *core);
+
+struct seninf_mux *mtk_cam_seninf_mux_get(struct seninf_ctx *ctx);
+struct seninf_mux *mtk_cam_seninf_mux_get_pref(struct seninf_ctx *ctx,
+ int *pref_idx, int pref_cnt);
+void mtk_cam_seninf_mux_put(struct seninf_ctx *ctx, struct seninf_mux *mux);
+void mtk_cam_seninf_release_mux(struct seninf_ctx *ctx);
+void mtk_cam_seninf_get_vcinfo_test(struct seninf_ctx *ctx);
+struct seninf_vc *mtk_cam_seninf_get_vc_by_pad(struct seninf_ctx *ctx, int idx);
+int mtk_cam_seninf_get_vcinfo(struct seninf_ctx *ctx);
+int mtk_cam_seninf_is_di_enabled(struct seninf_ctx *ctx, u8 ch, u8 dt);
+
+#endif /* __MTK_CAM_SENINF_ROUTE_H__ */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
new file mode 100644
index 000000000000..6984e6d1b3ff
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_SENINF_H__
+#define __MTK_CAM_SENINF_H__
+
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fwnode.h>
+
+#include "mtk_cam-seninf-def.h"
+#include "kd_imgsensor_define_v4l2.h"
+#include "mtk_cam-seninf-regs.h"
+
+struct seninf_mux {
+ struct list_head list;
+ int idx;
+};
+
+struct seninf_cam_mux {
+ struct list_head list;
+ int idx;
+};
+
+struct seninf_vc {
+ u8 vc;
+ u8 dt;
+ u8 feature;
+ u8 out_pad;
+ u8 pixel_mode;
+ u8 group;
+ u8 mux; /* allocated per group */
+ u8 cam; /* assigned by cam driver */
+ u8 enable;
+ u16 exp_hsize;
+ u16 exp_vsize;
+};
+
+struct seninf_vcinfo {
+ struct seninf_vc vc[SENINF_VC_MAXCNT];
+ int cnt;
+};
+
+struct seninf_dfs {
+ struct device *dev;
+ struct regulator *reg;
+ unsigned long *freqs;
+ unsigned long *volts;
+ int cnt;
+};
+
+struct seninf_core {
+ struct device *dev;
+ int pm_domain_cnt;
+ struct device **pm_domain_devs;
+ struct clk *clk[CLK_MAXCNT];
+ struct seninf_dfs dfs;
+ struct list_head list;
+ struct list_head list_mux; /* available mux */
+ struct seninf_mux mux[SENINF_MUX_NUM];
+ struct mutex mutex; /* protect seninf core operations */
+ void __iomem *reg_if;
+ void __iomem *reg_ana;
+ int refcnt;
+
+ /* platform properties */
+ int cphy_settle_delay_dt;
+ int dphy_settle_delay_dt;
+ int settle_delay_ck;
+ int hs_trail_parameter;
+
+ /* protect variables in irq handler */
+ spinlock_t spinlock_irq;
+
+ /* mipi error detection count */
+ unsigned int detection_cnt;
+ /* enable csi irq flag */
+ unsigned int csi_irq_en_flag;
+};
+
+struct seninf_ctx {
+ struct v4l2_subdev subdev;
+ struct v4l2_async_notifier notifier;
+ struct device *dev;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct media_pad pads[PAD_MAXCNT];
+ struct v4l2_subdev_format fmt[PAD_MAXCNT];
+ struct seninf_core *core;
+ struct list_head list;
+
+ u32 port;
+ u32 port_a;
+ u32 port_b;
+ u32 port_num;
+ u32 num_data_lanes;
+ s64 mipi_pixel_rate;
+ s64 buffered_pixel_rate;
+ s64 customized_pixel_rate;
+ unsigned int m_csi_efuse;
+
+ unsigned int is_4d1c:1;
+ unsigned int is_cphy:1;
+ unsigned int is_test_model:4;
+ unsigned int is_secure:1;
+ unsigned int sec_info_addr;
+ u32 seninf_idx;
+ int pad2cam[PAD_MAXCNT];
+
+ /* remote sensor */
+ struct v4l2_subdev *sensor_sd;
+ u32 sensor_pad_idx;
+
+ /* provided by sensor */
+ struct seninf_vcinfo vcinfo;
+ int fps_n;
+ int fps_d;
+
+ /* dfs */
+ int isp_freq;
+
+ void __iomem *reg_ana_csi_rx[CSI_PORT_MAX_NUM];
+ void __iomem *reg_ana_dphy_top[CSI_PORT_MAX_NUM];
+ void __iomem *reg_ana_cphy_top[CSI_PORT_MAX_NUM];
+ void __iomem *reg_if_top;
+ void __iomem *reg_if_ctrl[SENINF_NUM];
+ void __iomem *reg_if_cam_mux;
+ void __iomem *reg_if_cam_mux_gcsr;
+ void __iomem *reg_if_cam_mux_pcsr[SENINF_CAM_MUX_NUM];
+ void __iomem *reg_if_tg[SENINF_NUM];
+ void __iomem *reg_if_csi2[SENINF_NUM];
+ void __iomem *reg_if_mux[SENINF_MUX_NUM];
+
+ /* resources */
+ struct list_head list_mux; /* work mux */
+ struct list_head list_cam_mux;
+
+ /* flags */
+ unsigned int streaming:1;
+
+ int cphy_settle_delay_dt;
+ int dphy_settle_delay_dt;
+ int settle_delay_ck;
+ int hs_trail_parameter;
+
+ int open_refcnt;
+ struct mutex mutex; /* protect seninf context */
+
+ /* csi irq */
+ unsigned int data_not_enough_cnt;
+ unsigned int err_lane_resync_cnt;
+ unsigned int crc_err_cnt;
+ unsigned int ecc_err_double_cnt;
+ unsigned int ecc_err_corrected_cnt;
+ /* seninf_mux fifo overrun irq */
+ unsigned int fifo_overrun_cnt;
+ /* cam_mux h/v size irq */
+ unsigned int size_err_cnt;
+ /* error flag */
+ unsigned int data_not_enough_flag;
+ unsigned int err_lane_resync_flag;
+ unsigned int crc_err_flag;
+ unsigned int ecc_err_double_flag;
+ unsigned int ecc_err_corrected_flag;
+ unsigned int fifo_overrun_flag;
+ unsigned int size_err_flag;
+};
+
+#endif /* __MTK_CAM_SENINF_H__ */
--
2.18.0
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
@ 2024-10-09 11:15 ` Shu-hsiang Yang
2024-11-04 3:24 ` CK Hu (胡俊光)
2024-11-20 1:05 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config Shu-hsiang Yang
` (8 subsequent siblings)
11 siblings, 2 replies; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
Introduces the V4L2 video interface and feature management for the
MediaTek ISP7x CAMSYS. These interfaces include various functionalities,
such as video operation initialization and registration. They also
manage MediaTek-specific formats and handle buffers for MediaTek camera
video devices. This integrates CAMSYS functionalities to be compatible
with the V4L2 framework.
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
.../isp/isp_7x/camsys/mtk_cam-feature.c | 40 +
.../isp/isp_7x/camsys/mtk_cam-feature.h | 26 +
.../isp/isp_7x/camsys/mtk_cam-video.c | 1817 +++++++++++++++++
.../isp/isp_7x/camsys/mtk_cam-video.h | 224 ++
4 files changed, 2107 insertions(+)
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
new file mode 100644
index 000000000000..639c1e1671fc
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2022 MediaTek Inc.
+
+#include "mtk_cam-feature.h"
+
+struct mtk_cam_ctx;
+
+/*
+ * mtk_cam_is_[feature] is used for raw_feature,
+ * which must not change during streaming.
+ */
+
+static bool mtk_cam_is_no_seninf(struct mtk_cam_ctx *ctx)
+{
+ return !media_pad_remote_pad_first(&ctx->pipe->pads[MTK_RAW_SINK]);
+}
+
+bool mtk_cam_is_pure_m2m(struct mtk_cam_ctx *ctx)
+{
+ if (!ctx->used_raw_num)
+ return false;
+
+ if (ctx->pipe->feature_pending & MTK_CAM_FEATURE_PURE_OFFLINE_M2M_MASK ||
+ mtk_cam_is_no_seninf(ctx))
+ return true;
+ else
+ return false;
+}
+
+bool mtk_cam_is_m2m(struct mtk_cam_ctx *ctx)
+{
+ if (!ctx->used_raw_num)
+ return false;
+
+ if (mtk_cam_is_no_seninf(ctx))
+ return true;
+ else
+ return mtk_cam_feature_is_m2m(ctx->pipe->feature_pending);
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
new file mode 100644
index 000000000000..dd5acc754765
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_FEATURE_H
+#define __MTK_CAM_FEATURE_H
+
+#include "mtk_cam.h"
+#include "mtk_cam-raw.h"
+
+static inline bool mtk_cam_feature_is_m2m(int feature)
+{
+ return !!(feature & MTK_CAM_FEATURE_OFFLINE_M2M_MASK) ||
+ !!(feature & MTK_CAM_FEATURE_PURE_OFFLINE_M2M_MASK);
+}
+
+static inline bool mtk_cam_feature_is_pure_m2m(int feature)
+{
+ return !!(feature & MTK_CAM_FEATURE_PURE_OFFLINE_M2M_MASK);
+}
+
+bool mtk_cam_is_m2m(struct mtk_cam_ctx *ctx);
+bool mtk_cam_is_pure_m2m(struct mtk_cam_ctx *ctx);
+
+#endif /*__MTK_CAM_FEATURE_H */
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
new file mode 100644
index 000000000000..95cdf1a2fb4c
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
@@ -0,0 +1,1817 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2022 MediaTek Inc.
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+#include <linux/videodev2.h>
+#include <linux/iommu.h>
+
+#include "mtk_cam.h"
+#include "mtk_cam-feature.h"
+#include "mtk_cam-video.h"
+#include "mtk_camera-v4l2-controls.h"
+#include "mtk_cam-ufbc-def.h"
+
+/*
+ * differt dma (fmt) would have different bus_size
+ * align xsize(bytes per line) with [bus_size * pixel_mode]
+ */
+static inline int mtk_cam_is_fullg(unsigned int ipi_fmt)
+{
+ return (ipi_fmt == MTKCAM_IPI_IMG_FMT_FG_BAYER8) ||
+ (ipi_fmt == MTKCAM_IPI_IMG_FMT_FG_BAYER10) ||
+ (ipi_fmt == MTKCAM_IPI_IMG_FMT_FG_BAYER12);
+}
+
+static inline
+unsigned int mtk_cam_dma_bus_size(int bpp, int pixel_mode_shift, int is_fg)
+{
+ unsigned int bus_size = ALIGN(bpp, 16) << pixel_mode_shift;
+
+ if (is_fg)
+ bus_size <<= 1;
+ return bus_size / 8; /* in bytes */
+}
+
+static inline
+unsigned int mtk_cam_yuv_dma_bus_size(int bpp, int pixel_mode_shift)
+{
+ unsigned int bus_size = ALIGN(bpp, 32) << pixel_mode_shift;
+
+ return bus_size / 8; /* in bytes */
+}
+
+static inline
+unsigned int mtk_cam_dmao_xsize(int w, unsigned int ipi_fmt, int pixel_mode_shift)
+{
+ const unsigned int is_fg = mtk_cam_is_fullg(ipi_fmt);
+ const unsigned int bpp = mtk_cam_get_pixel_bits(ipi_fmt);
+ const unsigned int bytes = is_fg ?
+ DIV_ROUND_UP(w * bpp * 3 / 2, 8) : DIV_ROUND_UP(w * bpp, 8);
+ const unsigned int bus_size =
+ mtk_cam_dma_bus_size(bpp, pixel_mode_shift, is_fg);
+
+ return ALIGN(bytes, bus_size);
+}
+
+static void mtk_cam_release_all_buffer(struct mtk_cam_device *cam)
+{
+ struct mtk_cam_buffer *buf, *tmp;
+
+ spin_lock(&cam->dma_pending_lock);
+ list_for_each_entry_safe(buf, tmp, &cam->dma_pending, list) {
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vbb.vb2_buf, VB2_BUF_STATE_ERROR);
+ }
+ spin_unlock(&cam->dma_pending_lock);
+
+ spin_lock(&cam->dma_processing_lock);
+ list_for_each_entry_safe(buf, tmp, &cam->dma_processing, list) {
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vbb.vb2_buf, VB2_BUF_STATE_ERROR);
+ }
+ spin_unlock(&cam->dma_processing_lock);
+}
+
+static int mtk_cam_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vq);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ struct mtk_raw_pipeline *raw_pipeline;
+ unsigned int max_buffer_count = node->desc.max_buf_count;
+ const struct v4l2_format *fmt = &node->active_fmt;
+ unsigned int size;
+ int i;
+
+ /* Check the limitation of buffer size */
+ if (max_buffer_count)
+ *num_buffers = clamp_val(*num_buffers, 1, max_buffer_count);
+
+ if (node->desc.smem_alloc)
+ vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
+
+ if (vq->type == V4L2_BUF_TYPE_META_OUTPUT ||
+ vq->type == V4L2_BUF_TYPE_META_CAPTURE)
+ size = fmt->fmt.meta.buffersize;
+ else
+ size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
+
+ /* Add for q.create_bufs with fmt.g_sizeimage(p) / 2 test */
+ if (*num_planes) {
+ if (sizes[0] < size || *num_planes != 1)
+ return -EINVAL;
+ } else {
+ /* Set default as one plane */
+ *num_planes = 1;
+ sizes[0] = size;
+
+ if (is_raw_subdev(node->uid.pipe_id)) {
+ raw_pipeline =
+ mtk_cam_dev_get_raw_pipeline(cam, node->uid.pipe_id);
+
+ if (raw_pipeline &&
+ raw_pipeline->user_res.raw_res.feature &&
+ fmt->fmt.pix_mp.num_planes > 1) {
+ *num_planes = fmt->fmt.pix_mp.num_planes;
+ for (i = 0; i < *num_planes; i++)
+ sizes[i] = size;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int mtk_cam_vb2_buf_init(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_cam_buffer *buf;
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct device *dev = cam->raw.devs[0];
+ dma_addr_t addr;
+
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ buf->daddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+ buf->scp_addr = 0;
+
+ /* SCP address is only valid for meta input buffer */
+ if (!node->desc.smem_alloc)
+ return 0;
+
+ /* Use coherent address to get iova address */
+ addr = dma_map_resource(dev, buf->daddr, vb->planes[0].length,
+ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
+ if (dma_mapping_error(dev, addr)) {
+ dev_err(dev, "failed to map addr:%pad\n", &buf->daddr);
+ return -EFAULT;
+ }
+ buf->scp_addr = buf->daddr;
+ buf->daddr = addr;
+
+ return 0;
+}
+
+static int mtk_cam_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb);
+ const struct v4l2_format *fmt = &node->active_fmt;
+ unsigned int size;
+
+ dev_dbg(vb->vb2_queue->dev, "%s: %s\n", __func__, node->desc.name);
+
+ if (vb->vb2_queue->type == V4L2_BUF_TYPE_META_OUTPUT ||
+ vb->vb2_queue->type == V4L2_BUF_TYPE_META_CAPTURE)
+ size = fmt->fmt.meta.buffersize;
+ else
+ size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
+
+ if (vb2_plane_size(vb, 0) < size) {
+ dev_info(vb->vb2_queue->dev,
+ "plane size is too small:%lu<%u\n",
+ vb2_plane_size(vb, 0), size);
+ }
+
+ if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
+ if ((vb2_get_plane_payload(vb, 0) != size) &&
+ vb->vb2_queue->streaming) {
+ dev_dbg(vb->vb2_queue->dev,
+ "plane payload is mismatch:%lu:%u\n",
+ vb2_get_plane_payload(vb, 0), size);
+ }
+ return 0;
+ }
+
+ v4l2_buf->field = V4L2_FIELD_NONE;
+ vb2_set_plane_payload(vb, 0, size);
+
+ return 0;
+}
+
+static int mtk_cam_vb2_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vq);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ struct media_entity *entity = &node->vdev.entity;
+ struct mtk_cam_ctx *ctx = NULL;
+ struct device *dev = cam->dev;
+ int ret;
+
+ /* check entity is linked */
+ if (!node->enabled) {
+ dev_info(cam->dev,
+ "%s: stream on failed, node is not enabled\n",
+ node->desc.name);
+ ret = -ENOLINK;
+ goto fail_return_buffer;
+ }
+
+ if (!media_entity_is_streaming(entity)) {
+ ctx = mtk_cam_start_ctx(cam, node);
+ if (!ctx) {
+ ret = -ENOLINK;
+ goto fail_return_buffer;
+ }
+ } else {
+ ctx = mtk_cam_find_ctx(cam, entity);
+ if (WARN_ON(!ctx)) {
+ ret = -ENOLINK;
+ goto fail_return_buffer;
+ }
+ }
+
+ cam->streaming_pipe |= (1 << node->uid.pipe_id);
+ ctx->streaming_pipe |= (1 << node->uid.pipe_id);
+ ctx->streaming_node_cnt++;
+
+ if (ctx->streaming_node_cnt == 1)
+ if (is_raw_subdev(node->uid.pipe_id)) {
+ if (!isp_composer_create_session(ctx)) {
+ ctx->session_created = 1;
+ } else {
+ complete(&ctx->session_complete);
+ ret = -EBUSY;
+ goto fail_stop_ctx;
+ }
+ }
+
+ dev_dbg(dev, "%s:%s:ctx(%d): node:%d count info:%d\n", __func__,
+ node->desc.name, ctx->stream_id, node->desc.id,
+ ctx->streaming_node_cnt);
+
+ ret = mtk_cam_ctx_stream_on(ctx, node);
+ if (ret)
+ goto fail_destroy_session;
+
+ mtk_cam_buf_try_queue(ctx);
+
+ return 0;
+
+fail_destroy_session:
+ if (ctx->session_created)
+ isp_composer_destroy_session(ctx);
+fail_stop_ctx:
+ ctx->streaming_node_cnt--;
+ ctx->streaming_pipe &= ~(1 << node->uid.pipe_id);
+ cam->streaming_pipe &= ~(1 << node->uid.pipe_id);
+ mtk_cam_dev_req_cleanup(ctx, node->uid.pipe_id, VB2_BUF_STATE_QUEUED);
+ mtk_cam_stop_ctx(ctx, node);
+fail_return_buffer:
+ mtk_cam_release_all_buffer(cam);
+ /* relese bufs by request */
+ return ret;
+}
+
+static void mtk_cam_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vq);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ struct device *dev = cam->dev;
+ struct mtk_cam_ctx *ctx;
+
+ ctx = mtk_cam_find_ctx(cam, &node->vdev.entity);
+ if (WARN_ON(!ctx)) {
+ /* the ctx is stop, media_pipeline_stop is called */
+ mtk_cam_dev_req_clean_pending(cam, node->uid.pipe_id,
+ VB2_BUF_STATE_ERROR);
+ return;
+ }
+
+ dev_dbg(dev, "%s:%s:ctx(%d): node:%d count info:%d\n", __func__,
+ node->desc.name, ctx->stream_id, node->desc.id,
+ ctx->streaming_node_cnt);
+
+ mtk_cam_ctx_stream_off(ctx, node);
+
+ if (cam->streaming_pipe & (1 << node->uid.pipe_id)) {
+ /* NOTE: take multi-pipelines case into consideration */
+ /* Moreover, must clean bit mask before req cleanup */
+ /* Otherwise, would cause req not removed in pending list */
+ cam->streaming_pipe &= ~(1 << node->uid.pipe_id);
+ mtk_cam_dev_req_cleanup(ctx, node->uid.pipe_id, VB2_BUF_STATE_ERROR);
+ }
+
+ /* all bufs of node should be return by per requests */
+ mtk_cam_release_all_buffer(ctx->cam);
+
+ /* NOTE: take multi-pipelines case into consideration */
+ cam->streaming_pipe &= ~(1 << node->uid.pipe_id);
+ ctx->streaming_node_cnt--;
+ if (ctx->streaming_node_cnt)
+ return;
+
+ mtk_cam_stop_ctx(ctx, node);
+}
+
+int is_mtk_format(u32 pixelformat)
+{
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_YUYV10:
+ case V4L2_PIX_FMT_YVYU10:
+ case V4L2_PIX_FMT_UYVY10:
+ case V4L2_PIX_FMT_VYUY10:
+ case V4L2_PIX_FMT_YUYV12:
+ case V4L2_PIX_FMT_YVYU12:
+ case V4L2_PIX_FMT_UYVY12:
+ case V4L2_PIX_FMT_VYUY12:
+ case V4L2_PIX_FMT_MTISP_YUYV10P:
+ case V4L2_PIX_FMT_MTISP_YVYU10P:
+ case V4L2_PIX_FMT_MTISP_UYVY10P:
+ case V4L2_PIX_FMT_MTISP_VYUY10P:
+ case V4L2_PIX_FMT_MTISP_YUYV12P:
+ case V4L2_PIX_FMT_MTISP_YVYU12P:
+ case V4L2_PIX_FMT_MTISP_UYVY12P:
+ case V4L2_PIX_FMT_MTISP_VYUY12P:
+ case V4L2_PIX_FMT_NV12_10:
+ case V4L2_PIX_FMT_NV21_10:
+ case V4L2_PIX_FMT_NV16_10:
+ case V4L2_PIX_FMT_NV61_10:
+ case V4L2_PIX_FMT_NV12_12:
+ case V4L2_PIX_FMT_NV21_12:
+ case V4L2_PIX_FMT_NV16_12:
+ case V4L2_PIX_FMT_NV61_12:
+ case V4L2_PIX_FMT_MTISP_NV12_10P:
+ case V4L2_PIX_FMT_MTISP_NV21_10P:
+ case V4L2_PIX_FMT_MTISP_NV16_10P:
+ case V4L2_PIX_FMT_MTISP_NV61_10P:
+ case V4L2_PIX_FMT_MTISP_NV12_12P:
+ case V4L2_PIX_FMT_MTISP_NV21_12P:
+ case V4L2_PIX_FMT_MTISP_NV16_12P:
+ case V4L2_PIX_FMT_MTISP_NV61_12P:
+ case V4L2_PIX_FMT_MTISP_NV12_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV12_10_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_10_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV12_12_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_12_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER8_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER10_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER12_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER14_UFBC:
+ case V4L2_PIX_FMT_MTISP_SGRB8F:
+ case V4L2_PIX_FMT_MTISP_SGRB10F:
+ case V4L2_PIX_FMT_MTISP_SGRB12F:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int is_yuv_ufo(u32 pixelformat)
+{
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_MTISP_NV12_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV12_10_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_10_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV12_12_UFBC:
+ case V4L2_PIX_FMT_MTISP_NV21_12_UFBC:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int is_raw_ufo(u32 pixelformat)
+{
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_MTISP_BAYER8_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER10_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER12_UFBC:
+ case V4L2_PIX_FMT_MTISP_BAYER14_UFBC:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int is_fullg_rb(u32 pixelformat)
+{
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_MTISP_SGRB8F:
+ case V4L2_PIX_FMT_MTISP_SGRB10F:
+ case V4L2_PIX_FMT_MTISP_SGRB12F:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+const struct mtk_format_info *mtk_format_info(u32 format)
+{
+ static const struct mtk_format_info formats[] = {
+ /* YUV planar formats */
+ { .format = V4L2_PIX_FMT_NV12_10,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV21_10,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV16_10,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV61_10,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_YUYV10,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_YVYU10,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_UYVY10,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_VYUY10,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV12_12,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV21_12,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV16_12,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_NV61_12,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_YUYV12,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_YVYU12,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_UYVY12,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_VYUY12,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 2, .bit_r_den = 1 },
+ /* YUV packed formats */
+ { .format = V4L2_PIX_FMT_MTISP_YUYV10P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_YVYU10P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_UYVY10P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_VYUY10P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV12_10P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV21_10P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV16_10P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV61_10P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_YUYV12P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_YVYU12P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_UYVY12P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_VYUY12P,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_NV12_12P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_NV21_12P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_NV16_12P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_NV61_12P,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ /* YUV UFBC formats */
+ { .format = V4L2_PIX_FMT_MTISP_NV12_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_MTISP_NV21_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 2, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_MTISP_NV12_10_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV21_10_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_NV12_12_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_NV21_12_UFBC,
+ .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_BAYER8_UFBC,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 },
+ .hdiv = 1, .vdiv = 1, .bit_r_num = 1, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_MTISP_BAYER10_UFBC,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 },
+ .hdiv = 1, .vdiv = 1, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_BAYER12_UFBC,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 },
+ .hdiv = 1, .vdiv = 1, .bit_r_num = 3, .bit_r_den = 2 },
+ { .format = V4L2_PIX_FMT_MTISP_BAYER14_UFBC,
+ .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 },
+ .hdiv = 1, .vdiv = 1, .bit_r_num = 7, .bit_r_den = 4 },
+ /* Full-G RGB formats */
+ { .format = V4L2_PIX_FMT_MTISP_SGRB8F,
+ .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 1, .bit_r_den = 1 },
+ { .format = V4L2_PIX_FMT_MTISP_SGRB10F,
+ .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 5, .bit_r_den = 4 },
+ { .format = V4L2_PIX_FMT_MTISP_SGRB12F,
+ .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 },
+ .hdiv = 2, .vdiv = 2, .bit_r_num = 3, .bit_r_den = 2 },
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); ++i)
+ if (formats[i].format == format)
+ return &formats[i];
+ return NULL;
+}
+
+static void mtk_cam_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct mtk_cam_buffer *buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ struct mtk_cam_request *req = to_mtk_cam_req(vb->request);
+ struct mtk_cam_request_stream_data *req_stream_data;
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_raw_pde_config *pde_cfg;
+ struct device *dev = cam->dev;
+ struct mtkcam_ipi_frame_param *frame_param;
+ struct mtkcam_ipi_meta_input *meta_in;
+ struct mtkcam_ipi_meta_output *meta_out;
+ struct mtk_cam_ctx *ctx;
+ unsigned int pipe_id;
+ unsigned int desc_id;
+ unsigned int dma_port = node->desc.dma_port;
+
+ if (!vb->vb2_queue->uses_requests) {
+ spin_lock(&cam->dma_pending_lock);
+ list_add_tail(&buf->list, &cam->dma_pending);
+ spin_unlock(&cam->dma_pending_lock);
+ buf->state.estate = E_BUF_STATE_QUEUED;
+ if (media_entity_is_streaming(&node->vdev.entity)) {
+ ctx = mtk_cam_find_ctx(cam, &node->vdev.entity);
+ mtk_cam_buf_try_queue(ctx);
+ }
+ return;
+ }
+
+ dma_port = node->desc.dma_port;
+ pipe_id = node->uid.pipe_id;
+ req_stream_data = mtk_cam_req_get_s_data(req, pipe_id, 0);
+ frame_param = &req_stream_data->frame_params;
+ mtk_cam_s_data_set_vbuf(req_stream_data, buf, node->desc.id);
+
+ /* update buffer internal address */
+ switch (dma_port) {
+ case MTKCAM_IPI_RAW_META_STATS_CFG:
+ desc_id = node->desc.id - MTK_RAW_SINK_NUM;
+ meta_in = &frame_param->meta_inputs[desc_id];
+ meta_in->buf.size = node->active_fmt.fmt.meta.buffersize;
+ meta_in->buf.iova = buf->daddr;
+ meta_in->buf.scp_addr = buf->scp_addr;
+ meta_in->uid.id = dma_port;
+ break;
+ case MTKCAM_IPI_RAW_META_STATS_0:
+ case MTKCAM_IPI_RAW_META_STATS_1:
+ case MTKCAM_IPI_RAW_META_STATS_2:
+ pde_cfg = &cam->raw.pipelines[node->uid.pipe_id].pde_config;
+ desc_id = node->desc.id - MTK_RAW_META_OUT_BEGIN;
+ meta_out = &frame_param->meta_outputs[desc_id];
+ meta_out->buf.size = node->active_fmt.fmt.meta.buffersize;
+ meta_out->buf.iova = buf->daddr;
+ meta_out->buf.scp_addr = buf->scp_addr;
+ meta_out->uid.id = dma_port;
+ camsys_set_meta_stats_info(dma_port, vb, pde_cfg);
+ break;
+ default:
+ dev_dbg(dev, "%s:pipe(%d):buffer with invalid port(%d)\n",
+ __func__, pipe_id, dma_port);
+ break;
+ }
+}
+
+static void mtk_cam_vb2_buf_cleanup(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_cam_buffer *buf;
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct device *dev = cam->raw.devs[0];
+
+ /* SCP address is only valid for meta input buffer */
+ if (!node->desc.smem_alloc)
+ return;
+
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ dma_unmap_page_attrs(dev, buf->daddr, vb->planes[0].length,
+ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
+}
+
+static void mtk_cam_vb2_request_complete(struct vb2_buffer *vb)
+{
+ struct mtk_cam_device *cam = vb2_get_drv_priv(vb->vb2_queue);
+
+ dev_dbg(vb->vb2_queue->dev, "camsys | request %s\n", __func__);
+
+ v4l2_ctrl_request_complete(vb->req_obj.req, cam->v4l2_dev.ctrl_handler);
+}
+
+static int mtk_cam_vb2_buf_out_validate(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb);
+
+ if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
+ if (v4l2_buf->field == V4L2_FIELD_ANY)
+ v4l2_buf->field = V4L2_FIELD_NONE;
+
+ if (v4l2_buf->field != V4L2_FIELD_NONE)
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct vb2_ops mtk_cam_vb2_ops = {
+ .queue_setup = mtk_cam_vb2_queue_setup,
+
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+
+ .buf_out_validate = mtk_cam_vb2_buf_out_validate,
+ .buf_init = mtk_cam_vb2_buf_init,
+ .buf_prepare = mtk_cam_vb2_buf_prepare,
+
+ .start_streaming = mtk_cam_vb2_start_streaming,
+ .stop_streaming = mtk_cam_vb2_stop_streaming,
+
+ .buf_queue = mtk_cam_vb2_buf_queue,
+ .buf_cleanup = mtk_cam_vb2_buf_cleanup,
+ .buf_request_complete = mtk_cam_vb2_request_complete,
+};
+
+static const struct v4l2_file_operations mtk_cam_v4l2_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = video_ioctl2,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .poll = vb2_fop_poll,
+ .mmap = vb2_fop_mmap,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl32 = v4l2_compat_ioctl32,
+#endif
+};
+
+unsigned int mtk_cam_get_sensor_pixel_id(unsigned int fmt)
+{
+ switch (fmt & SENSOR_FMT_MASK) {
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ return MTKCAM_IPI_BAYER_PXL_ID_B;
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ return MTKCAM_IPI_BAYER_PXL_ID_GB;
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ return MTKCAM_IPI_BAYER_PXL_ID_GR;
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ return MTKCAM_IPI_BAYER_PXL_ID_R;
+ default:
+ return MTKCAM_IPI_BAYER_PXL_ID_UNKNOWN;
+ }
+}
+
+unsigned int mtk_cam_get_sensor_fmt(unsigned int fmt)
+{
+ switch (fmt & SENSOR_FMT_MASK) {
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ return MTKCAM_IPI_IMG_FMT_BAYER8;
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ return MTKCAM_IPI_IMG_FMT_BAYER10;
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ return MTKCAM_IPI_IMG_FMT_BAYER12;
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ return MTKCAM_IPI_IMG_FMT_BAYER14;
+ default:
+ return MTKCAM_IPI_IMG_FMT_UNKNOWN;
+ }
+}
+
+unsigned int mtk_cam_get_pixel_bits(unsigned int ipi_fmt)
+{
+ switch (ipi_fmt) {
+ case MTKCAM_IPI_IMG_FMT_BAYER8:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER8:
+ return 8;
+ case MTKCAM_IPI_IMG_FMT_BAYER10:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER10:
+ case MTKCAM_IPI_IMG_FMT_BAYER10_MIPI:
+ return 10;
+ case MTKCAM_IPI_IMG_FMT_BAYER12:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER12:
+ return 12;
+ case MTKCAM_IPI_IMG_FMT_BAYER14:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER14:
+ return 14;
+ case MTKCAM_IPI_IMG_FMT_BAYER10_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_BAYER12_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_BAYER14_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_BAYER16:
+ case MTKCAM_IPI_IMG_FMT_YUYV:
+ case MTKCAM_IPI_IMG_FMT_YVYU:
+ case MTKCAM_IPI_IMG_FMT_UYVY:
+ case MTKCAM_IPI_IMG_FMT_VYUY:
+ return 16;
+ case MTKCAM_IPI_IMG_FMT_Y8:
+ case MTKCAM_IPI_IMG_FMT_YUV_422_2P:
+ case MTKCAM_IPI_IMG_FMT_YVU_422_2P:
+ case MTKCAM_IPI_IMG_FMT_YUV_422_3P:
+ case MTKCAM_IPI_IMG_FMT_YVU_422_3P:
+ case MTKCAM_IPI_IMG_FMT_YUV_420_2P:
+ case MTKCAM_IPI_IMG_FMT_YVU_420_2P:
+ case MTKCAM_IPI_IMG_FMT_YUV_420_3P:
+ case MTKCAM_IPI_IMG_FMT_YVU_420_3P:
+ return 8;
+ case MTKCAM_IPI_IMG_FMT_YUYV_Y210:
+ case MTKCAM_IPI_IMG_FMT_YVYU_Y210:
+ case MTKCAM_IPI_IMG_FMT_UYVY_Y210:
+ case MTKCAM_IPI_IMG_FMT_VYUY_Y210:
+ return 32;
+ case MTKCAM_IPI_IMG_FMT_YUV_P210:
+ case MTKCAM_IPI_IMG_FMT_YVU_P210:
+ case MTKCAM_IPI_IMG_FMT_YUV_P010:
+ case MTKCAM_IPI_IMG_FMT_YVU_P010:
+ case MTKCAM_IPI_IMG_FMT_YUV_P212:
+ case MTKCAM_IPI_IMG_FMT_YVU_P212:
+ case MTKCAM_IPI_IMG_FMT_YUV_P012:
+ case MTKCAM_IPI_IMG_FMT_YVU_P012:
+ return 16;
+ case MTKCAM_IPI_IMG_FMT_YUYV_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVYU_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_UYVY_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_VYUY_Y210_PACKED:
+ return 20;
+ case MTKCAM_IPI_IMG_FMT_YUV_P210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P010_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P010_PACKED:
+ return 10;
+ case MTKCAM_IPI_IMG_FMT_YUV_P212_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P212_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P012_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P012_PACKED:
+ return 12;
+ case MTKCAM_IPI_IMG_FMT_RGB_8B_3P:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER8_3P:
+ case MTKCAM_IPI_IMG_FMT_UFBC_NV12:
+ case MTKCAM_IPI_IMG_FMT_UFBC_NV21:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER8:
+ return 8;
+ case MTKCAM_IPI_IMG_FMT_RGB_10B_3P_PACKED:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER10_3P_PACKED:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YUV_P010:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YVU_P010:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER10:
+ return 10;
+ case MTKCAM_IPI_IMG_FMT_RGB_12B_3P_PACKED:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER12_3P_PACKED:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YUV_P012:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YVU_P012:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER12:
+ return 12;
+ case MTKCAM_IPI_IMG_FMT_RGB_10B_3P:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER10_3P:
+ case MTKCAM_IPI_IMG_FMT_RGB_12B_3P:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER12_3P:
+ return 16;
+ default:
+ break;
+ }
+ pr_debug("not supported ipi-fmt 0x%08x", ipi_fmt);
+
+ return -1;
+}
+
+unsigned int mtk_cam_get_img_fmt(unsigned int fourcc)
+{
+ switch (fourcc) {
+ case V4L2_PIX_FMT_GREY:
+ return MTKCAM_IPI_IMG_FMT_Y8;
+ case V4L2_PIX_FMT_YUYV:
+ return MTKCAM_IPI_IMG_FMT_YUYV;
+ case V4L2_PIX_FMT_YVYU:
+ return MTKCAM_IPI_IMG_FMT_YVYU;
+ case V4L2_PIX_FMT_NV16:
+ return MTKCAM_IPI_IMG_FMT_YUV_422_2P;
+ case V4L2_PIX_FMT_NV61:
+ return MTKCAM_IPI_IMG_FMT_YVU_422_2P;
+ case V4L2_PIX_FMT_NV12:
+ return MTKCAM_IPI_IMG_FMT_YUV_420_2P;
+ case V4L2_PIX_FMT_NV21:
+ return MTKCAM_IPI_IMG_FMT_YVU_420_2P;
+ case V4L2_PIX_FMT_YUV422P:
+ return MTKCAM_IPI_IMG_FMT_YUV_422_3P;
+ case V4L2_PIX_FMT_YUV420:
+ return MTKCAM_IPI_IMG_FMT_YUV_420_3P;
+ case V4L2_PIX_FMT_YVU420:
+ return MTKCAM_IPI_IMG_FMT_YVU_420_3P;
+ case V4L2_PIX_FMT_NV12_10:
+ return MTKCAM_IPI_IMG_FMT_YUV_P010;
+ case V4L2_PIX_FMT_NV21_10:
+ return MTKCAM_IPI_IMG_FMT_YVU_P010;
+ case V4L2_PIX_FMT_NV16_10:
+ return MTKCAM_IPI_IMG_FMT_YUV_P210;
+ case V4L2_PIX_FMT_NV61_10:
+ return MTKCAM_IPI_IMG_FMT_YVU_P210;
+ case V4L2_PIX_FMT_MTISP_NV12_10P:
+ return MTKCAM_IPI_IMG_FMT_YUV_P010_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV21_10P:
+ return MTKCAM_IPI_IMG_FMT_YVU_P010_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV16_10P:
+ return MTKCAM_IPI_IMG_FMT_YUV_P210_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV61_10P:
+ return MTKCAM_IPI_IMG_FMT_YVU_P210_PACKED;
+ case V4L2_PIX_FMT_YUYV10:
+ return MTKCAM_IPI_IMG_FMT_YUYV_Y210;
+ case V4L2_PIX_FMT_YVYU10:
+ return MTKCAM_IPI_IMG_FMT_YVYU_Y210;
+ case V4L2_PIX_FMT_UYVY10:
+ return MTKCAM_IPI_IMG_FMT_UYVY_Y210;
+ case V4L2_PIX_FMT_VYUY10:
+ return MTKCAM_IPI_IMG_FMT_VYUY_Y210;
+ case V4L2_PIX_FMT_MTISP_YUYV10P:
+ return MTKCAM_IPI_IMG_FMT_YUYV_Y210_PACKED;
+ case V4L2_PIX_FMT_MTISP_YVYU10P:
+ return MTKCAM_IPI_IMG_FMT_YVYU_Y210_PACKED;
+ case V4L2_PIX_FMT_MTISP_UYVY10P:
+ return MTKCAM_IPI_IMG_FMT_UYVY_Y210_PACKED;
+ case V4L2_PIX_FMT_MTISP_VYUY10P:
+ return MTKCAM_IPI_IMG_FMT_VYUY_Y210_PACKED;
+ case V4L2_PIX_FMT_NV12_12:
+ return MTKCAM_IPI_IMG_FMT_YUV_P012;
+ case V4L2_PIX_FMT_NV21_12:
+ return MTKCAM_IPI_IMG_FMT_YVU_P012;
+ case V4L2_PIX_FMT_NV16_12:
+ return MTKCAM_IPI_IMG_FMT_YUV_P212;
+ case V4L2_PIX_FMT_NV61_12:
+ return MTKCAM_IPI_IMG_FMT_YVU_P212;
+ case V4L2_PIX_FMT_MTISP_NV12_12P:
+ return MTKCAM_IPI_IMG_FMT_YUV_P012_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV21_12P:
+ return MTKCAM_IPI_IMG_FMT_YVU_P012_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV16_12P:
+ return MTKCAM_IPI_IMG_FMT_YUV_P212_PACKED;
+ case V4L2_PIX_FMT_MTISP_NV61_12P:
+ return MTKCAM_IPI_IMG_FMT_YVU_P212_PACKED;
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ return MTKCAM_IPI_IMG_FMT_BAYER8;
+ case V4L2_PIX_FMT_MTISP_SBGGR8F:
+ case V4L2_PIX_FMT_MTISP_SGBRG8F:
+ case V4L2_PIX_FMT_MTISP_SGRBG8F:
+ case V4L2_PIX_FMT_MTISP_SRGGB8F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER8;
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ return MTKCAM_IPI_IMG_FMT_BAYER10_UNPACKED;
+ case V4L2_PIX_FMT_SBGGR10P:
+ case V4L2_PIX_FMT_SGBRG10P:
+ case V4L2_PIX_FMT_SGRBG10P:
+ case V4L2_PIX_FMT_SRGGB10P:
+ return MTKCAM_IPI_IMG_FMT_BAYER10_MIPI;
+ case V4L2_PIX_FMT_MTISP_SBGGR10:
+ case V4L2_PIX_FMT_MTISP_SGBRG10:
+ case V4L2_PIX_FMT_MTISP_SGRBG10:
+ case V4L2_PIX_FMT_MTISP_SRGGB10:
+ return MTKCAM_IPI_IMG_FMT_BAYER10;
+ case V4L2_PIX_FMT_MTISP_SBGGR10F:
+ case V4L2_PIX_FMT_MTISP_SGBRG10F:
+ case V4L2_PIX_FMT_MTISP_SGRBG10F:
+ case V4L2_PIX_FMT_MTISP_SRGGB10F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER10;
+ case V4L2_PIX_FMT_SBGGR12:
+ case V4L2_PIX_FMT_SGBRG12:
+ case V4L2_PIX_FMT_SGRBG12:
+ case V4L2_PIX_FMT_SRGGB12:
+ return MTKCAM_IPI_IMG_FMT_BAYER12_UNPACKED;
+ case V4L2_PIX_FMT_MTISP_SBGGR12:
+ case V4L2_PIX_FMT_MTISP_SGBRG12:
+ case V4L2_PIX_FMT_MTISP_SGRBG12:
+ case V4L2_PIX_FMT_MTISP_SRGGB12:
+ return MTKCAM_IPI_IMG_FMT_BAYER12;
+ case V4L2_PIX_FMT_MTISP_SBGGR12F:
+ case V4L2_PIX_FMT_MTISP_SGBRG12F:
+ case V4L2_PIX_FMT_MTISP_SGRBG12F:
+ case V4L2_PIX_FMT_MTISP_SRGGB12F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER12;
+ case V4L2_PIX_FMT_SBGGR14:
+ case V4L2_PIX_FMT_SGBRG14:
+ case V4L2_PIX_FMT_SGRBG14:
+ case V4L2_PIX_FMT_SRGGB14:
+ return MTKCAM_IPI_IMG_FMT_BAYER14_UNPACKED;
+ case V4L2_PIX_FMT_MTISP_SBGGR14:
+ case V4L2_PIX_FMT_MTISP_SGBRG14:
+ case V4L2_PIX_FMT_MTISP_SGRBG14:
+ case V4L2_PIX_FMT_MTISP_SRGGB14:
+ return MTKCAM_IPI_IMG_FMT_BAYER14;
+ case V4L2_PIX_FMT_MTISP_SBGGR14F:
+ case V4L2_PIX_FMT_MTISP_SGBRG14F:
+ case V4L2_PIX_FMT_MTISP_SGRBG14F:
+ case V4L2_PIX_FMT_MTISP_SRGGB14F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER14;
+ case V4L2_PIX_FMT_SBGGR16:
+ case V4L2_PIX_FMT_SGBRG16:
+ case V4L2_PIX_FMT_SGRBG16:
+ case V4L2_PIX_FMT_SRGGB16:
+ return MTKCAM_IPI_IMG_FMT_BAYER16;
+ case V4L2_PIX_FMT_MTISP_NV12_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_NV12;
+ case V4L2_PIX_FMT_MTISP_NV21_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_NV21;
+ case V4L2_PIX_FMT_MTISP_NV12_10_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_YUV_P010;
+ case V4L2_PIX_FMT_MTISP_NV21_10_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_YVU_P010;
+ case V4L2_PIX_FMT_MTISP_NV12_12_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_YUV_P012;
+ case V4L2_PIX_FMT_MTISP_NV21_12_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_YVU_P012;
+ case V4L2_PIX_FMT_MTISP_BAYER8_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_BAYER8;
+ case V4L2_PIX_FMT_MTISP_BAYER10_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_BAYER10;
+ case V4L2_PIX_FMT_MTISP_BAYER12_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_BAYER12;
+ case V4L2_PIX_FMT_MTISP_BAYER14_UFBC:
+ return MTKCAM_IPI_IMG_FMT_UFBC_BAYER14;
+ case V4L2_PIX_FMT_MTISP_SGRB8F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER8_3P;
+ case V4L2_PIX_FMT_MTISP_SGRB10F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER10_3P_PACKED;
+ case V4L2_PIX_FMT_MTISP_SGRB12F:
+ return MTKCAM_IPI_IMG_FMT_FG_BAYER12_3P_PACKED;
+ default:
+ return MTKCAM_IPI_IMG_FMT_UNKNOWN;
+ }
+}
+
+static void mtk_cam_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+ u32 pixelformat, u32 width, u32 height)
+{
+ struct v4l2_plane_pix_format *plane;
+ unsigned int ipi_fmt = mtk_cam_get_img_fmt(pixelformat);
+ u8 pixel_bits = mtk_cam_get_pixel_bits(ipi_fmt);
+ u32 stride;
+ u32 aligned_width;
+ u8 bus_size;
+ u8 i;
+
+ pixfmt->width = width;
+ pixfmt->height = height;
+ pixfmt->pixelformat = pixelformat;
+ plane = &pixfmt->plane_fmt[0];
+ bus_size = mtk_cam_yuv_dma_bus_size(pixel_bits, 0);
+ plane->sizeimage = 0;
+
+ if (is_mtk_format(pixelformat)) {
+ const struct mtk_format_info *info;
+
+ info = mtk_format_info(pixelformat);
+ if (!info)
+ return;
+
+ pixfmt->num_planes = info->mem_planes;
+ if (info->mem_planes == 1) {
+ if (is_yuv_ufo(pixelformat)) {
+ /* UFO format width should align 64 pixel */
+ aligned_width = ALIGN(width, 64);
+ stride = aligned_width * info->bit_r_num / info->bit_r_den;
+
+ if (stride > plane->bytesperline)
+ plane->bytesperline = stride;
+ plane->sizeimage = stride * height;
+ plane->sizeimage += stride * height / 2;
+ plane->sizeimage += ALIGN((aligned_width / 64), 8) * height;
+ plane->sizeimage += ALIGN((aligned_width / 64), 8) * height / 2;
+ plane->sizeimage += sizeof(struct ufbc_buffer_header);
+ } else if (is_raw_ufo(pixelformat)) {
+ /* UFO format width should align 64 pixel */
+ aligned_width = ALIGN(width, 64);
+ stride = aligned_width * info->bit_r_num / info->bit_r_den;
+
+ if (stride > plane->bytesperline)
+ plane->bytesperline = stride;
+ plane->sizeimage = stride * height;
+ plane->sizeimage += ALIGN((aligned_width / 64), 8) * height;
+ plane->sizeimage += sizeof(struct ufbc_buffer_header);
+ } else {
+ /* width should be bus_size align */
+ aligned_width = ALIGN(DIV_ROUND_UP(width
+ * info->bit_r_num, info->bit_r_den), bus_size);
+ stride = aligned_width * info->bpp[0];
+
+ if (stride > plane->bytesperline)
+ plane->bytesperline = stride;
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ if (plane->bytesperline > stride &&
+ is_fullg_rb(pixelformat)) {
+ plane->sizeimage +=
+ DIV_ROUND_UP(plane->bytesperline, hdiv)
+ * DIV_ROUND_UP(height, vdiv);
+ } else if (plane->bytesperline > stride &&
+ !is_fullg_rb(pixelformat)) {
+ plane->sizeimage +=
+ plane->bytesperline
+ * DIV_ROUND_UP(height, vdiv);
+ } else {
+ plane->sizeimage += info->bpp[i]
+ * DIV_ROUND_UP(aligned_width, hdiv)
+ * DIV_ROUND_UP(height, vdiv);
+ }
+ }
+ }
+ pr_debug("%s stride %d sizeimage %d\n", __func__,
+ plane->bytesperline, plane->sizeimage);
+ } else {
+ pr_debug("do not support non contiguous mplane\n");
+ }
+ } else {
+ const struct v4l2_format_info *info;
+
+ pr_debug("pixelformat:0x%x sizeimage:%d\n",
+ pixelformat, plane->sizeimage);
+ info = v4l2_format_info(pixelformat);
+ if (!info)
+ return;
+
+ pixfmt->num_planes = info->mem_planes;
+ if (info->mem_planes == 1) {
+ aligned_width = ALIGN(width, bus_size);
+ stride = aligned_width * info->bpp[0];
+ if (stride > plane->bytesperline)
+ plane->bytesperline = stride;
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ plane->sizeimage += info->bpp[i]
+ * DIV_ROUND_UP(aligned_width, hdiv)
+ * DIV_ROUND_UP(height, vdiv);
+ }
+ pr_debug("%s stride %d sizeimage %d\n", __func__,
+ plane->bytesperline, plane->sizeimage);
+ } else {
+ pr_warn("do not support non contiguous mplane\n");
+ }
+ }
+}
+
+static void mtk_cam_fill_ext_fmtdesc(struct v4l2_fmtdesc *fmt)
+{
+ const char *descr = NULL;
+ const unsigned int sz = sizeof(fmt->description);
+
+ switch (fmt->pixelformat) {
+ case V4L2_PIX_FMT_MTISP_SBGGR8:
+ descr = "8-bit Bayer BGGR MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG8:
+ descr = "8-bit Bayer GBRG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG8:
+ descr = "8-bit Bayer GRBG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB8:
+ descr = "8-bit Bayer RGGB MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR10:
+ descr = "10-bit Bayer BGGR MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG10:
+ descr = "10-bit Bayer GBRG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG10:
+ descr = "10-bit Bayer GRBG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB10:
+ descr = "10-bit Bayer RGGB MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR12:
+ descr = "12-bit Bayer BGGR MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG12:
+ descr = "12-bit Bayer GBRG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG12:
+ descr = "12-bit Bayer GRBG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB12:
+ descr = "12-bit Bayer RGGB MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR14:
+ descr = "14-bit Bayer BGGR MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG14:
+ descr = "14-bit Bayer GBRG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG14:
+ descr = "14-bit Bayer GRBG MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB14:
+ descr = "14-bit Bayer RGGB MTISP Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR8F:
+ descr = "8-bit Full-G Bayer BGGR Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG8F:
+ descr = "8-bit Full-G Bayer GBRG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG8F:
+ descr = "8-bit Full-G Bayer GRBG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB8F:
+ descr = "8-bit Full-G Bayer RGGB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR10F:
+ descr = "10-bit Full-G Bayer BGGR Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG10F:
+ descr = "10-bit Full-G Bayer GBRG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG10F:
+ descr = "10-bit Full-G Bayer GRBG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB10F:
+ descr = "10-bit Full-G Bayer RGGB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR12F:
+ descr = "12-bit Full-G Bayer BGGR Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG12F:
+ descr = "12-bit Full-G Bayer GBRG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG12F:
+ descr = "12-bit Full-G Bayer GRBG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB12F:
+ descr = "12-bit Full-G Bayer RGGB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SBGGR14F:
+ descr = "14-bit Full-G Bayer BGGR Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGBRG14F:
+ descr = "14-bit Full-G Bayer GBRG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRBG14F:
+ descr = "14-bit Full-G Bayer GRBG Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SRGGB14F:
+ descr = "14-bit Full-G Bayer RGGB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV12_10P:
+ descr = "Y/CbCr 4:2:0 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV21_10P:
+ descr = "Y/CrCb 4:2:0 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV16_10P:
+ descr = "Y/CbCr 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV61_10P:
+ descr = "Y/CrCb 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_YUYV10P:
+ descr = "YUYV 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_YVYU10P:
+ descr = "YVYU 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_UYVY10P:
+ descr = "UYVY 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_VYUY10P:
+ descr = "VYUY 4:2:2 10 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV12_12P:
+ descr = "Y/CbCr 4:2:0 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV21_12P:
+ descr = "Y/CrCb 4:2:0 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV16_12P:
+ descr = "Y/CbCr 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV61_12P:
+ descr = "Y/CrCb 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_YUYV12P:
+ descr = "YUYV 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_YVYU12P:
+ descr = "YVYU 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_UYVY12P:
+ descr = "UYVY 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_VYUY12P:
+ descr = "VYUY 4:2:2 12 bits packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV12_UFBC:
+ descr = "YCbCr 420 8 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV21_UFBC:
+ descr = "YCrCb 420 8 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV12_10_UFBC:
+ descr = "YCbCr 420 10 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV21_10_UFBC:
+ descr = "YCrCb 420 10 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV12_12_UFBC:
+ descr = "YCbCr 420 12 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_NV21_12_UFBC:
+ descr = "YCrCb 420 12 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_BAYER8_UFBC:
+ descr = "RAW 8 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_BAYER10_UFBC:
+ descr = "RAW 10 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_BAYER12_UFBC:
+ descr = "RAW 12 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_BAYER14_UFBC:
+ descr = "RAW 14 bits compress";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRB8F:
+ descr = "8-bit 3 plane GRB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRB10F:
+ descr = "10-bit 3 plane GRB Packed";
+ break;
+ case V4L2_PIX_FMT_MTISP_SGRB12F:
+ descr = "12-bit 3 plane GRB Packed";
+ break;
+ case V4L2_META_FMT_MTISP_PARAMS:
+ descr = "MTK ISP Tuning Metadata";
+ break;
+ case V4L2_META_FMT_MTISP_3A:
+ descr = "MTK 3A Statistics";
+ break;
+ case V4L2_META_FMT_MTISP_AF:
+ descr = "MTK AF Statistics";
+ break;
+ case V4L2_META_FMT_MTISP_LCS:
+ descr = "MTK LCS Statistics";
+ break;
+ case V4L2_META_FMT_MTISP_LMV:
+ descr = "MTK LMV Statistics";
+ break;
+ default:
+ descr = NULL;
+ break;
+ }
+
+ if (descr)
+ WARN_ON(strscpy(fmt->description, descr, sz) < 0);
+}
+
+static void cal_image_pix_mp(unsigned int node_id,
+ struct v4l2_pix_format_mplane *mp,
+ unsigned int pixel_mode)
+{
+ unsigned int ipi_fmt = mtk_cam_get_img_fmt(mp->pixelformat);
+ unsigned int width = mp->width;
+ unsigned int height = mp->height;
+ unsigned int stride, i;
+
+ pr_debug("fmt:0x%x ipi_fmt:%d\n", mp->pixelformat, ipi_fmt);
+ switch (ipi_fmt) {
+ case MTKCAM_IPI_IMG_FMT_BAYER8:
+ case MTKCAM_IPI_IMG_FMT_BAYER10:
+ case MTKCAM_IPI_IMG_FMT_BAYER12:
+ case MTKCAM_IPI_IMG_FMT_BAYER14:
+ case MTKCAM_IPI_IMG_FMT_BAYER16:
+ case MTKCAM_IPI_IMG_FMT_BAYER10_MIPI:
+ case MTKCAM_IPI_IMG_FMT_BAYER10_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_BAYER12_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_BAYER14_UNPACKED:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER8:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER10:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER12:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER14:
+ stride = mtk_cam_dmao_xsize(width, ipi_fmt, pixel_mode);
+ for (i = 0; i < mp->num_planes; i++) {
+ if (stride > mp->plane_fmt[i].bytesperline)
+ mp->plane_fmt[i].bytesperline = stride;
+ mp->plane_fmt[i].sizeimage =
+ mp->plane_fmt[i].bytesperline * height;
+ }
+ break;
+ case MTKCAM_IPI_IMG_FMT_YUYV:
+ case MTKCAM_IPI_IMG_FMT_YVYU:
+ case MTKCAM_IPI_IMG_FMT_UYVY:
+ case MTKCAM_IPI_IMG_FMT_VYUY:
+ case MTKCAM_IPI_IMG_FMT_YUV_422_2P:
+ case MTKCAM_IPI_IMG_FMT_YVU_422_2P:
+ case MTKCAM_IPI_IMG_FMT_YUV_422_3P:
+ case MTKCAM_IPI_IMG_FMT_YVU_422_3P:
+ case MTKCAM_IPI_IMG_FMT_YUV_420_2P:
+ case MTKCAM_IPI_IMG_FMT_YVU_420_2P:
+ case MTKCAM_IPI_IMG_FMT_YUV_420_3P:
+ case MTKCAM_IPI_IMG_FMT_YVU_420_3P:
+ case MTKCAM_IPI_IMG_FMT_Y8:
+ case MTKCAM_IPI_IMG_FMT_YUYV_Y210:
+ case MTKCAM_IPI_IMG_FMT_YVYU_Y210:
+ case MTKCAM_IPI_IMG_FMT_UYVY_Y210:
+ case MTKCAM_IPI_IMG_FMT_VYUY_Y210:
+ case MTKCAM_IPI_IMG_FMT_YUYV_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVYU_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_UYVY_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_VYUY_Y210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P210:
+ case MTKCAM_IPI_IMG_FMT_YVU_P210:
+ case MTKCAM_IPI_IMG_FMT_YUV_P010:
+ case MTKCAM_IPI_IMG_FMT_YVU_P010:
+ case MTKCAM_IPI_IMG_FMT_YUV_P210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P210_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P010_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P010_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P212:
+ case MTKCAM_IPI_IMG_FMT_YVU_P212:
+ case MTKCAM_IPI_IMG_FMT_YUV_P012:
+ case MTKCAM_IPI_IMG_FMT_YVU_P012:
+ case MTKCAM_IPI_IMG_FMT_YUV_P212_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P212_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YUV_P012_PACKED:
+ case MTKCAM_IPI_IMG_FMT_YVU_P012_PACKED:
+ case MTKCAM_IPI_IMG_FMT_UFBC_NV12:
+ case MTKCAM_IPI_IMG_FMT_UFBC_NV21:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YUV_P010:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YVU_P010:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YUV_P012:
+ case MTKCAM_IPI_IMG_FMT_UFBC_YVU_P012:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER8:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER10:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER12:
+ case MTKCAM_IPI_IMG_FMT_UFBC_BAYER14:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER8_3P:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER10_3P_PACKED:
+ case MTKCAM_IPI_IMG_FMT_FG_BAYER12_3P_PACKED:
+ mtk_cam_fill_pixfmt_mp(mp, mp->pixelformat, width, height);
+ break;
+ default:
+ break;
+ }
+}
+
+static int mtk_video_init_format(struct mtk_cam_video_device *video)
+{
+ struct mtk_cam_dev_node_desc *desc = &video->desc;
+ struct v4l2_format *active = &video->active_fmt;
+ const struct v4l2_format *default_fmt =
+ &desc->fmts[desc->default_fmt_idx].vfmt;
+
+ active->type = desc->buf_type;
+
+ if (!desc->image) {
+ active->fmt.meta.dataformat = default_fmt->fmt.meta.dataformat;
+ active->fmt.meta.buffersize = default_fmt->fmt.meta.buffersize;
+ return 0;
+ }
+
+ active->fmt.pix_mp.pixelformat = default_fmt->fmt.pix_mp.pixelformat;
+ active->fmt.pix_mp.width = default_fmt->fmt.pix_mp.width;
+ active->fmt.pix_mp.height = default_fmt->fmt.pix_mp.height;
+ active->fmt.pix_mp.num_planes = default_fmt->fmt.pix_mp.num_planes;
+
+ cal_image_pix_mp(desc->id, &active->fmt.pix_mp, 0);
+
+ /* set init one-plane */
+ active->fmt.pix_mp.num_planes = 1;
+ active->fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+ active->fmt.pix_mp.field = V4L2_FIELD_NONE;
+ active->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ active->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ active->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_SRGB;
+
+ return 0;
+}
+
+int mtk_cam_video_register(struct mtk_cam_video_device *video,
+ struct v4l2_device *v4l2_dev)
+{
+ struct mtk_cam_device *cam =
+ container_of(v4l2_dev, struct mtk_cam_device, v4l2_dev);
+ struct media_pad *pad = &video->pad;
+ struct video_device *vdev = &video->vdev;
+ struct vb2_queue *q = &video->vb2_q;
+ unsigned int output = V4L2_TYPE_IS_OUTPUT(video->desc.buf_type);
+ int ret;
+
+ if (video->desc.link_flags & MEDIA_LNK_FL_ENABLED)
+ video->enabled = true;
+ else
+ video->enabled = false;
+
+ mutex_init(&video->q_lock);
+
+ /* initialize vb2_queue */
+ q->type = video->desc.buf_type;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+
+ if (q->type == V4L2_BUF_TYPE_META_OUTPUT)
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ else
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_BOOTIME;
+
+ if (video->desc.smem_alloc) {
+ q->bidirectional = 1;
+ /* reserved memory */
+ q->dev = cam->smem_dev;
+ } else if (is_yuv_node(video->desc.id)) {
+ q->dev = cam->raw.yuvs[0];
+ } else {
+ q->dev = cam->raw.devs[0];
+ }
+
+ q->supports_requests = true;
+ q->lock = &video->q_lock;
+ q->ops = &mtk_cam_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->drv_priv = cam;
+ q->buf_struct_size = sizeof(struct mtk_cam_buffer);
+
+ if (output)
+ q->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
+ else
+ q->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_SOE;
+
+ /* No minimum buffers limitation */
+ q->min_queued_buffers = 0;
+
+ ret = vb2_queue_init(q);
+ if (ret < 0) {
+ dev_info(v4l2_dev->dev, "Failed to init vb2 queue: %d\n", ret);
+ goto error_vb2_init;
+ }
+
+ pad->flags = output ? MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;
+ ret = media_entity_pads_init(&vdev->entity, 1, pad);
+ if (ret < 0) {
+ dev_info(v4l2_dev->dev, "Failed to init video entity: %d\n", ret);
+ goto error_media_init;
+ }
+
+ ret = mtk_video_init_format(video);
+ if (ret < 0) {
+ dev_info(v4l2_dev->dev, "Failed to init format: %d\n", ret);
+ goto error_video_register;
+ }
+
+ vdev->entity.function = MEDIA_ENT_F_IO_V4L;
+ vdev->entity.ops = NULL;
+ vdev->fops = &mtk_cam_v4l2_fops;
+ vdev->device_caps = video->desc.cap | V4L2_CAP_STREAMING;
+ vdev->v4l2_dev = v4l2_dev;
+
+ vdev->vfl_dir = output ? VFL_DIR_TX : VFL_DIR_RX;
+ vdev->queue = &video->vb2_q;
+ vdev->ioctl_ops = video->desc.ioctl_ops;
+ vdev->release = video_device_release_empty;
+ /* share q_lock */
+ vdev->lock = &video->q_lock;
+ strscpy(vdev->name, video->desc.name, sizeof(vdev->name));
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret < 0) {
+ dev_info(v4l2_dev->dev, "Failed to register video device: %d\n",
+ ret);
+ goto error_video_register;
+ }
+ video_set_drvdata(vdev, cam);
+
+ dev_dbg(v4l2_dev->dev, "registered vdev:%d:%s\n",
+ video->desc.id, vdev->name);
+
+ return 0;
+
+error_video_register:
+ media_entity_cleanup(&vdev->entity);
+error_media_init:
+ vb2_queue_release(&video->vb2_q);
+error_vb2_init:
+ mutex_destroy(&video->q_lock);
+
+ return ret;
+}
+
+void mtk_cam_video_unregister(struct mtk_cam_video_device *video)
+{
+ video_unregister_device(&video->vdev);
+ vb2_queue_release(&video->vb2_q);
+ media_entity_cleanup(&video->vdev.entity);
+ mutex_destroy(&video->q_lock);
+}
+
+const struct v4l2_format *
+mtk_cam_dev_find_fmt(struct mtk_cam_dev_node_desc *desc, u32 format)
+{
+ unsigned int i;
+ const struct v4l2_format *fmt;
+
+ for (i = 0; i < desc->num_fmts; i++) {
+ fmt = &desc->fmts[i].vfmt;
+ if (fmt->fmt.pix_mp.pixelformat == format)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+int mtk_cam_vidioc_querycap(struct file *file, void *fh,
+ struct v4l2_capability *cap)
+{
+ struct mtk_cam_device *cam = video_drvdata(file);
+
+ strscpy(cap->driver, dev_driver_string(cam->dev), sizeof(cap->driver));
+ strscpy(cap->card, dev_driver_string(cam->dev), sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+ dev_name(cam->dev));
+
+ return 0;
+}
+
+int mtk_cam_vidioc_enum_framesizes(struct file *filp, void *priv,
+ struct v4l2_frmsizeenum *sizes)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(filp);
+ const struct v4l2_format *dev_fmt;
+
+ dev_fmt = mtk_cam_dev_find_fmt(&node->desc, sizes->pixel_format);
+ if (!dev_fmt || sizes->index)
+ return -EINVAL;
+
+ sizes->type = node->desc.frmsizes->type;
+ memcpy(&sizes->stepwise, &node->desc.frmsizes->stepwise,
+ sizeof(sizes->stepwise));
+ return 0;
+}
+
+int mtk_cam_vidioc_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ if (f->index >= node->desc.num_fmts)
+ return -EINVAL;
+
+ f->pixelformat = node->desc.fmts[f->index].vfmt.fmt.pix_mp.pixelformat;
+ f->flags = 0;
+ /* extended fmt description is filled here */
+ /* common fmt description is filled in v4l_fill_fmtdesc */
+ mtk_cam_fill_ext_fmtdesc(f);
+
+ return 0;
+}
+
+int mtk_cam_vidioc_g_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ f->fmt = node->active_fmt.fmt;
+
+ return 0;
+}
+
+int mtk_cam_vidioc_s_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_device *cam = video_drvdata(file);
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+ struct mtk_raw_pipeline *raw_pipeline;
+ int raw_feature = 0;
+
+ raw_pipeline = mtk_cam_dev_get_raw_pipeline(cam, node->uid.pipe_id);
+
+ if (!vb2_is_busy(node->vdev.queue)) {
+ /* Get the valid format */
+ if (raw_pipeline)
+ raw_feature = raw_pipeline->user_res.raw_res.feature;
+
+ mtk_cam_video_set_fmt(node, f, raw_feature);
+
+ /* Configure to video device */
+ node->active_fmt = *f;
+ return 0;
+ }
+
+ dev_info(cam->dev,
+ "%s:pipe(%d):%s:Cannot change format while streaming\n",
+ __func__, node->uid.pipe_id, node->desc.name);
+
+ return -EBUSY;
+}
+
+int mtk_cam_video_set_fmt(struct mtk_cam_video_device *node,
+ struct v4l2_format *f, int raw_feature)
+{
+ struct mtk_cam_device *cam = video_get_drvdata(&node->vdev);
+ const struct v4l2_format *dev_fmt;
+ struct v4l2_format try_fmt;
+ s32 i;
+
+ dev_dbg(cam->dev,
+ "%s:pipe(%d):%s:feature(0x%x)\n",
+ __func__, node->uid.pipe_id, node->desc.name, raw_feature);
+
+ memset(&try_fmt, 0, sizeof(try_fmt));
+ try_fmt.type = f->type;
+
+ /* Validate pixelformat */
+ dev_fmt = mtk_cam_dev_find_fmt(&node->desc, f->fmt.pix_mp.pixelformat);
+ if (!dev_fmt) {
+ dev_dbg(cam->dev, "unknown fmt:%d\n",
+ f->fmt.pix_mp.pixelformat);
+ dev_fmt = &node->desc.fmts[node->desc.default_fmt_idx].vfmt;
+ }
+ try_fmt.fmt.pix_mp.pixelformat = dev_fmt->fmt.pix_mp.pixelformat;
+
+ /* Validate image width & height range */
+ try_fmt.fmt.pix_mp.width = clamp_val(f->fmt.pix_mp.width,
+ IMG_MIN_WIDTH, IMG_MAX_WIDTH);
+ try_fmt.fmt.pix_mp.height = clamp_val(f->fmt.pix_mp.height,
+ IMG_MIN_HEIGHT, IMG_MAX_HEIGHT);
+ /* 4 bytes alignment for width */
+ /* width and stride should align bus_size */
+ try_fmt.fmt.pix_mp.width = ALIGN(try_fmt.fmt.pix_mp.width, IMG_PIX_ALIGN);
+ try_fmt.fmt.pix_mp.num_planes = 1;
+
+ for (i = 0 ; i < try_fmt.fmt.pix_mp.num_planes ; i++)
+ try_fmt.fmt.pix_mp.plane_fmt[i].bytesperline =
+ f->fmt.pix_mp.plane_fmt[i].bytesperline;
+
+ /* bytesperline & sizeimage calculation */
+ cal_image_pix_mp(node->desc.id, &try_fmt.fmt.pix_mp, 0);
+
+ /* Constant format fields */
+ try_fmt.fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+ try_fmt.fmt.pix_mp.field = V4L2_FIELD_NONE;
+ try_fmt.fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ try_fmt.fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ try_fmt.fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_SRGB;
+
+ *f = try_fmt;
+
+ return 0;
+}
+
+int mtk_cam_vidioc_try_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ mtk_cam_video_set_fmt(node, f, 0);
+
+ return 0;
+}
+
+int mtk_cam_vidioc_meta_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ if (f->index)
+ return -EINVAL;
+
+ f->pixelformat = node->active_fmt.fmt.meta.dataformat;
+ f->flags = 0;
+ /* extended fmt description is filled here */
+ /* common fmt description is filled in v4l_fill_fmtdesc */
+ mtk_cam_fill_ext_fmtdesc(f);
+
+ return 0;
+}
+
+int mtk_cam_vidioc_g_meta_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_device *cam = video_drvdata(file);
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+ struct mtk_cam_dev_node_desc *desc = &node->desc;
+ const struct v4l2_format *default_fmt =
+ &desc->fmts[desc->default_fmt_idx].vfmt;
+ struct mtk_raw_pde_config *pde_cfg;
+ struct mtk_cam_pde_info *pde_info;
+
+ if (node->desc.dma_port == MTKCAM_IPI_RAW_META_STATS_CFG) {
+ pde_cfg = &cam->raw.pipelines[node->uid.pipe_id].pde_config;
+ pde_info = &pde_cfg->pde_info;
+ if (pde_info->pd_table_offset) {
+ node->active_fmt.fmt.meta.buffersize =
+ default_fmt->fmt.meta.buffersize +
+ pde_info->pdi_max_size;
+
+ dev_dbg(cam->dev, "PDE: node(%d), enlarge meta size(%u)",
+ node->desc.dma_port,
+ node->active_fmt.fmt.meta.buffersize);
+ }
+ }
+ if (node->desc.dma_port == MTKCAM_IPI_RAW_META_STATS_0) {
+ pde_cfg = &cam->raw.pipelines[node->uid.pipe_id].pde_config;
+ pde_info = &pde_cfg->pde_info;
+ if (pde_info->pd_table_offset) {
+ node->active_fmt.fmt.meta.buffersize =
+ default_fmt->fmt.meta.buffersize +
+ pde_info->pdo_max_size;
+
+ dev_dbg(cam->dev, "PDE: node(%d), enlarge meta size(%u)",
+ node->desc.dma_port,
+ node->active_fmt.fmt.meta.buffersize);
+ }
+ }
+ f->fmt.meta.dataformat = node->active_fmt.fmt.meta.dataformat;
+ f->fmt.meta.buffersize = node->active_fmt.fmt.meta.buffersize;
+
+ return 0;
+}
+
+int mtk_cam_vidioc_s_selection(struct file *file, void *fh,
+ struct v4l2_selection *s)
+{
+ struct mtk_cam_device *cam = video_drvdata(file);
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+ struct mtk_raw_pipeline *raw_pipeline;
+
+ raw_pipeline = mtk_cam_dev_get_raw_pipeline(cam, node->uid.pipe_id);
+ if (raw_pipeline) {
+ node->active_crop = *s;
+
+ dev_dbg(raw_pipeline->subdev.v4l2_dev->dev,
+ "%s:%s:%s:Set selection (%d,%d,%d,%d)\n",
+ __func__, raw_pipeline->subdev.name, node->desc.name,
+ s->r.left, s->r.top, s->r.width, s->r.height);
+ }
+
+ return 0;
+}
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
new file mode 100644
index 000000000000..6c79987670f8
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_VIDEO_H
+#define __MTK_CAM_VIDEO_H
+
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <media/media-entity.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-dev.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "mtk_cam-ipi.h"
+
+#define MAX_PLANE_NUM 3
+
+struct mtk_cam_resource;
+struct mtk_raw_pde_config;
+
+typedef int (*set_pad_fmt_func_t)(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *sink_fmt,
+ struct mtk_cam_resource *res,
+ int pad, int which);
+
+typedef int (*set_pad_selection_func_t)(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *sink_fmt,
+ struct mtk_cam_resource *res,
+ int pad, int which);
+
+/*For state analysis and controlling for request*/
+enum MTK_BUF_STATE {
+ E_BUF_STATE_QUEUED = 0x0,
+ E_BUF_STATE_COMPOSED,
+ E_BUF_STATE_CQ,
+ E_BUF_STATE_OUTER,
+};
+
+struct mtk_buf_state {
+ enum MTK_BUF_STATE estate;
+ struct list_head list;
+};
+
+/**
+ * struct mtk_cam_buffer - MTK camera device buffer.
+ *
+ * @vbb: Embedded struct vb2_v4l2_buffer.
+ * @list: List entry for the buffer queue
+ * @daddr: The DMA address of this buffer.
+ * @scp_addr: The SCP address of this buffer which
+ * is only supported for meta input node.
+ * @state: The camera buffer status.
+ */
+struct mtk_cam_buffer {
+ struct vb2_v4l2_buffer vbb;
+ struct list_head list;
+
+ dma_addr_t daddr;
+ dma_addr_t scp_addr;
+ struct mtk_buf_state state;
+};
+
+struct mtk_cam_format_desc {
+ struct v4l2_format vfmt;
+ struct v4l2_mbus_framefmt pfmt;
+};
+
+struct mtk_cam_pad_ops {
+ set_pad_fmt_func_t set_pad_fmt;
+ set_pad_selection_func_t set_pad_selection;
+};
+
+/**
+ * struct mtk_cam_dev_node_desc - MTK camera device node descriptor
+ *
+ * @id: id of the node
+ * @name: name of the node
+ * @cap: supported V4L2 capabilities
+ * @buf_type: supported V4L2 buffer type
+ * @dma_port: the dma ports associated to the node
+ * @link_flags: default media link flags
+ * @smem_alloc: using the smem_dev as alloc device or not
+ * @need_cache_sync_on_prepare: do cache sync at buf_prepare (userspace sync)
+ * @need_cache_sync_on_finish: do cache sync at buf_finish (userspace sync)
+ * @image: true for image node, false for meta node
+ * @num_fmts: the number of supported node formats
+ * @default_fmt_idx: default format of this node
+ * @max_buf_count: maximum VB2 buffer count
+ * @ioctl_ops: mapped to v4l2_ioctl_ops
+ * @fmts: supported format
+ * @frmsizes: supported V4L2 frame size number
+ * @pad_ops: set and select pad configurations and formats
+ */
+struct mtk_cam_dev_node_desc {
+ u8 id;
+ const char *name;
+ u32 cap;
+ u32 buf_type;
+ u32 dma_port;
+ u32 link_flags;
+ u8 smem_alloc:1;
+ u8 image:1;
+ u8 num_fmts;
+ u8 default_fmt_idx;
+ u8 max_buf_count;
+ const struct v4l2_ioctl_ops *ioctl_ops;
+ const struct mtk_cam_format_desc *fmts;
+ const struct v4l2_frmsizeenum *frmsizes;
+ struct mtk_cam_pad_ops *pad_ops;
+};
+
+/**
+ * struct mtk_cam_video_device - MediaTek video device structure.
+ */
+struct mtk_cam_video_device {
+ struct mtkcam_ipi_uid uid;
+ struct mtk_cam_dev_node_desc desc;
+ unsigned int enabled;
+
+ struct vb2_queue vb2_q;
+ struct video_device vdev;
+ struct media_pad pad;
+ struct v4l2_format active_fmt;
+ /* use first 4 elements of reserved field of v4l2_pix_format_mplane as request fd */
+ struct v4l2_format pending_fmt;
+ /* use first elements of reserved field of v4l2_selection as request fd*/
+ struct v4l2_selection active_crop;
+ /* Serializes vb2 queue and video device operations */
+ struct mutex q_lock;
+ int streaming_id;
+
+ /* cached ctx info */
+ struct mtk_cam_ctx *ctx;
+};
+
+struct mtk_format_info {
+ u32 format;
+ u8 mem_planes;
+ u8 comp_planes;
+ u8 bpp[4];
+ u8 hdiv;
+ u8 vdiv;
+ u8 bit_r_num; /* numerator of bit ratio */
+ u8 bit_r_den; /* denominator of bit ratio */
+};
+
+int mtk_cam_video_register(struct mtk_cam_video_device *video,
+ struct v4l2_device *v4l2_dev);
+
+void mtk_cam_video_unregister(struct mtk_cam_video_device *video);
+
+static inline struct mtk_cam_video_device *
+file_to_mtk_cam_node(struct file *__file)
+{
+ return container_of(video_devdata(__file), struct mtk_cam_video_device, vdev);
+}
+
+static inline struct mtk_cam_buffer *
+mtk_cam_vb2_buf_to_dev_buf(struct vb2_buffer *__vb)
+{
+ return container_of(__vb, struct mtk_cam_buffer, vbb.vb2_buf);
+}
+
+static inline struct mtk_cam_video_device *
+mtk_cam_vbq_to_vdev(struct vb2_queue *__vq)
+{
+ return container_of(__vq, struct mtk_cam_video_device, vb2_q);
+}
+
+const struct v4l2_format *
+mtk_cam_dev_find_fmt(struct mtk_cam_dev_node_desc *desc, u32 format);
+
+int mtk_cam_vidioc_querycap(struct file *file, void *fh,
+ struct v4l2_capability *cap);
+
+int mtk_cam_vidioc_enum_framesizes(struct file *filp, void *priv,
+ struct v4l2_frmsizeenum *sizes);
+
+int mtk_cam_vidioc_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+
+int mtk_cam_vidioc_g_fmt(struct file *file, void *fh, struct v4l2_format *f);
+
+int mtk_cam_vidioc_s_fmt(struct file *file, void *fh, struct v4l2_format *f);
+
+int mtk_cam_vidioc_try_fmt(struct file *file, void *fh, struct v4l2_format *f);
+
+int mtk_cam_vidioc_meta_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+
+int mtk_cam_vidioc_s_selection(struct file *file, void *fh,
+ struct v4l2_selection *s);
+
+int mtk_cam_vidioc_g_meta_fmt(struct file *file, void *fh,
+ struct v4l2_format *f);
+
+/* Utility functions to convert format enum */
+unsigned int mtk_cam_get_sensor_pixel_id(unsigned int fmt);
+
+unsigned int mtk_cam_get_sensor_fmt(unsigned int fmt);
+
+unsigned int mtk_cam_get_pixel_bits(unsigned int pix_fmt);
+
+unsigned int mtk_cam_get_img_fmt(unsigned int fourcc);
+
+int mtk_cam_video_set_fmt(struct mtk_cam_video_device *node,
+ struct v4l2_format *f, int feature);
+
+int is_mtk_format(u32 pixelformat);
+
+int is_yuv_ufo(u32 pixelformat);
+
+int is_raw_ufo(u32 pixelformat);
+
+int is_fullg_rb(u32 pixelformat);
+
+const struct mtk_format_info *mtk_format_info(u32 format);
+
+#endif /*__MTK_CAM_VIDEO_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
` (2 preceding siblings ...)
2024-10-09 11:15 ` [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops Shu-hsiang Yang
@ 2024-10-09 11:15 ` Shu-hsiang Yang
2024-10-16 1:56 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api Shu-hsiang Yang
` (7 subsequent siblings)
11 siblings, 1 reply; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
Add Kconfig and Makefile to include MTK ISP CAMSYS, integrating
the driver into the kernel build and configuration process.
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
drivers/media/platform/mediatek/Kconfig | 1 +
drivers/media/platform/mediatek/Makefile | 2 ++
drivers/media/platform/mediatek/isp/Kconfig | 21 +++++++++++++++++++
.../platform/mediatek/isp/isp_7x/Makefile | 7 +++++++
.../mediatek/isp/isp_7x/camsys/Makefile | 16 ++++++++++++++
5 files changed, 47 insertions(+)
create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
diff --git a/drivers/media/platform/mediatek/Kconfig b/drivers/media/platform/mediatek/Kconfig
index 84104e2cd024..a405d5701329 100644
--- a/drivers/media/platform/mediatek/Kconfig
+++ b/drivers/media/platform/mediatek/Kconfig
@@ -2,6 +2,7 @@
comment "Mediatek media platform drivers"
+source "drivers/media/platform/mediatek/isp/Kconfig"
source "drivers/media/platform/mediatek/jpeg/Kconfig"
source "drivers/media/platform/mediatek/mdp/Kconfig"
source "drivers/media/platform/mediatek/vcodec/Kconfig"
diff --git a/drivers/media/platform/mediatek/Makefile b/drivers/media/platform/mediatek/Makefile
index 38e6ba917fe5..74164df8c68d 100644
--- a/drivers/media/platform/mediatek/Makefile
+++ b/drivers/media/platform/mediatek/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
+
obj-y += jpeg/
obj-y += mdp/
obj-y += vcodec/
obj-y += vpu/
obj-y += mdp3/
+obj-y += isp/isp_7x/
diff --git a/drivers/media/platform/mediatek/isp/Kconfig b/drivers/media/platform/mediatek/isp/Kconfig
new file mode 100644
index 000000000000..8633e893a37d
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config VIDEO_MTK_ISP_71_CAMSYS
+ tristate "MediaTek ISP 7.1 camsys driver"
+ depends on ARCH_MEDIATEK
+ select V4L2_FWNODE
+ select VIDEO_V4L2_SUBDEV_API
+ select VIDEOBUF2_DMA_CONTIG
+ select RPMSG_MTK_CCD
+ select MTKCCD_REMOTEPROC
+ select MTK_SCP
+
+ default n
+ help
+ Camsys driver controls 3A (auto-focus, exposure,
+ and white balance) with tuning feature and outputs
+ the captured image buffers in MediaTek's ISP7 system.
+
+ Choose y if you want to use MediaTek SoCs to create image
+ captured application such as video recording and still image
+ capturing.
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/Makefile
new file mode 100644
index 000000000000..c927999cd854
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -Werror
+
+subdir-ccflags-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += -DISP7_1
+
+obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += camsys/
diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
new file mode 100644
index 000000000000..8e758cf6877f
--- /dev/null
+++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2022 MediaTek Inc.
+
+mtk-cam-isp-objs := mtk_cam.o mtk_cam-raw.o mtk_cam-pool.o \
+ mtk_cam-video.o mtk_cam-ctrl.o \
+ mtk_cam-seninf-route.o mtk_cam-seninf-drv.o \
+ mtk_cam-debug.o \
+ mtk_cam-raw_debug.o \
+ mtk_cam-feature.o mtk_cam-timesync.o
+
+mtk-cam-plat-util-objs := mtk_cam-plat-util.o
+
+include $(src)/mtk_csi_phy_2_0/Makefile
+
+obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += mtk-cam-plat-util.o
+obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += mtk-cam-isp.o
--
2.18.0
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
` (3 preceding siblings ...)
2024-10-09 11:15 ` [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config Shu-hsiang Yang
@ 2024-10-09 11:15 ` Shu-hsiang Yang
2024-10-11 7:47 ` CK Hu (胡俊光)
` (2 more replies)
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
` (6 subsequent siblings)
11 siblings, 3 replies; 88+ messages in thread
From: Shu-hsiang Yang @ 2024-10-09 11:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang, Shu-hsiang Yang
Add UAPI for MediaTek ISP platform, providing user-space
interfaces for the new camsys driver.
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
include/uapi/linux/mtkisp_camsys.h | 227 +++++++++++++++++++++++++++++
1 file changed, 227 insertions(+)
create mode 100644 include/uapi/linux/mtkisp_camsys.h
diff --git a/include/uapi/linux/mtkisp_camsys.h b/include/uapi/linux/mtkisp_camsys.h
new file mode 100644
index 000000000000..9c43f0799dbf
--- /dev/null
+++ b/include/uapi/linux/mtkisp_camsys.h
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * MediaTek ISP camsys User space API
+ *
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef _MTKISP_CAMSYS_USER_H
+#define _MTKISP_CAMSYS_USER_H
+
+#include <linux/videodev2.h>
+#include <linux/v4l2-controls.h>
+
+#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000
+#define V4L2_BUF_FLAG_TIMESTAMP_BOOTIME 0x00008000
+
+/* MTK ISP camsys events */
+#define V4L2_EVENT_REQUEST_DRAINED (V4L2_EVENT_PRIVATE_START + 1)
+#define V4L2_EVENT_REQUEST_DUMPED (V4L2_EVENT_PRIVATE_START + 2)
+
+/* The base for the mediatek camsys driver controls */
+/* We reserve 48 controls for this driver. */
+#define V4L2_CID_USER_MTK_CAM_BASE (V4L2_CID_USER_BASE + 0x10d0)
+
+/* MTK ISP camsys controls */
+#define V4L2_CID_MTK_CAM_USED_ENGINE_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 1)
+#define V4L2_CID_MTK_CAM_BIN_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 2)
+#define V4L2_CID_MTK_CAM_FRZ_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 3)
+#define V4L2_CID_MTK_CAM_RESOURCE_PLAN_POLICY (V4L2_CID_USER_MTK_CAM_BASE + 4)
+#define V4L2_CID_MTK_CAM_USED_ENGINE (V4L2_CID_USER_MTK_CAM_BASE + 5)
+#define V4L2_CID_MTK_CAM_BIN (V4L2_CID_USER_MTK_CAM_BASE + 6)
+#define V4L2_CID_MTK_CAM_FRZ (V4L2_CID_USER_MTK_CAM_BASE + 7)
+#define V4L2_CID_MTK_CAM_USED_ENGINE_TRY (V4L2_CID_USER_MTK_CAM_BASE + 8)
+#define V4L2_CID_MTK_CAM_BIN_TRY (V4L2_CID_USER_MTK_CAM_BASE + 9)
+#define V4L2_CID_MTK_CAM_FRZ_TRY (V4L2_CID_USER_MTK_CAM_BASE + 10)
+#define V4L2_CID_MTK_CAM_PIXEL_RATE (V4L2_CID_USER_MTK_CAM_BASE + 11)
+#define V4L2_CID_MTK_CAM_FEATURE (V4L2_CID_USER_MTK_CAM_BASE + 12)
+#define V4L2_CID_MTK_CAM_SYNC_ID (V4L2_CID_USER_MTK_CAM_BASE + 13)
+#define V4L2_CID_MTK_CAM_RAW_PATH_SELECT (V4L2_CID_USER_MTK_CAM_BASE + 14)
+#define V4L2_CID_MTK_CAM_HSF_EN (V4L2_CID_USER_MTK_CAM_BASE + 15)
+#define V4L2_CID_MTK_CAM_PDE_INFO (V4L2_CID_USER_MTK_CAM_BASE + 16)
+#define V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE (V4L2_CID_USER_MTK_CAM_BASE + 17)
+#define V4L2_CID_MTK_CAM_RAW_RESOURCE_CALC (V4L2_CID_USER_MTK_CAM_BASE + 18)
+#define V4L2_CID_MTK_CAM_TG_FLASH_CFG (V4L2_CID_USER_MTK_CAM_BASE + 19)
+#define V4L2_CID_MTK_CAM_RAW_RESOURCE_UPDATE (V4L2_CID_USER_MTK_CAM_BASE + 20)
+#define V4L2_CID_MTK_CAM_CAMSYS_HW_MODE (V4L2_CID_USER_MTK_CAM_BASE + 21)
+
+/* Luminance+Chrominance formats */
+#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'A') /* 16 YUV 4:2:2 10-bit */
+#define V4L2_PIX_FMT_YVYU10 v4l2_fourcc('Y', 'V', 'Y', 'A') /* 16 YUV 4:2:2 10-bit */
+#define V4L2_PIX_FMT_UYVY10 v4l2_fourcc('U', 'Y', 'V', 'A') /* 16 YUV 4:2:2 10-bit */
+#define V4L2_PIX_FMT_VYUY10 v4l2_fourcc('V', 'Y', 'U', 'A') /* 16 YUV 4:2:2 10-bit */
+#define V4L2_PIX_FMT_YUYV12 v4l2_fourcc('Y', 'U', 'Y', 'C') /* 16 YUV 4:2:2 12-bit */
+#define V4L2_PIX_FMT_YVYU12 v4l2_fourcc('Y', 'V', 'Y', 'C') /* 16 YUV 4:2:2 12-bit */
+#define V4L2_PIX_FMT_UYVY12 v4l2_fourcc('U', 'Y', 'V', 'C') /* 16 YUV 4:2:2 12-bit */
+#define V4L2_PIX_FMT_VYUY12 v4l2_fourcc('V', 'Y', 'U', 'C') /* 16 YUV 4:2:2 12-bit */
+
+/* two planes -- one Y, one Cr + Cb interleaved */
+#define V4L2_PIX_FMT_NV12_10 v4l2_fourcc('1', '2', 'A', 'U') /* 12 Y/CbCr 4:2:0 10 bits un-packed */
+#define V4L2_PIX_FMT_NV21_10 v4l2_fourcc('2', '1', 'A', 'U') /* 12 Y/CrCb 4:2:0 10 bits un-packed */
+#define V4L2_PIX_FMT_NV16_10 v4l2_fourcc('1', '6', 'A', 'U') /* 16 Y/CbCr 4:2:2 10 bits un-packed */
+#define V4L2_PIX_FMT_NV61_10 v4l2_fourcc('6', '1', 'A', 'U') /* 16 Y/CrCb 4:2:2 10 bits un-packed */
+#define V4L2_PIX_FMT_NV12_12 v4l2_fourcc('1', '2', 'C', 'U') /* 12 Y/CbCr 4:2:0 12 bits un-packed */
+#define V4L2_PIX_FMT_NV21_12 v4l2_fourcc('2', '1', 'C', 'U') /* 12 Y/CrCb 4:2:0 12 bits un-packed */
+#define V4L2_PIX_FMT_NV16_12 v4l2_fourcc('1', '6', 'C', 'U') /* 16 Y/CbCr 4:2:2 12 bits un-packed */
+#define V4L2_PIX_FMT_NV61_12 v4l2_fourcc('6', '1', 'C', 'U') /* 16 Y/CrCb 4:2:2 12 bits un-packed */
+
+/* Vendor specific - MediaTek ISP bayer formats */
+#define V4L2_PIX_FMT_MTISP_SBGGR8 v4l2_fourcc('M', 'B', 'B', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG8 v4l2_fourcc('M', 'B', 'G', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG8 v4l2_fourcc('M', 'B', 'g', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB8 v4l2_fourcc('M', 'B', 'R', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR10 v4l2_fourcc('M', 'B', 'B', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG10 v4l2_fourcc('M', 'B', 'G', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG10 v4l2_fourcc('M', 'B', 'g', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB10 v4l2_fourcc('M', 'B', 'R', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR12 v4l2_fourcc('M', 'B', 'B', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG12 v4l2_fourcc('M', 'B', 'G', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG12 v4l2_fourcc('M', 'B', 'g', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB12 v4l2_fourcc('M', 'B', 'R', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR14 v4l2_fourcc('M', 'B', 'B', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG14 v4l2_fourcc('M', 'B', 'G', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG14 v4l2_fourcc('M', 'B', 'g', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB14 v4l2_fourcc('M', 'B', 'R', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR8F v4l2_fourcc('M', 'F', 'B', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG8F v4l2_fourcc('M', 'F', 'G', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG8F v4l2_fourcc('M', 'F', 'g', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB8F v4l2_fourcc('M', 'F', 'R', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR10F v4l2_fourcc('M', 'F', 'B', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG10F v4l2_fourcc('M', 'F', 'G', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG10F v4l2_fourcc('M', 'F', 'g', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB10F v4l2_fourcc('M', 'F', 'R', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR12F v4l2_fourcc('M', 'F', 'B', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG12F v4l2_fourcc('M', 'F', 'G', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG12F v4l2_fourcc('M', 'F', 'g', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB12F v4l2_fourcc('M', 'F', 'R', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR14F v4l2_fourcc('M', 'F', 'B', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG14F v4l2_fourcc('M', 'F', 'G', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG14F v4l2_fourcc('M', 'F', 'g', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB14F v4l2_fourcc('M', 'F', 'R', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGRB8F v4l2_fourcc('M', 'F', '8', 'P') /* three planes Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGRB10F v4l2_fourcc('M', 'F', 'A', 'P') /* three planes Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGRB12F v4l2_fourcc('M', 'F', 'C', 'P') /* three planes Full-G 12-bit */
+
+/* Vendor specific - MediaTek Luminance+Chrominance formats */
+#define V4L2_PIX_FMT_MTISP_YUYV10P v4l2_fourcc('Y', 'U', 'A', 'P') /* YUV 4:2:2 10-bit packed */
+#define V4L2_PIX_FMT_MTISP_YVYU10P v4l2_fourcc('Y', 'V', 'A', 'P') /* YUV 4:2:2 10-bit packed */
+#define V4L2_PIX_FMT_MTISP_UYVY10P v4l2_fourcc('U', 'Y', 'A', 'P') /* YUV 4:2:2 10-bit packed */
+#define V4L2_PIX_FMT_MTISP_VYUY10P v4l2_fourcc('V', 'Y', 'A', 'P') /* YUV 4:2:2 10-bit packed */
+#define V4L2_PIX_FMT_MTISP_NV12_10P v4l2_fourcc('1', '2', 'A', 'P') /* Y/CbCr 4:2:0 10 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV21_10P v4l2_fourcc('2', '1', 'A', 'P') /* Y/CrCb 4:2:0 10 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV16_10P v4l2_fourcc('1', '6', 'A', 'P') /* Y/CbCr 4:2:2 10 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV61_10P v4l2_fourcc('6', '1', 'A', 'P') /* Y/CrCb 4:2:2 10 bits packed */
+#define V4L2_PIX_FMT_MTISP_YUYV12P v4l2_fourcc('Y', 'U', 'C', 'P') /* YUV 4:2:2 12-bit packed */
+#define V4L2_PIX_FMT_MTISP_YVYU12P v4l2_fourcc('Y', 'V', 'C', 'P') /* YUV 4:2:2 12-bit packed */
+#define V4L2_PIX_FMT_MTISP_UYVY12P v4l2_fourcc('U', 'Y', 'C', 'P') /* YUV 4:2:2 12-bit packed */
+#define V4L2_PIX_FMT_MTISP_VYUY12P v4l2_fourcc('V', 'Y', 'C', 'P') /* YUV 4:2:2 12-bit packed */
+#define V4L2_PIX_FMT_MTISP_NV12_12P v4l2_fourcc('1', '2', 'C', 'P') /* Y/CbCr 4:2:0 12 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV21_12P v4l2_fourcc('2', '1', 'C', 'P') /* Y/CrCb 4:2:0 12 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV16_12P v4l2_fourcc('1', '6', 'C', 'P') /* Y/CbCr 4:2:2 12 bits packed */
+#define V4L2_PIX_FMT_MTISP_NV61_12P v4l2_fourcc('6', '1', 'C', 'P') /* Y/CrCb 4:2:2 12 bits packed */
+
+/* Vendor specific - MediaTek specified compressed format */
+#define V4L2_PIX_FMT_MTISP_NV12_UFBC v4l2_fourcc('1', '2', '8', 'F') /* Y/CbCr 4:2:0 8 bits compressed */
+#define V4L2_PIX_FMT_MTISP_NV21_UFBC v4l2_fourcc('2', '1', '8', 'F') /* Y/CrCb 4:2:0 8 bits compressed */
+#define V4L2_PIX_FMT_MTISP_NV12_10_UFBC v4l2_fourcc('1', '2', 'A', 'F') /* Y/CbCr 4:2:0 10 bits compressed */
+#define V4L2_PIX_FMT_MTISP_NV21_10_UFBC v4l2_fourcc('2', '1', 'A', 'F') /* Y/CrCb 4:2:0 10 bits compressed */
+#define V4L2_PIX_FMT_MTISP_NV12_12_UFBC v4l2_fourcc('1', '2', 'C', 'F') /* Y/CbCr 4:2:0 12 bits compressed */
+#define V4L2_PIX_FMT_MTISP_NV21_12_UFBC v4l2_fourcc('2', '1', 'C', 'F') /* Y/CrCb 4:2:0 12 bits compressed */
+#define V4L2_PIX_FMT_MTISP_BAYER8_UFBC v4l2_fourcc('M', 'B', '8', 'U') /* Raw 8 bits compressed */
+#define V4L2_PIX_FMT_MTISP_BAYER10_UFBC v4l2_fourcc('M', 'B', 'A', 'U') /* Raw 10 bits compressed */
+#define V4L2_PIX_FMT_MTISP_BAYER12_UFBC v4l2_fourcc('M', 'B', 'C', 'U') /* Raw 12 bits compressed */
+#define V4L2_PIX_FMT_MTISP_BAYER14_UFBC v4l2_fourcc('M', 'B', 'E', 'U') /* Raw 14 bits compressed */
+
+/* Vendor specific - MediaTek ISP parameters for firmware */
+#define V4L2_META_FMT_MTISP_3A v4l2_fourcc('M', 'T', 'f', 'a') /* AE/AWB histogram */
+#define V4L2_META_FMT_MTISP_AF v4l2_fourcc('M', 'T', 'f', 'f') /* AF histogram */
+#define V4L2_META_FMT_MTISP_LCS v4l2_fourcc('M', 'T', 'f', 'c') /* Local contrast enhanced statistics */
+#define V4L2_META_FMT_MTISP_LMV v4l2_fourcc('M', 'T', 'f', 'm') /* Local motion vector histogram */
+#define V4L2_META_FMT_MTISP_PARAMS v4l2_fourcc('M', 'T', 'f', 'p') /* ISP tuning parameters */
+
+/*
+ * struct mtk_cam_resource_sensor - sensor resoruces for format negotiation
+ *
+ */
+struct mtk_cam_resource_sensor {
+ struct v4l2_fract interval;
+ __u32 hblank;
+ __u32 vblank;
+ __u64 pixel_rate;
+ __u64 cust_pixel_rate;
+};
+
+/*
+ * struct mtk_cam_resource_raw - MTK camsys raw resoruces for format negotiation
+ *
+ * @feature: value of V4L2_CID_MTK_CAM_FEATURE the user want to check the
+ * resource with. If it is used in set CTRL, we will apply the value
+ * to V4L2_CID_MTK_CAM_FEATURE ctrl directly.
+ * @strategy: indicate the order of multiple raws, binning or DVFS to be selected
+ * when doing format negotiation of raw's source pads (output pads).
+ * Please pass MTK_CAM_RESOURCE_DEFAULT if you want camsys driver to
+ * determine it.
+ * @raw_max: indicate the max number of raw to be used for the raw pipeline.
+ * Please pass MTK_CAM_RESOURCE_DEFAULT if you want camsys driver to
+ * determine it.
+ * @raw_min: indicate the max number of raw to be used for the raw pipeline.
+ * Please pass MTK_CAM_RESOURCE_DEFAULT if you want camsys driver to
+ * determine it.
+ * @raw_used: The number of raw used. The used don't need to writ this failed,
+ * the driver always updates the field.
+ * @bin: indicate if the driver should enable the bining or not. The driver
+ * update the field depanding the hardware supporting status. Please pass
+ * MTK_CAM_RESOURCE_DEFAULT if you want camsys driver to determine it.
+ * @path_sel: indicate the user selected raw path. The driver
+ * update the field depanding the hardware supporting status. Please
+ * pass MTK_CAM_RESOURCE_DEFAULT if you want camsys driver to
+ * determine it.
+ * @pixel_mode: the pixel mode driver used in the raw pipeline. It is written by
+ * driver only.
+ * @throughput: the throughput be used in the raw pipeline. It is written by
+ * driver only.
+ *
+ */
+struct mtk_cam_resource_raw {
+ __s64 feature;
+ __u16 strategy;
+ __u8 raw_max;
+ __u8 raw_min;
+ __u8 raw_used;
+ __u8 bin;
+ __u8 path_sel;
+ __u8 pixel_mode;
+ __u64 throughput;
+};
+
+/*
+ * struct mtk_cam_resource - MTK camsys resoruces for format negotiation
+ *
+ * @sink_fmt: sink_fmt pad's format, it must be return by g_fmt or s_fmt
+ * from driver.
+ * @sensor_res: senor information to calculate the required resource, it is
+ * read-only and camsys driver will not change it.
+ * @raw_res: user hint and resource negotiation result.
+ * @status: resource negotiation status.
+ *
+ */
+struct mtk_cam_resource {
+ __u64 sink_fmt;
+ struct mtk_cam_resource_sensor sensor_res;
+ struct mtk_cam_resource_raw raw_res;
+ __u8 status;
+};
+
+/**
+ * struct mtk_cam_pde_info - PDE module information for raw
+ *
+ * @pdo_max_size: the max pdo size of pde sensor.
+ * @pdi_max_size: the max pdi size of pde sensor or max pd table size.
+ * @pd_table_offset: the offest of meta config for pd table content.
+ */
+struct mtk_cam_pde_info {
+ __u32 pdo_max_size;
+ __u32 pdi_max_size;
+ __u32 pd_table_offset;
+};
+#endif /* _MTKISP_CAMSYS_USER_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 88+ messages in thread
* Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-09 12:50 ` AngeloGioacchino Del Regno
2024-10-11 1:36 ` CK Hu (胡俊光)
` (3 subsequent siblings)
4 siblings, 0 replies; 88+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-10-09 12:50 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Sumit Semwal,
Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
Il 09/10/24 13:15, Shu-hsiang Yang ha scritto:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 ++++++
> .../mtk_cam-seninf-csi0-cphy.h | 69 +
> .../mtk_cam-seninf-csi0-dphy.h | 139 +
> .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++++++++++
> .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 ++
> .../mtk_cam-seninf-seninf1-csi2.h | 415 +++
> .../mtk_cam-seninf-seninf1-mux.h | 147 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 +
> 11 files changed, 5017 insertions(+)
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
The PHY driver should go to the PHY directory as a PHY driver - or at least
part of this mtk_csi_phy_2_0 driver should go there.
I see that this is tightly integrated with the rest of the code in seninf,
but there seems to be many functions that are just handling a "real" PHY.
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h
>
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
> new file mode 100644
> index 000000000000..e00b8d3904a9
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (C) 2022 MediaTek Inc.
> +
> +mtk-cam-isp-objs += \
> + mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.o
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
> new file mode 100644
> index 000000000000..ec3c621d742a
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
> @@ -0,0 +1,911 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + */
> +
> +#ifndef __SENINF_CAM_MUX_H__
> +#define __SENINF_CAM_MUX_H__
> +
> +#define SENINF_CAM_MUX_CTRL_0 0x0000
> +#define RG_SENINF_CAM_MUX0_SRC_SEL_SHIFT 0
> +#define RG_SENINF_CAM_MUX0_SRC_SEL_MASK (0xf << 0)
For all definitions: drop _SHIFT and use the GENMASK(x,y) macro.
#define RG_SENINF_CAM_MUX0_SRC_SEL GENMASK(7, 0)
#define RG_SENINF_CAM_MUX1_SRC_SEL GENMASK(11, 8)
etc.
> +#define RG_SENINF_CAM_MUX1_SRC_SEL_SHIFT 8
> +#define RG_SENINF_CAM_MUX1_SRC_SEL_MASK (0xf << 8)
> +#define RG_SENINF_CAM_MUX2_SRC_SEL_SHIFT 16
> +#define RG_SENINF_CAM_MUX2_SRC_SEL_MASK (0xf << 16)
> +#define RG_SENINF_CAM_MUX3_SRC_SEL_SHIFT 24
> +#define RG_SENINF_CAM_MUX3_SRC_SEL_MASK (0xf << 24)
..snip..
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
> new file mode 100644
> index 000000000000..f24d8a056d0e
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
> @@ -0,0 +1,2879 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2022 MediaTek Inc.
> +
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +
> +#include "../mtk_cam-seninf.h"
> +#include "../mtk_cam-seninf-hw.h"
> +#include "../mtk_cam-seninf-regs.h"
> +#include "mtk_cam-seninf-top-ctrl.h"
> +#include "mtk_cam-seninf-seninf1-mux.h"
> +#include "mtk_cam-seninf-seninf1.h"
> +#include "mtk_cam-seninf-seninf1-csi2.h"
> +#include "mtk_cam-seninf-tg1.h"
> +#include "mtk_cam-seninf-cammux.h"
> +#include "mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h"
> +#include "mtk_cam-seninf-csi0-cphy.h"
> +#include "mtk_cam-seninf-csi0-dphy.h"
> +#include "../kd_imgsensor_define_v4l2.h"
> +
> +/* seninf cfg default, dts may override */
dts may override: for which reason? Why should DT override that? For which usecase?
> +static struct mtk_cam_seninf_cfg _seninf_cfg = {
> + .mux_num = 8,
> + .seninf_num = 4,
> + .cam_mux_num = 11,
> + .pref_mux_num = 11,
> +};
> +
> +struct mtk_cam_seninf_cfg *g_seninf_cfg = &_seninf_cfg;
That's unused. Drop.
> +
> +static inline void mtk_cam_seninf_set_di_ch_ctrl(void __iomem *pseninf,
> + unsigned int stream_id,
> + struct seninf_vc *vc)
> +{
> + if (stream_id > 7)
No magic numbers, please.
#define SOMETHING 7
> + return;
> +
> + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2),
Is it me, or is SENINF_BITS() not defined?!
> + RG_CSI2_DT_SEL, vc->dt);
> + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2),
> + RG_CSI2_VC_SEL, vc->vc);
> + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2),
> + RG_CSI2_DT_INTERLEAVE_MODE, 1);
> + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2),
> + RG_CSI2_VC_INTERLEAVE_EN, 1);
> +
..snip..
> +}
> +
> +int mtk_cam_seninf_init_iomem(struct seninf_ctx *ctx, void __iomem *if_base,
> + void __iomem *ana_base)
> +{
> + u32 i;
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_0] =
Please don't use "a = b = c" assignments. In this case, that impacts on human
readability.
> + ctx->reg_ana_csi_rx[CSI_PORT_0A] = ana_base + 0;
> + ctx->reg_ana_csi_rx[CSI_PORT_0B] = ana_base + 0x1000;
Again, no magic numbers please.
#define SOMETHING 0x1000
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_1] =
> + ctx->reg_ana_csi_rx[CSI_PORT_1A] = ana_base + 0x4000;
> + ctx->reg_ana_csi_rx[CSI_PORT_1B] = ana_base + 0x5000;
..snip..
> + return 0;
> +}
> +
> +int mtk_cam_seninf_init_port(struct seninf_ctx *ctx, int port)
> +{
> + u32 port_num;
> +
> + if (port >= CSI_PORT_0A)
> + port_num = (port - CSI_PORT_0) >> 1;
I think that you really want to use bitfield.h macros to simplify this.
> + else
> + port_num = port;
> +
> + ctx->port = port;
> + ctx->port_num = port_num;
> + ctx->port_a = CSI_PORT_0A + (port_num << 1);
> + ctx->port_b = ctx->port_a + 1;
> + ctx->is_4d1c = (port == port_num);
> +
> + switch (port) {
> + case CSI_PORT_0:
> + ctx->seninf_idx = SENINF_1;
Is the CSI port to SENINF mapping supposed to be static and unchangeable?
If yes, then you want to add that into an array indexed by CSI_PORT_xx,
so that you end up doing
ctx->seninf_idx = seninf_csi[port];
> + break;
> + case CSI_PORT_0A:
> + ctx->seninf_idx = SENINF_1;
> + break;
> + case CSI_PORT_0B:
> + ctx->seninf_idx = SENINF_2;
> + break;
> + case CSI_PORT_1:
> + ctx->seninf_idx = SENINF_3;
> + break;
> + case CSI_PORT_1A:
> + ctx->seninf_idx = SENINF_3;
> + break;
> + case CSI_PORT_1B:
> + ctx->seninf_idx = SENINF_4;
> + break;
> + case CSI_PORT_2:
> + ctx->seninf_idx = SENINF_5;
> + break;
> + case CSI_PORT_2A:
> + ctx->seninf_idx = SENINF_5;
> + break;
> + case CSI_PORT_2B:
> + ctx->seninf_idx = SENINF_6;
> + break;
> + case CSI_PORT_3:
> + ctx->seninf_idx = SENINF_7;
> + break;
> + case CSI_PORT_3A:
> + ctx->seninf_idx = SENINF_7;
> + break;
> + case CSI_PORT_3B:
> + ctx->seninf_idx = SENINF_8;
> + break;
> + default:
> + dev_dbg(ctx->dev, "invalid port %d\n", port);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_is_cammux_used(struct seninf_ctx *ctx, int cam_mux)
> +{
> + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux;
> + u32 temp = SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN);
Please, just use readl() or regmap_read() (preferrably the latter, and preferrably
also define regmap reg fields).
> +
> + if (cam_mux >= _seninf_cfg.cam_mux_num) {
> + dev_dbg(ctx->dev,
> + "%s err cam_mux %d >= SENINF_CAM_MUX_NUM %d\n",
> + __func__, cam_mux, _seninf_cfg.cam_mux_num);
That shouldn't ever happen, should it. In that case, it's dev_err(), or even a
WARN(), if necessary.
> +
> + return 0;
> + }
> +
> + return !!(temp & (1 << cam_mux));
> +}
> +
> +int mtk_cam_seninf_cammux(struct seninf_ctx *ctx, int cam_mux)
> +{
> + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux;
> + u32 temp;
> +
> + if (cam_mux >= _seninf_cfg.cam_mux_num) {
This check is duplicated across many functions... you want to do something such
that it either never happens or it gets commonized.
> + dev_dbg(ctx->dev,
> + "%s err cam_mux %d >= SENINF_CAM_MUX_NUM %d\n",
> + __func__, cam_mux, _seninf_cfg.cam_mux_num);
> +
> + return 0;
You return 0, so there's no problem if this is the wrong cam_mux?!?!?
> + }
> +
> + temp = SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN);
> + SENINF_WRITE_REG(seninf_cam_mux, SENINF_CAM_MUX_EN,
> + temp | (1 << cam_mux));
BIT(cam_mux)
> +
> + SENINF_WRITE_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_STATUS,
> + 3 << (cam_mux * 2)); /* clr irq */
> +
> + dev_dbg(ctx->dev, "cam_mux %d EN 0x%x IRQ_EN 0x%x IRQ_STATUS 0x%x\n",
> + cam_mux, SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN),
> + SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_EN),
> + SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_STATUS));
> +
> + return 0;
> +}
> +
> +
> +int mtk_cam_seninf_set_vc(struct seninf_ctx *ctx, u32 seninf_idx,
> + struct seninf_vcinfo *vcinfo)
> +{
> + void __iomem *seninf_csi2 = ctx->reg_if_csi2[seninf_idx];
> + int i;
> + struct seninf_vc *vc;
> +
> + if (!vcinfo || !vcinfo->cnt)
> + return 0;
Does !vcinfo mean that Virtual Channel should not be set?
Please add a comment explaining that.
> +
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S0_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S1_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S2_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S3_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S4_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S5_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S6_DI_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S7_DI_CTRL, 0);
> +
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH0_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH1_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH2_CTRL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH3_CTRL, 0);
> +
> + for (i = 0; i < vcinfo->cnt; i++) {
> + vc = &vcinfo->vc[i];
> +
> + /* General Long Packet Data Types: 0x10-0x17 */
> + if (vc->dt >= 0x10 && vc->dt <= 0x17) {
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT,
> + RG_CSI2_GENERIC_LONG_PACKET_EN, 1);
> + }
> +
> + mtk_cam_seninf_set_di_ch_ctrl(seninf_csi2, i, vc);
> + }
> +
> + dev_dbg(ctx->dev, "DI_CTRL 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S0_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S1_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S2_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S3_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S4_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S5_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S6_DI_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S7_DI_CTRL));
> +
> + dev_dbg(ctx->dev, "CH_CTRL 0x%x 0x%x 0x%x 0x%x\n",
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH0_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH1_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH2_CTRL),
> + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH3_CTRL));
> +
> + return 0;
> +}
> +
..snip..
> +
> +static int csirx_phyA_power_on(struct seninf_ctx *ctx, u32 port_idx, int en)
Please, lower case on all functions. csirx_phy_a_power_on().
Also, you want to split this function in two: one should be csirx_phy_a_power_off()
and one for power_on().
static void csirx_phy_a_power_off(struct seninf_ctx *ctx, u32 port_idx)
{
> +{
> + void __iomem *base = ctx->reg_ana_csi_rx[port_idx];
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L0_T0AB_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L1_T1AB_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L2_T1BC_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T0BC_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T0CA_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T1CA_EQ_OS_CAL_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0, RG_CSI0_BG_LPF_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0, RG_CSI0_BG_CORE_EN, 0);
> + usleep_range(200, 300);
> +
}
static int csirx_phy_a_power_on(struct seninf_ctx *ctx, u32 port_idx) <-- NO int en
{
void *iomem base = .....
/* Power it off first to ... reset, I believe? */
csirx_phy_a_power_off();
power on sequence here
return 0;
}
> + if (en) {
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_BG_CORE_EN, 1);
> + usleep_range(30, 40);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_BG_LPF_EN, 1);
> + udelay(1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_L0_T0AB_EQ_OS_CAL_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_L1_T1AB_EQ_OS_CAL_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_L2_T1BC_EQ_OS_CAL_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_XX_T0BC_EQ_OS_CAL_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_XX_T0CA_EQ_OS_CAL_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_8,
> + RG_CSI0_XX_T1CA_EQ_OS_CAL_EN, 1);
> + udelay(1);
> + }
> +
> + return 0;
> +}
> +
> +static int apply_efuse_data(struct seninf_ctx *ctx)
> +{
void __iomem *base;
u32 m_csi_efuse = ctx->m_csi_efuse;
u32 port;
int ret;
> + int ret = 0;
> + void __iomem *base;
> + u32 port;
> + u32 m_csi_efuse = ctx->m_csi_efuse;
> +
> + if (m_csi_efuse == 0) {
> + dev_dbg(ctx->dev, "No efuse data. Returned.\n");
> + return -1;
> + }
..snip..
> +
> + return ret;
return 0;
> +}
> +
> +static int csirx_phyA_init(struct seninf_ctx *ctx)
> +{
> + u32 i, port;
> + void __iomem *base;
> +
> + port = ctx->port;
> + for (i = 0; i <= ctx->is_4d1c; i++) {
Move the setup in a different function, then call it with
something(port);
if (is_4d1c)
something(port_b);
> + port = i ? ctx->port_b : ctx->port;
> + base = ctx->reg_ana_csi_rx[port];
> + SENINF_BITS(base, CDPHY_RX_ANA_1,
> + RG_CSI0_BG_LPRX_VTL_SEL, 0x4);
> + SENINF_BITS(base, CDPHY_RX_ANA_1,
> + RG_CSI0_BG_LPRX_VTH_SEL, 0x4);
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_BG_ALP_RX_VTL_SEL, 0x4);
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_BG_ALP_RX_VTH_SEL, 0x4);
> + SENINF_BITS(base, CDPHY_RX_ANA_1,
> + RG_CSI0_BG_VREF_SEL, 0x8);
> + SENINF_BITS(base, CDPHY_RX_ANA_1,
> + RG_CSI0_CDPHY_EQ_DES_VREF_SEL, 0x2);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_9,
> + RG_CSI0_RESERVE, 0x3003);
> + SENINF_BITS(base, CDPHY_RX_ANA_SETTING_0,
> + CSR_CSI_RST_MODE, 0x2);
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_L0P_T0A_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_L0N_T0B_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_3,
> + RG_CSI0_L1P_T0C_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_3,
> + RG_CSI0_L1N_T1A_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_4,
> + RG_CSI0_L2P_T1B_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_4,
> + RG_CSI0_L2N_T1C_HSRT_CODE, 0x10);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_T0_CDR_FIRST_EDGE_EN, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_T1_CDR_FIRST_EDGE_EN, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_CPHY_T0_CDR_SELF_CAL_EN, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_2,
> + RG_CSI0_CPHY_T1_CDR_SELF_CAL_EN, 0x0);
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_6,
> + RG_CSI0_CPHY_T0_CDR_CK_DELAY, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_7,
> + RG_CSI0_CPHY_T1_CDR_CK_DELAY, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_6,
> + RG_CSI0_CPHY_T0_CDR_AB_WIDTH, 0x9);
> + SENINF_BITS(base, CDPHY_RX_ANA_6,
> + RG_CSI0_CPHY_T0_CDR_BC_WIDTH, 0x9);
> + SENINF_BITS(base, CDPHY_RX_ANA_6,
> + RG_CSI0_CPHY_T0_CDR_CA_WIDTH, 0x9);
> + SENINF_BITS(base, CDPHY_RX_ANA_7,
> + RG_CSI0_CPHY_T1_CDR_AB_WIDTH, 0x9);
> + SENINF_BITS(base, CDPHY_RX_ANA_7,
> + RG_CSI0_CPHY_T1_CDR_BC_WIDTH, 0x9);
> + SENINF_BITS(base, CDPHY_RX_ANA_7,
> + RG_CSI0_CPHY_T1_CDR_CA_WIDTH, 0x9);
> +
> + dev_dbg(ctx->dev, "port:%d CDPHY_RX_ANA_0(0x%x)\n",
> + port, SENINF_READ_REG(base, CDPHY_RX_ANA_0));
> + }
> +
> + apply_efuse_data(ctx);
> +
> + return 0;
> +}
> +
> +static int csirx_dphy_init(struct seninf_ctx *ctx)
> +{
> + void __iomem *base = ctx->reg_ana_dphy_top[ctx->port];
> + int settle_delay_dt, settle_delay_ck, hs_trail, hs_trail_en;
> + int bit_per_pixel;
u8 bits_per_pixel;
> + u64 data_rate;
> +
> + settle_delay_dt = ctx->is_cphy ? ctx->core->cphy_settle_delay_dt :
> + ctx->core->dphy_settle_delay_dt;
Please set settle_delay_ck and hs_trail here.
> +
> + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER,
> + settle_delay_dt);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER,
> + RG_CDPHY_RX_LD1_TRIO1_HS_SETTLE_PARAMETER,
> + settle_delay_dt);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER,
> + RG_CDPHY_RX_LD2_TRIO2_HS_SETTLE_PARAMETER,
> + settle_delay_dt);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER,
> + RG_CDPHY_RX_LD3_TRIO3_HS_SETTLE_PARAMETER,
> + settle_delay_dt);
> +
> + settle_delay_ck = ctx->core->settle_delay_ck;
> +
> + SENINF_BITS(base, DPHY_RX_CLOCK_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER,
> + settle_delay_ck);
> + SENINF_BITS(base, DPHY_RX_CLOCK_LANE1_HS_PARAMETER,
> + RG_DPHY_RX_LC1_HS_SETTLE_PARAMETER,
> + settle_delay_ck);
> +
> + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_PARAMETER, 2);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER,
> + RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_PARAMETER, 2);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER,
> + RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_PARAMETER, 2);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER,
> + RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_PARAMETER, 2);
> +
> + hs_trail = ctx->hs_trail_parameter;
> +
> + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER, hs_trail);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER,
> + RG_DPHY_RX_LD1_HS_TRAIL_PARAMETER, hs_trail);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER,
> + RG_DPHY_RX_LD2_HS_TRAIL_PARAMETER, hs_trail);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER,
> + RG_DPHY_RX_LD3_HS_TRAIL_PARAMETER, hs_trail);
> +
> + if (!ctx->is_cphy) {
> + bit_per_pixel = 10;
data_rate = ctx->customized_pixel_rate ?
ctx->customized_pixel_rate : ctx->mipi_pixel_rate;
data_rate *= bits_per_pixel;
> + if (ctx->customized_pixel_rate != 0)
> + data_rate = ctx->customized_pixel_rate * bit_per_pixel;
> + else
> + data_rate = ctx->mipi_pixel_rate * bit_per_pixel;
> +
> + do_div(data_rate, ctx->num_data_lanes);
> + hs_trail_en = data_rate < 1400000000;
> + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LD0_HS_TRAIL_EN, hs_trail_en);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER,
> + RG_DPHY_RX_LD1_HS_TRAIL_EN, hs_trail_en);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER,
> + RG_DPHY_RX_LD2_HS_TRAIL_EN, hs_trail_en);
> + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER,
> + RG_DPHY_RX_LD3_HS_TRAIL_EN, hs_trail_en);
> + }
> +
> + return 0;
> +}
> +
> +static int csirx_cphy_init(struct seninf_ctx *ctx)
> +{
> + void __iomem *base = ctx->reg_ana_cphy_top[ctx->port];
> +
> + SENINF_BITS(base, CPHY_RX_DETECT_CTRL_POST,
> + RG_CPHY_RX_DATA_VALID_POST_EN, 1);
> +
> + return 0;
> +}
> +
> +static int csirx_phy_init(struct seninf_ctx *ctx)
> +{
> + csirx_phyA_init(ctx);
> +
> + csirx_dphy_init(ctx);
> + csirx_cphy_init(ctx);
> +
> + return 0;
> +}
> +
> +static int csirx_seninf_csi2_setting(struct seninf_ctx *ctx)
> +{
> + void __iomem *seninf_csi2 = ctx->reg_if_csi2[ctx->seninf_idx];
> + int csi_en;
> +
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_DBG_CTRL,
> + RG_CSI2_DBG_PACKET_CNT_EN, 1);
> +
> + /* lane/trio count */
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_RESYNC_MERGE_CTRL,
> + RG_CSI2_RESYNC_CYCLE_CNT_OPT, 1);
> +
> + csi_en = (1 << ctx->num_data_lanes) - 1;
csi_en = BIT(ctx->num_data_lanes) - 1;
or
csi_en = GENMASK(ctx->num_data_lanes - 1, 0);
> +
> + if (!ctx->is_cphy) {
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT, RG_CSI2_CPHY_SEL, 0);
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, csi_en);
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0,
> + RG_CSI2_HEADER_MODE, 0);
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0,
> + RG_CSI2_HEADER_LEN, 0);
> + } else {
> + u8 map_hdr_len[] = {0, 1, 2, 4, 5};
u8 map_hdr_len[] = { 0, 1, 2, 4, 5 };
> +
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, csi_en);
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT,
> + RG_CSI2_CPHY_SEL, 1);
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0,
> + RG_CSI2_HEADER_MODE, 2);
> + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0,
> + RG_CSI2_HEADER_LEN,
> + map_hdr_len[ctx->num_data_lanes]);
> + }
> +
> + return 0;
> +}
> +
> +static int csirx_seninf_setting(struct seninf_ctx *ctx)
> +{
> + void __iomem *seninf = ctx->reg_if_ctrl[ctx->seninf_idx];
> +
> + /* enable/disable seninf csi2 */
> + SENINF_BITS(seninf, SENINF_CSI2_CTRL, RG_SENINF_CSI2_EN, 1);
> +
> + /* enable/disable seninf, enable after csi2, testmdl is done */
> + SENINF_BITS(seninf, SENINF_CTRL, SENINF_EN, 1);
> +
> + return 0;
> +}
> +
> +static int csirx_seninf_top_setting(struct seninf_ctx *ctx)
> +{
..snip..
> +
> + /* port operation mode */
> + switch (ctx->port) {
> + case CSI_PORT_0:
> + case CSI_PORT_0A:
> + case CSI_PORT_0B:
reg = TOP_PHY_CTRL_CSI0;
field_cphy = PHY_SENINF_MUX0_CPHY_EN;
field_dphy = PHY_SENINF_MUX0_DPHY_EN;
break;
case CSI_PORT_1:
case CSI_PORT_1A:
case CSI_PORT_1B:
reg = TOP_PHY_CTRL_CSI1;
field_cphy = PHY_SENINF_MUX1_CPHY_EN;
field_dphy = PHY_SENINF_MUX1_DPHY_EN;
break;
.... etc
}
regmap_write_bits(regmap, reg, field_cphy, ctx->is_cphy);
regmap_write_bits(regmap, reg, field_dphy, !ctx->is_cphy);
> + if (!ctx->is_cphy) {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0,
> + PHY_SENINF_MUX0_CPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0,
> + PHY_SENINF_MUX0_DPHY_EN, 1);
> + } else {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0,
> + PHY_SENINF_MUX0_DPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0,
> + PHY_SENINF_MUX0_CPHY_EN, 1);
> + }
> + break;
> + case CSI_PORT_1:
> + case CSI_PORT_1A:
> + case CSI_PORT_1B:
> + if (!ctx->is_cphy) {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1,
> + PHY_SENINF_MUX1_CPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1,
> + PHY_SENINF_MUX1_DPHY_EN, 1);
> + } else {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1,
> + PHY_SENINF_MUX1_DPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1,
> + PHY_SENINF_MUX1_CPHY_EN, 1);
> + }
> + break;
> + case CSI_PORT_2:
> + case CSI_PORT_2A:
> + case CSI_PORT_2B:
> + if (!ctx->is_cphy) {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2,
> + PHY_SENINF_MUX2_CPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2,
> + PHY_SENINF_MUX2_DPHY_EN, 1);
> + } else {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2,
> + PHY_SENINF_MUX2_DPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2,
> + PHY_SENINF_MUX2_CPHY_EN, 1);
> + }
> + break;
> + case CSI_PORT_3:
> + case CSI_PORT_3A:
> + case CSI_PORT_3B:
> + if (!ctx->is_cphy) {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3,
> + PHY_SENINF_MUX3_CPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3,
> + PHY_SENINF_MUX3_DPHY_EN, 1);
> + } else {
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3,
> + PHY_SENINF_MUX3_DPHY_EN, 0);
> + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3,
> + PHY_SENINF_MUX3_CPHY_EN, 1);
> + }
> + break;
> + default:
> + break;
So if this is called with a CSI_PORT that is out of range, we're not
erroring out?!?!
> + }
> +
> + return 0;
> +}
> +
> +static int csirx_phyA_setting(struct seninf_ctx *ctx)
> +{
> + void __iomem *base, *baseA, *baseB;
> +
> + base = ctx->reg_ana_csi_rx[ctx->port];
> + baseA = ctx->reg_ana_csi_rx[ctx->port_a];
> + baseB = ctx->reg_ana_csi_rx[ctx->port_b];
> +
> + if (!ctx->is_cphy) { /* dphy */
For this huge register write sequence, you want to split it in at least
two functions to improve human readability and reduce indentation.
> + if (ctx->is_4d1c) {
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 0);
> + /* clear clk sel first */
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 0);
> +
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKSEL, 1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKSEL, 1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKSEL, 1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKSEL, 1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKSEL, 1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKSEL, 1);
> +
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 0);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 0);
> +
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> +
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> + } else {
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 0);
> + /* clear clk sel first */
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 0);
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKSEL, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKSEL, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKSEL, 0);
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L0_CKMODE_EN, 0);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L1_CKMODE_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_DPHY_L2_CKMODE_EN, 0);
> +
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> + }
> + } else { /* cphy */
> + if (ctx->is_4d1c) {
> + SENINF_BITS(baseA, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 1);
> + SENINF_BITS(baseB, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 1);
> +
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x3);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> +
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x3);
> + SENINF_BITS(baseA, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> + } else {
> + SENINF_BITS(base, CDPHY_RX_ANA_0,
> + RG_CSI0_CPHY_EN, 1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_BW, 0x3);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_IS, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR0, 0x3);
> + SENINF_BITS(base, CDPHY_RX_ANA_5,
> + RG_CSI0_CDPHY_EQ_SR1, 0x0);
> + }
> + }
> +
> + /* phyA power on */
> + if (ctx->is_4d1c) {
> + csirx_phyA_power_on(ctx, ctx->port_a, 1);
> + csirx_phyA_power_on(ctx, ctx->port_b, 1);
> + } else {
> + csirx_phyA_power_on(ctx, ctx->port, 1);
> + }
> +
> + return 0;
> +}
> +
> +static int csirx_dphy_setting(struct seninf_ctx *ctx)
> +{
> + void __iomem *base = ctx->reg_ana_dphy_top[ctx->port];
> +
> + if (ctx->is_4d1c) {
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD3_SEL, 4);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD2_SEL, 0);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD1_SEL, 3);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD0_SEL, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC0_SEL, 2);
> +
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD0_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD1_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD2_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD3_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC0_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC1_EN, 0);
> + } else {
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD3_SEL, 5);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD2_SEL, 3);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD1_SEL, 2);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD0_SEL, 0);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC1_SEL, 4);
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC0_SEL, 1);
> +
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD0_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD1_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD2_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD3_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC0_EN, 1);
> + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC1_EN, 1);
> + }
> +
> + SENINF_BITS(base, DPHY_RX_LANE_SELECT, DPHY_RX_CK_DATA_MUX_EN, 1);
> +
> + return 0;
> +}
> +
> +static int csirx_cphy_setting(struct seninf_ctx *ctx)
> +{
> + void __iomem *base = ctx->reg_ana_cphy_top[ctx->port];
u32 reg_lprx[] = { CPHY_RX_TR0_LPRX_EN, CPHY_RX_TR1_LPRX_EN, ...TR2, ...TR3 };
> +
> + switch (ctx->port) {
> + case CSI_PORT_0:
> + case CSI_PORT_1:
> + case CSI_PORT_2:
> + case CSI_PORT_3:
> + case CSI_PORT_0A:
> + case CSI_PORT_1A:
> + case CSI_PORT_2A:
> + case CSI_PORT_3A:
for (i = 0; i < ctx->num_data_lanes; i++)
regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 1);
for (; i < ARRAY_SIZE(reg_lprx); i++)
regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 0);
> + if (ctx->num_data_lanes == 3) {
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1);
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR1_LPRX_EN, 1);
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1);
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR3_LPRX_EN, 0);
> + } else if (ctx->num_data_lanes == 2) {
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1);
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR1_LPRX_EN, 1);
> + } else {
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1);
> + }
> + break;
> + case CSI_PORT_0B:
> + case CSI_PORT_1B:
> + case CSI_PORT_2B:
> + case CSI_PORT_3B:
for (i = 0; i < ctx->num_data_lanes; i++) {
regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 0);
regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i+2], 1);
}
> + if (ctx->num_data_lanes == 2) {
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1);
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR3_LPRX_EN, 1);
> + } else {
> + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1);
> + }
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int csirx_phy_setting(struct seninf_ctx *ctx)
> +{
> + csirx_phyA_setting(ctx);
> +
Please,
if (ctx->is_cphy)
x()
else
y()
> + if (!ctx->is_cphy)
> + csirx_dphy_setting(ctx);
> + else
> + csirx_cphy_setting(ctx);
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_set_csi_mipi(struct seninf_ctx *ctx)
> +{
> + csirx_phy_init(ctx);
> +
> + /* seninf csi2 */
> + csirx_seninf_csi2_setting(ctx);
> +
> + /* seninf */
> + csirx_seninf_setting(ctx);
> +
> + /* seninf top */
> + csirx_seninf_top_setting(ctx);
> +
> + /* phy */
> + csirx_phy_setting(ctx);
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_poweroff(struct seninf_ctx *ctx)
> +{
> + void __iomem *seninf_csi2;
> +
> + seninf_csi2 = ctx->reg_if_csi2[ctx->seninf_idx];
> +
> + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, 0x0);
> +
> + if (ctx->is_4d1c) {
> + csirx_phyA_power_on(ctx, ctx->port_a, 0);
> + csirx_phyA_power_on(ctx, ctx->port_b, 0);
> + } else {
> + csirx_phyA_power_on(ctx, ctx->port, 0);
> + }
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_reset(struct seninf_ctx *ctx, u32 seninf_idx)
> +{
> + int i;
> + void __iomem *seninf_mux;
> + void __iomem *seninf = ctx->reg_if_ctrl[seninf_idx];
> +
> + SENINF_BITS(seninf, SENINF_CSI2_CTRL, SENINF_CSI2_SW_RST, 1);
What about adding a reset controller that includes SENINF_CSI(x)_SW_RST?
Also, why are you resetting only CSI2 and not the others?
> + udelay(1);
> + SENINF_BITS(seninf, SENINF_CSI2_CTRL, SENINF_CSI2_SW_RST, 0);
> +
> + dev_dbg(ctx->dev, "reset seninf %d\n", seninf_idx);
> +
> + for (i = SENINF_MUX1; i < _seninf_cfg.mux_num; i++)
> + if (mtk_cam_seninf_get_top_mux_ctrl(ctx, i) == seninf_idx &&
> + mtk_cam_seninf_is_mux_used(ctx, i)) {
> + seninf_mux = ctx->reg_if_mux[i];
> + SENINF_BITS(seninf_mux, SENINF_MUX_CTRL_0,
> + SENINF_MUX_SW_RST, 1);
> + udelay(1);
> + SENINF_BITS(seninf_mux, SENINF_MUX_CTRL_0,
> + SENINF_MUX_SW_RST, 0);
> + dev_dbg(ctx->dev, "reset mux %d\n", i);
> + }
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_set_idle(struct seninf_ctx *ctx)
> +{
> + int i;
> + struct seninf_vcinfo *vcinfo = &ctx->vcinfo;
> + struct seninf_vc *vc;
> +
> + for (i = 0; i < vcinfo->cnt; i++) {
> + vc = &vcinfo->vc[i];
> + if (vc->enable) {
> + mtk_cam_seninf_disable_mux(ctx, vc->mux);
> + mtk_cam_seninf_disable_cammux(ctx, vc->cam);
> + ctx->pad2cam[vc->out_pad] = 0xff;
> + }
> + }
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_get_mux_meter(struct seninf_ctx *ctx, u32 mux,
> + struct mtk_cam_seninf_mux_meter *meter)
> +{
> + void __iomem *seninf_mux;
> + s64 hv, hb, vv, vb, w, h;
> + u64 mipi_pixel_rate, vb_in_us, hb_in_us, line_time_in_us;
> + u32 res;
> +
> + seninf_mux = ctx->reg_if_mux[mux];
> +
> + SENINF_BITS(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_CTRL,
> + RG_SENINF_MUX_FRAME_SIZE_MON_EN, 1);
> +
> + hv = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_H_VALID);
> + hb = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_H_BLANK);
> + vv = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_V_VALID);
> + vb = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_V_BLANK);
> + res = SENINF_READ_REG(seninf_mux, SENINF_MUX_SIZE);
> +
> + w = res & 0xffff;
Another case of bitfield.h macros open-coded, or missed opportunity to just
use regmap to simplify this.
> + h = res >> 16;
And same here, of course.
> +
> + if (ctx->fps_n && ctx->fps_d) {
> + mipi_pixel_rate = w * ctx->fps_n * (vv + vb);
> + do_div(mipi_pixel_rate, ctx->fps_d);
Use div_s64() for safe 64-bits division.
> + do_div(mipi_pixel_rate, hv);
> +
> + vb_in_us = vb * ctx->fps_d * 1000000;
> + do_div(vb_in_us, vv + vb);
> + do_div(vb_in_us, ctx->fps_n);
> +
> + hb_in_us = hb * ctx->fps_d * 1000000;
> + do_div(hb_in_us, vv + vb);
> + do_div(hb_in_us, ctx->fps_n);
> +
> + line_time_in_us = (hv + hb) * ctx->fps_d * 1000000;
> + do_div(line_time_in_us, vv + vb);
> + do_div(line_time_in_us, ctx->fps_n);
> +
> + meter->mipi_pixel_rate = mipi_pixel_rate;
> + meter->vb_in_us = vb_in_us;
> + meter->hb_in_us = hb_in_us;
> + meter->line_time_in_us = line_time_in_us;
> + } else {
> + meter->mipi_pixel_rate = -1;
> + meter->vb_in_us = -1;
> + meter->hb_in_us = -1;
> + meter->line_time_in_us = -1;
> + }
> +
> + meter->width = w;
> + meter->height = h;
> +
> + meter->h_valid = hv;
> + meter->h_blank = hb;
> + meter->v_valid = vv;
> + meter->v_blank = vb;
> +
> + return 0;
> +}
> +
> +ssize_t mtk_cam_seninf_show_status(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + int i, len;
> + struct seninf_core *core;
struct seninf_core *core = dev_get_drvdata(dev);
> + struct seninf_ctx *ctx;
> + struct seninf_vc *vc;
> + struct media_link *link;
> + struct media_pad *pad;
> + struct mtk_cam_seninf_mux_meter meter;
> + void __iomem *csi2, *pmux;
> + void __iomem *rx, *pcammux;
int i, len = 0;
> +
> + core = dev_get_drvdata(dev);
> + len = 0;
> +
> + mutex_lock(&core->mutex);
> +
> + list_for_each_entry(ctx, &core->list, list) {
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\n[%s] port %d intf %d test %d cphy %d lanes %d\n",
> + ctx->subdev.name, ctx->port, ctx->seninf_idx,
> + ctx->is_test_model, ctx->is_cphy,
> + ctx->num_data_lanes);
> +
> + pad = &ctx->pads[PAD_SINK];
> + list_for_each_entry(link, &pad->entity->links, list) {
> + if (link->sink == pad) {
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "source %s flags 0x%lx\n",
> + link->source->entity->name,
> + link->flags);
> + }
> + }
> +
> + if (!ctx->streaming)
> + continue;
> +
> + csi2 = ctx->reg_if_csi2[ctx->seninf_idx];
> + rx = ctx->reg_ana_dphy_top[ctx->port];
> +
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "csi2 irq_stat 0x%08x\n",
> + SENINF_READ_REG(csi2, SENINF_CSI2_IRQ_STATUS));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "csi2 line_frame_num 0x%08x\n",
> + SENINF_READ_REG(csi2, SENINF_CSI2_LINE_FRAME_NUM));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "csi2 packet_status 0x%08x\n",
> + SENINF_READ_REG(csi2, SENINF_CSI2_PACKET_STATUS));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "csi2 packet_cnt_status 0x%08x\n",
> + SENINF_READ_REG(csi2, SENINF_CSI2_PACKET_CNT_STATUS));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "rx-ana settle ck 0x%02x dt 0x%02x\n",
> + SENINF_READ_BITS(rx, DPHY_RX_CLOCK_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER),
> + SENINF_READ_BITS(rx,
> + DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "rx-ana trail en %u param 0x%02x\n",
> + SENINF_READ_BITS(rx, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LD0_HS_TRAIL_EN),
> + SENINF_READ_BITS(rx, DPHY_RX_DATA_LANE0_HS_PARAMETER,
> + RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER));
> +
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "data_not_enough_cnt : <%d>",
> + ctx->data_not_enough_cnt);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "err_lane_resync_cnt : <%d>",
> + ctx->err_lane_resync_cnt);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "crc_err_cnt : <%d>", ctx->crc_err_flag);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "ecc_err_double_cnt : <%d>",
> + ctx->ecc_err_double_cnt);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "ecc_err_corrected_cnt : <%d>\n",
> + ctx->ecc_err_corrected_cnt);
> +
> + for (i = 0; i < ctx->vcinfo.cnt; i++) {
> + vc = &ctx->vcinfo.vc[i];
> + pmux = ctx->reg_if_mux[vc->mux];
> + pcammux = ctx->reg_if_cam_mux;
> +
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "[%d] vc 0x%x dt 0x%x mux %d cam %d\n",
> + i, vc->vc, vc->dt, vc->mux, vc->cam);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tmux[%d] en %d src %d irq_stat 0x%x\n",
> + vc->mux,
> + mtk_cam_seninf_is_mux_used(ctx, vc->mux),
> + mtk_cam_seninf_get_top_mux_ctrl(ctx, vc->mux),
> + SENINF_READ_REG(pmux, SENINF_MUX_IRQ_STATUS));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\t\tfifo_overrun_cnt : <%d>\n",
> + ctx->fifo_overrun_cnt);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tcam[%d] en %d src %d exp 0x%x res 0x%x irq_stat 0x%x\n",
> + vc->cam,
> + mtk_cam_seninf_is_cammux_used(ctx, vc->cam),
> + mtk_cam_seninf_get_cammux_ctrl(ctx, vc->cam),
> + mtk_cam_seninf_get_cammux_exp(ctx, vc->cam),
> + mtk_cam_seninf_get_cammux_res(ctx, vc->cam),
> + SENINF_READ_REG(pcammux,
> + SENINF_CAM_MUX_IRQ_STATUS));
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\t\tsize_err_cnt : <%d>\n",
> + ctx->size_err_cnt);
> +
> + if (vc->feature == VC_RAW_DATA ||
> + vc->feature == VC_STAGGER_NE ||
> + vc->feature == VC_STAGGER_ME ||
> + vc->feature == VC_STAGGER_SE) {
> + mtk_cam_seninf_get_mux_meter(ctx, vc->mux,
> + &meter);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\t--- mux meter ---\n");
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\twidth %d height %d\n",
> + meter.width, meter.height);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\th_valid %d, h_blank %d\n",
> + meter.h_valid, meter.h_blank);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tv_valid %d, v_blank %d\n",
> + meter.v_valid, meter.v_blank);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tmipi_pixel_rate %lld\n",
> + meter.mipi_pixel_rate);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tv_blank %lld us\n",
> + meter.vb_in_us);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\th_blank %lld us\n",
> + meter.hb_in_us);
> + len += snprintf(buf + len, PAGE_SIZE - len,
> + "\tline_time %lld us\n",
> + meter.line_time_in_us);
> + }
> + }
> + }
> +
> + mutex_unlock(&core->mutex);
> +
> + return len;
> +}
> +
> +#define SENINF_DRV_DEBUG_MAX_DELAY 400
> +
> +static inline void
> +mtk_cam_seninf_clear_matched_cam_mux_irq(struct seninf_ctx *ctx,
> + u32 cam_mux_idx,
Why is this a u32 param?....
> + u32 vc_idx,
> + s32 enabled)
> +{
> + u8 used_cammux;
...if this is a u8 local variable?
(cam_mux_idx should be u8 instead - same for vc_idx)
> +
> + if (cam_mux_idx >= SENINF_CAM_MUX_NUM) {
> + dev_info(ctx->dev, "unsupport cam_mux(%u)", cam_mux_idx);
> + return;
> + }
> + if (vc_idx >= SENINF_VC_MAXCNT) {
> + dev_info(ctx->dev, "unsupport vc_idx(%u)", vc_idx);
> + return;
> + }
> +
> + used_cammux = ctx->vcinfo.vc[vc_idx].cam;
> + if (used_cammux == cam_mux_idx &&
> + enabled & (1 << cam_mux_idx)) {
> + dev_dbg(ctx->dev,
> + "before clear cam mux%u recSize = 0x%x, irq = 0x%x",
> + cam_mux_idx,
> + SENINF_READ_REG(ctx->reg_if_cam_mux,
> + SENINF_CAM_MUX0_CHK_RES + (0x10 * cam_mux_idx)),
> + SENINF_READ_REG(ctx->reg_if_cam_mux,
> + SENINF_CAM_MUX_IRQ_STATUS));
> +
> + SENINF_WRITE_REG(ctx->reg_if_cam_mux,
> + SENINF_CAM_MUX_IRQ_STATUS,
> + 3 << (cam_mux_idx * 2));
> + }
> +}
> +
> +static inline void mtk_cam_seninf_check_matched_cam_mux(struct seninf_ctx *ctx,
> + u32 cam_mux_idx,
> + u32 vc_idx,
> + s32 enabled,
> + s32 irq_status)
> +{
> + u8 used_cammux;
> +
> + if (cam_mux_idx >= SENINF_CAM_MUX_NUM) {
> + dev_info(ctx->dev, "unsupport cam_mux(%u)", cam_mux_idx);
> + return;
> + }
> + if (vc_idx >= SENINF_VC_MAXCNT) {
> + dev_info(ctx->dev, "unsupport vc_idx(%u)", vc_idx);
> + return;
> + }
> +
> + used_cammux = ctx->vcinfo.vc[vc_idx].cam;
> +
> + if (used_cammux == cam_mux_idx && enabled & (1 << cam_mux_idx)) {
> + int rec_size = SENINF_READ_REG(ctx->reg_if_cam_mux,
> + SENINF_CAM_MUX0_CHK_RES + (0x10 * cam_mux_idx));
> + int exp_size = SENINF_READ_REG(ctx->reg_if_cam_mux,
> + SENINF_CAM_MUX0_CHK_CTL_1 + (0x10 * cam_mux_idx));
> + if (rec_size != exp_size) {
> + dev_dbg(ctx->dev,
> + "cam mux%u size mismatch, (rec, exp) = (0x%x, 0x%x)",
> + cam_mux_idx, rec_size, exp_size);
> + }
> + if ((irq_status &
> + (3 << (cam_mux_idx * 2))) != 0) {
> + dev_dbg(ctx->dev,
> + "cam mux%u size mismatch!, irq = 0x%x",
> + cam_mux_idx, irq_status);
> + }
> + }
> +}
> +
..snip..
> +
> +#define SBUF 256
> +int mtk_cam_seninf_irq_handler(int irq, void *data)
> +{
> + struct seninf_core *core = (struct seninf_core *)data;
> + unsigned long flags; /* for mipi err detection */
> + struct seninf_ctx *ctx;
> + struct seninf_vc *vc;
> + void __iomem *csi2, *pmux, *seninf_cam_mux;
> + int i;
> + unsigned int csi_irq_ro;
> + unsigned int mux_irq_ro;
> + unsigned int cam_irq_exp_ro;
> + unsigned int cam_irq_res_ro;
> + char seninf_log[SBUF];
> + unsigned int wcnt = 0;
> +
> + spin_lock_irqsave(&core->spinlock_irq, flags);
> +
> + /* debug for set_reg case: REG_KEY_CSI_IRQ_EN */
> + if (core->csi_irq_en_flag) {
> + list_for_each_entry(ctx, &core->list, list) {
> + csi2 = ctx->reg_if_csi2[ctx->seninf_idx];
> + csi_irq_ro =
> + SENINF_READ_REG(csi2, SENINF_CSI2_IRQ_STATUS);
> +
> + if (csi_irq_ro) {
> + SENINF_WRITE_REG(csi2, SENINF_CSI2_IRQ_STATUS,
> + 0xFFFFFFFF);
> + }
> +
> + if (csi_irq_ro & (0x1 << RO_CSI2_ECC_ERR_CORRECTED_IRQ_SHIFT))
> + ctx->ecc_err_corrected_cnt++;
> + if (csi_irq_ro & (0x1 << RO_CSI2_ECC_ERR_DOUBLE_IRQ_SHIFT))
> + ctx->ecc_err_double_cnt++;
> + if (csi_irq_ro & (0x1 << RO_CSI2_CRC_ERR_IRQ_SHIFT))
> + ctx->crc_err_cnt++;
> + if (csi_irq_ro & (0x1 << RO_CSI2_ERR_LANE_RESYNC_IRQ_SHIFT))
> + ctx->err_lane_resync_cnt++;
> + if (csi_irq_ro & (0x1 << RO_CSI2_RECEIVE_DATA_NOT_ENOUGH_IRQ_SHIFT))
> + ctx->data_not_enough_cnt++;
> +
> + for (i = 0; i < ctx->vcinfo.cnt; i++) {
> + vc = &ctx->vcinfo.vc[i];
> + pmux = ctx->reg_if_mux[vc->mux];
> + seninf_cam_mux = ctx->reg_if_cam_mux;
> +
> + mux_irq_ro = SENINF_READ_REG(pmux,
> + SENINF_MUX_IRQ_STATUS);
> +
> + cam_irq_exp_ro = SENINF_READ_REG(seninf_cam_mux,
> + SENINF_CAM_MUX0_CHK_CTL_1 +
> + (0x10 * (vc->cam)));
> +
> + cam_irq_res_ro = SENINF_READ_REG(seninf_cam_mux,
> + SENINF_CAM_MUX0_CHK_RES +
> + (0x10 * (vc->cam)));
> +
> + if (mux_irq_ro)
> + SENINF_WRITE_REG(pmux,
> + SENINF_MUX_IRQ_STATUS,
> + 0xFFFFFFFF);
> +
> + if (cam_irq_res_ro != cam_irq_exp_ro)
> + SENINF_WRITE_REG(seninf_cam_mux,
> + SENINF_CAM_MUX0_CHK_RES +
> + (0x10 * (vc->cam)),
> + 0xFFFFFFFF);
> +
> + if (mux_irq_ro & (0x1 << 0))
> + ctx->fifo_overrun_cnt++;
> +
> + if (cam_irq_res_ro != cam_irq_exp_ro)
> + ctx->size_err_cnt++;
> + }
> +
> + /* dump status counter: debug for electrical signal */
> + if (ctx->data_not_enough_cnt >= core->detection_cnt ||
> + ctx->err_lane_resync_cnt >= core->detection_cnt ||
> + ctx->crc_err_cnt >= core->detection_cnt ||
> + ctx->ecc_err_double_cnt >= core->detection_cnt ||
> + ctx->ecc_err_corrected_cnt >= core->detection_cnt ||
> + ctx->fifo_overrun_cnt >= core->detection_cnt ||
> + ctx->size_err_cnt >= core->detection_cnt) {
> + /* disable all interrupts */
> + SENINF_WRITE_REG(csi2, SENINF_CSI2_IRQ_EN, 0x80000000);
> +
> + if (ctx->data_not_enough_cnt >= core->detection_cnt)
> + ctx->data_not_enough_flag = 1;
> + if (ctx->err_lane_resync_cnt >= core->detection_cnt)
> + ctx->err_lane_resync_flag = 1;
> + if (ctx->crc_err_cnt >= core->detection_cnt)
> + ctx->crc_err_flag = 1;
> + if (ctx->ecc_err_double_cnt >= core->detection_cnt)
> + ctx->ecc_err_double_flag = 1;
> + if (ctx->ecc_err_corrected_cnt >= core->detection_cnt)
> + ctx->ecc_err_corrected_flag = 1;
> + if (ctx->fifo_overrun_cnt >= core->detection_cnt)
> + ctx->fifo_overrun_flag = 1;
> + if (ctx->size_err_cnt >= core->detection_cnt)
> + ctx->size_err_flag = 1;
> +
> + wcnt = snprintf(seninf_log, SBUF, "info: %s", __func__);
You're not even printing seninf_log, so either print it (no, please don't)
or just drop it.
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " data_not_enough_count: %d",
> + ctx->data_not_enough_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " err_lane_resync_count: %d",
> + ctx->err_lane_resync_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " crc_err_count: %d",
> + ctx->crc_err_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " ecc_err_double_count: %d",
> + ctx->ecc_err_double_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " ecc_err_corrected_count: %d",
> + ctx->ecc_err_corrected_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " fifo_overrun_count: %d",
> + ctx->fifo_overrun_cnt);
> + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt,
> + " size_err_count: %d",
> + ctx->size_err_cnt);
> + }
> + }
> + }
> +
> + spin_unlock_irqrestore(&core->spinlock_irq, flags);
> +
> + return 0;
> +}
> +
> +int mtk_cam_seninf_set_sw_cfg_busy(struct seninf_ctx *ctx, bool enable,
> + int index)
> +{
> + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux;
mask = index ? RG_SENINF_CAM_MUX_DYN_SWITCH_BSY1 :
RG_SENINF_CAM_MUX_DYN_SWITCH_BSY0
> +
> + if (index == 0)
> + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_CTRL,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_BSY0, enable);
> + else
> + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_CTRL,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_BSY1, enable);
> + return 0;
> +}
> +
> +int mtk_cam_seninf_set_cam_mux_dyn_en(struct seninf_ctx *ctx, bool enable,
> + int cam_mux, int index)
> +{
> + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux;
> + u32 tmp = 0;
> +
> + if (index == 0) {
> + tmp = SENINF_READ_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_EN0);
regmap_set_bits() will definitely help here.
> + if (enable)
> + tmp = tmp | (1 << cam_mux);
> + else
> + tmp = tmp & ~(1 << cam_mux);
> +
> + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_EN0, tmp);
> + } else {
> + tmp = SENINF_READ_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_EN1);
> + if (enable)
> + tmp = tmp | (1 << cam_mux);
> + else
> + tmp = tmp & ~(1 << cam_mux);
> +
> + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN,
> + RG_SENINF_CAM_MUX_DYN_SWITCH_EN1, tmp);
> + }
> +
> + return 0;
> +}
> +
There is surely more to say on this driver, and it's far from being near to
upstream quality.
Please start with addressing these comments on the entire series, then we can go
on with further reviews.
Regards,
Angelo
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
@ 2024-10-09 21:00 ` Rob Herring
2024-10-11 1:29 ` CK Hu (胡俊光)
` (4 subsequent siblings)
5 siblings, 0 replies; 88+ messages in thread
From: Rob Herring @ 2024-10-09 21:00 UTC (permalink / raw)
To: Shu-hsiang Yang
Cc: Mauro Carvalho Chehab, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Sumit Semwal,
Christian Konig, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
On Wed, Oct 09, 2024 at 07:15:42PM +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
> .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
> .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
> 5 files changed, 582 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> new file mode 100644
> index 000000000000..c709e4bf0a18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
Compatibles should be SoC specific.
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
Don't need these. You don't have any child nodes with addresses.
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
Drop items.
> + minItems: 1
> + maxItems: 2
You have to specify what each region is.
Why does it vary? A h/w block either has register region or it doesn't.
> +
> + reg-names:
> + minItems: 1
> + maxItems: 2
You must define the names.
> +
> + mediatek,cam-id:
> + description:
> + Describes the index of MediaTek cam-raw unit for ISP
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
No, we don't put module indices in DT.
> +
> + mediatek,larbs:
> + description:
> + Describes MediaTek bus infrastructure unit for ISP system.
> + List of phandle to the local arbiters in the current SoCs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + maxItems: 32
> +
> + interrupts:
> + minItems: 1
> +
> + dma-ranges:
> + description:
> + Describes the address information of IOMMU mapping to memory.
> + Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
> + minItems: 1
> +
> + power-domains:
> + minItems: 1
> +
> + clocks:
> + minItems: 4
> + maxItems: 16
You have to define what the clocks are.
> +
> + clock-names:
> + minItems: 4
> + maxItems: 16
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
Drop. You don't need to document assigned-clocks.
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> new file mode 100644
> index 000000000000..30dfd5e5ecb1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
Similar comments on the rest.
Rob
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-10 12:49 ` AngeloGioacchino Del Regno
2024-10-11 2:23 ` CK Hu (胡俊光)
` (12 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-10-10 12:49 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, Sumit Semwal,
Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
Il 09/10/24 13:15, Shu-hsiang Yang ha scritto:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 +
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 +
> .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 +
> 5 files changed, 6191 insertions(+)
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
>
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
> new file mode 100644
> index 000000000000..c025f53c952d
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
> @@ -0,0 +1,5359 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/vmalloc.h>
> +#include <linux/videodev2.h>
> +#include <linux/suspend.h>
> +#include <linux/rtc.h>
> +
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-subdev.h>
> +
> +#include <soc/mediatek/smi.h>
> +
> +#include "mtk_cam.h"
> +#include "mtk_cam-feature.h"
> +#include "mtk_cam-raw.h"
> +
> +#include "mtk_cam-regs-mt8188.h"
> +
> +#include "mtk_cam-video.h"
> +#include "mtk_cam-seninf-if.h"
> +#include "mtk_camera-v4l2-controls.h"
> +
> +#include "mtk_cam-dmadbg.h"
> +#include "mtk_cam-raw_debug.h"
> +
> +static unsigned int debug_raw;
> +module_param(debug_raw, uint, 0644);
> +MODULE_PARM_DESC(debug_raw, "activates debug info");
> +
> +static int debug_raw_num = -1;
> +module_param(debug_raw_num, int, 0644);
> +MODULE_PARM_DESC(debug_raw_num, "debug: num of used raw devices");
> +
> +static int debug_pixel_mode = -1;
> +module_param(debug_pixel_mode, int, 0644);
> +MODULE_PARM_DESC(debug_pixel_mode, "debug: pixel mode");
> +
> +static int debug_clk_idx = -1;
> +module_param(debug_clk_idx, int, 0644);
> +MODULE_PARM_DESC(debug_clk_idx, "debug: clk idx");
> +
> +static int debug_dump_fbc;
> +module_param(debug_dump_fbc, int, 0644);
> +MODULE_PARM_DESC(debug_dump_fbc, "debug: dump fbc");
> +
In addition to the first review that I gave you on patch [02/10]: please drop
all those module parameters. If you want debug switches, use debugfs instead.
Regards,
Angelo
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
2024-10-09 21:00 ` Rob Herring
@ 2024-10-11 1:29 ` CK Hu (胡俊光)
2024-10-11 3:20 ` CK Hu (胡俊光)
` (3 subsequent siblings)
5 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 1:29 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-shiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
> .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
> .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
Break each binding document to an independent patch and this would make review process easier.
For example, there are five patches for each of cam-raw, cam-yuv, camisp, seninf-core, seninf.
When I feel good about cam-raw, cam-yuv, camisp, I would give reviewed-by tag on these three patches.
After you send new version, I could focus on reviewing seninf-core and seninf.
If these are combined into one patch, even I feel good about cam-raw, cam-yuv, camisp, I can not give reviewed-by tag on this patch.
After you send new version, I need to review the whole patch again. This would slow down the review process.
> 5 files changed, 582 insertions(+)
>
[snip]
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPnhKvzWQ$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
mediatek,mt8188-cam-raw
> +
> + "#address-cells":
> + const: 2
> +
>
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> new file mode 100644
> index 000000000000..30dfd5e5ecb1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> @@ -0,0 +1,148 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-yuv.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPyS5asjc$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The cam-yuv unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-yuv is the camera YUV processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-yuv
mediatek,mt8188-cam-yuv
> +
> + "#address-cells":
> + const: 2
> +
>
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> new file mode 100644
> index 000000000000..ce378ddbd5bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPg8zy568$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The camisp unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,camisp
mediatek,mt8188-camisp
> +
> + "#address-cells":
> + const: 2
> +
>
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> new file mode 100644
> index 000000000000..bc509976a79e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> @@ -0,0 +1,106 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf-core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPyn0dkZA$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The seninf-core top unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek seninf-core is the ISP sensor interface unit in MediaTek SoC.
> + The sensor interface serves as the MIPI-CSI2 top RX controller.
> +
> +properties:
> + compatible:
> + const: mediatek,seninf-core
mediatek,mt8188-seninf-core
> +
> + "#address-cells":
> + const: 2
> +
>
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> new file mode 100644
> index 000000000000..37d94138c558
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPVkLta9M$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The seninf unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC.
> + These ports provide the optional capability to define endpoints and set RX
> + controller for camera sensors.
> +
> +properties:
> + compatible:
> + const: mediatek,seninf
mediatek,mt8188-seninf
Regards,
CK
> +
> + csi-port:
> + description: MediaTek CSI Rx port name
> + $ref: /schemas/types.yaml#/definitions/string
> +
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
2024-10-09 12:50 ` [PATCH v1 02/10] media: platform: mediatek: add seninf controller AngeloGioacchino Del Regno
@ 2024-10-11 1:36 ` CK Hu (胡俊光)
2024-10-11 2:38 ` CK Hu (胡俊光)
` (2 subsequent siblings)
4 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 1:36 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 ++++++
> .../mtk_cam-seninf-csi0-cphy.h | 69 +
> .../mtk_cam-seninf-csi0-dphy.h | 139 +
> .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++++++++++
> .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 ++
> .../mtk_cam-seninf-seninf1-csi2.h | 415 +++
> .../mtk_cam-seninf-seninf1-mux.h | 147 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 +
Move the phy part to phy/mediatek/ folder. You could refer to phy/mediatek/phy-mtk-mipi-csi-0-5.c
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
2024-10-10 12:49 ` [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit AngeloGioacchino Del Regno
@ 2024-10-11 2:23 ` CK Hu (胡俊光)
2024-10-11 2:55 ` CK Hu (胡俊光)
` (11 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 2:23 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 +
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 +
> .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 +
Without debug, this driver could still work, so separate debug function to an independent patch.
It seems yuv is an independent function. If so, separate yuv function to an independent patch.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
2024-10-09 12:50 ` [PATCH v1 02/10] media: platform: mediatek: add seninf controller AngeloGioacchino Del Regno
2024-10-11 1:36 ` CK Hu (胡俊光)
@ 2024-10-11 2:38 ` CK Hu (胡俊光)
2024-10-22 4:16 ` CK Hu (胡俊光)
2024-10-28 1:55 ` CK Hu (胡俊光)
4 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 2:38 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +int mtk_cam_seninf_debug(struct seninf_ctx *ctx)
> +{
Without debug, this driver could still work. So separate debug function to an independent patch.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
2024-10-10 12:49 ` [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit AngeloGioacchino Del Regno
2024-10-11 2:23 ` CK Hu (胡俊光)
@ 2024-10-11 2:55 ` CK Hu (胡俊光)
2024-10-11 5:40 ` CK Hu (胡俊光)
` (10 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 2:55 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +static void set_fifo_threshold(void __iomem *dma_base)
> +{
> + u32 fifo_size = 0;
> +
> + fifo_size = readl_relaxed(dma_base + DMA_OFFSET_CON0) & 0xFFF;
> + writel_relaxed((0x1 << 28) |
> + ((fifo_size * 1 / 4) & 0xFFF) << 16 |
> + ((fifo_size * 1 / 8) & 0xFFF),
> + dma_base + DMA_OFFSET_CON1);
I can not find definition of DMA_OFFSET_CON1 in this patch, but I find it in [6/10] patch.
Move the definition to this patch.
And when you add this file, make sure you could build it successfully.
Regards,
CK
> + writel_relaxed((0x1 << 28) |
> + ((fifo_size * 1 / 2) & 0xFFF) << 16 |
> + ((fifo_size * 3 / 8) & 0xFFF),
> + dma_base + DMA_OFFSET_CON2);
> + writel_relaxed((0x1 << 31) |
> + ((fifo_size * 2 / 3) & 0xFFF) << 16 |
> + ((fifo_size * 13 / 24) & 0xFFF),
> + dma_base + DMA_OFFSET_CON3);
> + writel_relaxed((0x1 << 31) |
> + ((fifo_size * 3 / 8) & 0xFFF) << 16 |
> + ((fifo_size * 1 / 4) & 0xFFF),
> + dma_base + DMA_OFFSET_CON4);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
2024-10-09 21:00 ` Rob Herring
2024-10-11 1:29 ` CK Hu (胡俊光)
@ 2024-10-11 3:20 ` CK Hu (胡俊光)
2024-10-22 5:36 ` Krzysztof Kozlowski
` (2 subsequent siblings)
5 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 3:20 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> new file mode 100644
> index 000000000000..37d94138c558
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPVkLta9M$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The seninf unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC.
> + These ports provide the optional capability to define endpoints and set RX
> + controller for camera sensors.
> +
> +properties:
> + compatible:
> + const: mediatek,seninf
> +
> + csi-port:
> + description: MediaTek CSI Rx port name
> + $ref: /schemas/types.yaml#/definitions/string
> +
> + port:
> + description:
> + MediaTek sensor interface endpoints for one sensor bus.
> + $ref: /schemas/graph.yaml#/$defs/port-base
> +
> + properties:
> + "#address-cells":
> + const: 1
> + "#size-cells":
> + const: 0
> +
> + patternProperties:
> + "^endpoint(@[0-9]+)?$":
> + description:
> + CSI port for one sensor endpoint configuration.
> + Consider one sensor bus can support differet links for MIPI PHY.
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> + properties:
> + data-lanes:
> + items:
> + enum: [1, 2, 3, 4]
> + maxItems: 4
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - csi-port
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + seninf_top {
> + seninf_csi_port_0: seninf_csi_port_0 {
> + compatible = "mediatek,seninf";
> + csi-port = "0A";
This device has no reg property, so it's a virtual device not a real device.
binding document is used to describe a real hardware device, so drop this binding document.
There is another seninf device [1] which is upstreaming.
Even though it's not upstreamed yet, it have been reviewed.
You may take it as a reference.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=874617
Regards,
CK
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + seninf_csi_port_0_in_1: endpoint {
> + data-lanes = <1 2>;
> + link-frequencies = /bits/ 64 <1440000000 624000000>;
> + remote-endpoint = <&sensor0_out_1>;
> + };
> +
> + seninf_csi_port_0_in_2: endpoint@2 {
> + reg = <2>;
> + data-lanes = <1 2>;
> + link-frequencies = /bits/ 64 <336000000 207000000>;
> + remote-endpoint = <&sensor0_out_2>;
> + };
> + };
> + };
> + };
> +
> +...
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (2 preceding siblings ...)
2024-10-11 2:55 ` CK Hu (胡俊光)
@ 2024-10-11 5:40 ` CK Hu (胡俊光)
2024-10-11 6:03 ` CK Hu (胡俊光)
` (9 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 5:40 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +static irqreturn_t mtk_thread_irq_raw(int irq, void *data)
> +{
> + struct mtk_raw_device *raw_dev = (struct mtk_raw_device *)data;
> + struct mtk_camsys_irq_info irq_info;
> +
> + if (unlikely(atomic_cmpxchg(&raw_dev->is_fifo_overflow, 1, 0)))
> + dev_info(raw_dev->dev, "msg fifo overflow\n");
> +
> + while (kfifo_len(&raw_dev->msg_fifo) >= sizeof(irq_info)) {
> + int len = kfifo_out(&raw_dev->msg_fifo, &irq_info, sizeof(irq_info));
> +
> + WARN_ON(len != sizeof(irq_info));
> +
> + dev_dbg(raw_dev->dev, "ts=%llu irq_type %d, req:%d/%d\n",
> + irq_info.ts_ns, irq_info.irq_type,
> + irq_info.frame_idx_inner, irq_info.frame_idx);
> +
> + /* error case */
> + if (unlikely(irq_info.irq_type == (1 << CAMSYS_IRQ_ERROR))) {
> + raw_handle_error(raw_dev, &irq_info);
> + continue;
> + }
> +
> + /* normal case */
> + /* inform interrupt information to camsys controller */
> + mtk_camsys_isr_event(raw_dev->cam, CAMSYS_ENGINE_RAW,
> + raw_dev->id, &irq_info);
mtk_camsys_isr_event() is not defined in this patch but defined in [8/10] patch.
This is weird to use a function defined in future.
Define this function in this patch or previous patch.
Regards,
CK
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (3 preceding siblings ...)
2024-10-11 5:40 ` CK Hu (胡俊光)
@ 2024-10-11 6:03 ` CK Hu (胡俊光)
2024-10-22 5:43 ` Krzysztof Kozlowski
` (8 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 6:03 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +/* feature mask to categorize all raw functions */
> +#define MTK_CAM_FEATURE_HDR_MASK 0x0000000F
> +#define MTK_CAM_FEATURE_SUBSAMPLE_MASK 0x000000F0
> +#define MTK_CAM_FEATURE_OFFLINE_M2M_MASK 0x00000100
> +#define MTK_CAM_FEATURE_PURE_OFFLINE_M2M_MASK 0x00000200
It seems that M2M is not basic function. It's an advanced function, so separate M2M related code to an independent patch.
Make the first patch as simple as possible.
Regards,
CK
> +
> +enum raw_function_id {
> + /* bit [0~3] hdr */
> + /* bit [4~7] fps */
> + /* bit [8~9] m2m */
> + OFFLINE_M2M = (1 << 8),
> + PURE_OFFLINE_M2M = (1 << 9),
> + RAW_FUNCTION_END = 0xF0000000,
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-10-09 11:15 ` [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api Shu-hsiang Yang
@ 2024-10-11 7:47 ` CK Hu (胡俊光)
2024-10-14 5:56 ` CK Hu (胡俊光)
2024-11-05 5:36 ` CK Hu (胡俊光)
2 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-11 7:47 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Add UAPI for MediaTek ISP platform, providing user-space
> interfaces for the new camsys driver.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +/* Luminance+Chrominance formats */
> +#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'A') /* 16 YUV 4:2:2 10-bit */
> +#define V4L2_PIX_FMT_YVYU10 v4l2_fourcc('Y', 'V', 'Y', 'A') /* 16 YUV 4:2:2 10-bit */
> +#define V4L2_PIX_FMT_UYVY10 v4l2_fourcc('U', 'Y', 'V', 'A') /* 16 YUV 4:2:2 10-bit */
> +#define V4L2_PIX_FMT_VYUY10 v4l2_fourcc('V', 'Y', 'U', 'A') /* 16 YUV 4:2:2 10-bit */
> +#define V4L2_PIX_FMT_YUYV12 v4l2_fourcc('Y', 'U', 'Y', 'C') /* 16 YUV 4:2:2 12-bit */
> +#define V4L2_PIX_FMT_YVYU12 v4l2_fourcc('Y', 'V', 'Y', 'C') /* 16 YUV 4:2:2 12-bit */
> +#define V4L2_PIX_FMT_UYVY12 v4l2_fourcc('U', 'Y', 'V', 'C') /* 16 YUV 4:2:2 12-bit */
> +#define V4L2_PIX_FMT_VYUY12 v4l2_fourcc('V', 'Y', 'U', 'C') /* 16 YUV 4:2:2 12-bit */
> +
> +/* two planes -- one Y, one Cr + Cb interleaved */
> +#define V4L2_PIX_FMT_NV12_10 v4l2_fourcc('1', '2', 'A', 'U') /* 12 Y/CbCr 4:2:0 10 bits un-packed */
> +#define V4L2_PIX_FMT_NV21_10 v4l2_fourcc('2', '1', 'A', 'U') /* 12 Y/CrCb 4:2:0 10 bits un-packed */
> +#define V4L2_PIX_FMT_NV16_10 v4l2_fourcc('1', '6', 'A', 'U') /* 16 Y/CbCr 4:2:2 10 bits un-packed */
> +#define V4L2_PIX_FMT_NV61_10 v4l2_fourcc('6', '1', 'A', 'U') /* 16 Y/CrCb 4:2:2 10 bits un-packed */
> +#define V4L2_PIX_FMT_NV12_12 v4l2_fourcc('1', '2', 'C', 'U') /* 12 Y/CbCr 4:2:0 12 bits un-packed */
> +#define V4L2_PIX_FMT_NV21_12 v4l2_fourcc('2', '1', 'C', 'U') /* 12 Y/CrCb 4:2:0 12 bits un-packed */
> +#define V4L2_PIX_FMT_NV16_12 v4l2_fourcc('1', '6', 'C', 'U') /* 16 Y/CbCr 4:2:2 12 bits un-packed */
> +#define V4L2_PIX_FMT_NV61_12 v4l2_fourcc('6', '1', 'C', 'U') /* 16 Y/CrCb 4:2:2 12 bits un-packed */
> +
> +/* Vendor specific - MediaTek ISP bayer formats */
> +#define V4L2_PIX_FMT_MTISP_SBGGR8 v4l2_fourcc('M', 'B', 'B', '8') /* Packed 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG8 v4l2_fourcc('M', 'B', 'G', '8') /* Packed 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG8 v4l2_fourcc('M', 'B', 'g', '8') /* Packed 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB8 v4l2_fourcc('M', 'B', 'R', '8') /* Packed 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR10 v4l2_fourcc('M', 'B', 'B', 'A') /* Packed 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG10 v4l2_fourcc('M', 'B', 'G', 'A') /* Packed 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG10 v4l2_fourcc('M', 'B', 'g', 'A') /* Packed 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB10 v4l2_fourcc('M', 'B', 'R', 'A') /* Packed 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR12 v4l2_fourcc('M', 'B', 'B', 'C') /* Packed 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG12 v4l2_fourcc('M', 'B', 'G', 'C') /* Packed 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG12 v4l2_fourcc('M', 'B', 'g', 'C') /* Packed 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB12 v4l2_fourcc('M', 'B', 'R', 'C') /* Packed 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR14 v4l2_fourcc('M', 'B', 'B', 'E') /* Packed 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG14 v4l2_fourcc('M', 'B', 'G', 'E') /* Packed 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG14 v4l2_fourcc('M', 'B', 'g', 'E') /* Packed 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB14 v4l2_fourcc('M', 'B', 'R', 'E') /* Packed 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR8F v4l2_fourcc('M', 'F', 'B', '8') /* Full-G 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG8F v4l2_fourcc('M', 'F', 'G', '8') /* Full-G 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG8F v4l2_fourcc('M', 'F', 'g', '8') /* Full-G 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB8F v4l2_fourcc('M', 'F', 'R', '8') /* Full-G 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR10F v4l2_fourcc('M', 'F', 'B', 'A') /* Full-G 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG10F v4l2_fourcc('M', 'F', 'G', 'A') /* Full-G 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG10F v4l2_fourcc('M', 'F', 'g', 'A') /* Full-G 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB10F v4l2_fourcc('M', 'F', 'R', 'A') /* Full-G 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR12F v4l2_fourcc('M', 'F', 'B', 'C') /* Full-G 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG12F v4l2_fourcc('M', 'F', 'G', 'C') /* Full-G 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG12F v4l2_fourcc('M', 'F', 'g', 'C') /* Full-G 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB12F v4l2_fourcc('M', 'F', 'R', 'C') /* Full-G 12-bit */
> +#define V4L2_PIX_FMT_MTISP_SBGGR14F v4l2_fourcc('M', 'F', 'B', 'E') /* Full-G 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SGBRG14F v4l2_fourcc('M', 'F', 'G', 'E') /* Full-G 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRBG14F v4l2_fourcc('M', 'F', 'g', 'E') /* Full-G 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SRGGB14F v4l2_fourcc('M', 'F', 'R', 'E') /* Full-G 14-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRB8F v4l2_fourcc('M', 'F', '8', 'P') /* three planes Full-G 8-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRB10F v4l2_fourcc('M', 'F', 'A', 'P') /* three planes Full-G 10-bit */
> +#define V4L2_PIX_FMT_MTISP_SGRB12F v4l2_fourcc('M', 'F', 'C', 'P') /* three planes Full-G 12-bit */
> +
> +/* Vendor specific - MediaTek Luminance+Chrominance formats */
> +#define V4L2_PIX_FMT_MTISP_YUYV10P v4l2_fourcc('Y', 'U', 'A', 'P') /* YUV 4:2:2 10-bit packed */
> +#define V4L2_PIX_FMT_MTISP_YVYU10P v4l2_fourcc('Y', 'V', 'A', 'P') /* YUV 4:2:2 10-bit packed */
> +#define V4L2_PIX_FMT_MTISP_UYVY10P v4l2_fourcc('U', 'Y', 'A', 'P') /* YUV 4:2:2 10-bit packed */
> +#define V4L2_PIX_FMT_MTISP_VYUY10P v4l2_fourcc('V', 'Y', 'A', 'P') /* YUV 4:2:2 10-bit packed */
> +#define V4L2_PIX_FMT_MTISP_NV12_10P v4l2_fourcc('1', '2', 'A', 'P') /* Y/CbCr 4:2:0 10 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV21_10P v4l2_fourcc('2', '1', 'A', 'P') /* Y/CrCb 4:2:0 10 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV16_10P v4l2_fourcc('1', '6', 'A', 'P') /* Y/CbCr 4:2:2 10 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV61_10P v4l2_fourcc('6', '1', 'A', 'P') /* Y/CrCb 4:2:2 10 bits packed */
> +#define V4L2_PIX_FMT_MTISP_YUYV12P v4l2_fourcc('Y', 'U', 'C', 'P') /* YUV 4:2:2 12-bit packed */
> +#define V4L2_PIX_FMT_MTISP_YVYU12P v4l2_fourcc('Y', 'V', 'C', 'P') /* YUV 4:2:2 12-bit packed */
> +#define V4L2_PIX_FMT_MTISP_UYVY12P v4l2_fourcc('U', 'Y', 'C', 'P') /* YUV 4:2:2 12-bit packed */
> +#define V4L2_PIX_FMT_MTISP_VYUY12P v4l2_fourcc('V', 'Y', 'C', 'P') /* YUV 4:2:2 12-bit packed */
> +#define V4L2_PIX_FMT_MTISP_NV12_12P v4l2_fourcc('1', '2', 'C', 'P') /* Y/CbCr 4:2:0 12 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV21_12P v4l2_fourcc('2', '1', 'C', 'P') /* Y/CrCb 4:2:0 12 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV16_12P v4l2_fourcc('1', '6', 'C', 'P') /* Y/CbCr 4:2:2 12 bits packed */
> +#define V4L2_PIX_FMT_MTISP_NV61_12P v4l2_fourcc('6', '1', 'C', 'P') /* Y/CrCb 4:2:2 12 bits packed */
> +
> +/* Vendor specific - MediaTek specified compressed format */
> +#define V4L2_PIX_FMT_MTISP_NV12_UFBC v4l2_fourcc('1', '2', '8', 'F') /* Y/CbCr 4:2:0 8 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_NV21_UFBC v4l2_fourcc('2', '1', '8', 'F') /* Y/CrCb 4:2:0 8 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_NV12_10_UFBC v4l2_fourcc('1', '2', 'A', 'F') /* Y/CbCr 4:2:0 10 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_NV21_10_UFBC v4l2_fourcc('2', '1', 'A', 'F') /* Y/CrCb 4:2:0 10 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_NV12_12_UFBC v4l2_fourcc('1', '2', 'C', 'F') /* Y/CbCr 4:2:0 12 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_NV21_12_UFBC v4l2_fourcc('2', '1', 'C', 'F') /* Y/CrCb 4:2:0 12 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_BAYER8_UFBC v4l2_fourcc('M', 'B', '8', 'U') /* Raw 8 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_BAYER10_UFBC v4l2_fourcc('M', 'B', 'A', 'U') /* Raw 10 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_BAYER12_UFBC v4l2_fourcc('M', 'B', 'C', 'U') /* Raw 12 bits compressed */
> +#define V4L2_PIX_FMT_MTISP_BAYER14_UFBC v4l2_fourcc('M', 'B', 'E', 'U') /* Raw 14 bits compressed */
> +
I think the V4L2 pixel format should be defined in include/uapi/linux/videodev2.h
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-14 5:21 ` CK Hu (胡俊光)
2024-10-22 5:30 ` CK Hu (胡俊光)
` (15 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-14 5:21 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * V 4 L 2 M E T A B U F F E R L A Y O U T
> + */
> +
> +/*
> + * struct mtk_cam_uapi_meta_raw_stats_cfg
> + *
> + * @ae_awb_enable: To indicate if AE and AWB should be enblaed or not. If
> + * it is 1, it means that we enable the following parts of
> + * hardware:
> + * (1) AE/AWB
> + * (2) aao
> + * (3) aaho
> + * @af_enable: To indicate if AF should be enabled or not. If it is 1,
> + * it means that the AF and afo is enabled.
> + * @dgn_enable: To indicate if dgn module should be enabled or not.
> + * @flk_enable: If it is 1, it means flk and flko is enable. If ie is 0,
> + * both flk and flko is disabled.
> + * @tsf_enable: If it is 1, it means tsfs and tsfso is enable. If ie is 0,
> + * both tsfs and tsfso is disabled.
> + * @wb_enable: To indicate if wb module should be enabled or not.
> + * @pde_enable: To indicate if pde module should be enabled or not.
> + * @ae_param: AE Statistic window config
> + * @awb_param: AWB statistic configuration control
> + * @dgn_param: DGN settings
> + * @flk_param: Flicker statistic configuration
> + * @tsf_param: tsf statistic configuration
> + * @wb_param: WB settings
> + * @pde_param: pde settings
> + */
> +struct mtk_cam_uapi_meta_raw_stats_cfg {
struct mtk_cam_uapi_meta_raw_stats_cfg{} is useless, so drop it.
Regards,
CK
> + s8 ae_awb_enable;
> + s8 af_enable;
> + s8 dgn_enable;
> + s8 flk_enable;
> + s8 tsf_enable;
> + s8 wb_enable;
> + s8 pde_enable;
> + u8 rsv;
> +
> + struct mtk_cam_uapi_ae_param ae_param;
> + struct mtk_cam_uapi_awb_param awb_param;
> + struct mtk_cam_uapi_af_param af_param;
> + struct mtk_cam_uapi_dgn_param dgn_param;
> + struct mtk_cam_uapi_flk_param flk_param;
> + struct mtk_cam_uapi_tsf_param tsf_param;
> + struct mtk_cam_uapi_wb_param wb_param;
> + struct mtk_cam_uapi_pde_param pde_param;
> +
> + struct mtk_cam_uapi_prot {
> + /* The following top control are generated by script */
> + u8 drzh2n_r1_tuning_enable;
> + u8 drzh2n_r2_tuning_enable;
> + u8 drzh2n_r3_tuning_enable;
> + u8 drzh2n_r4_tuning_enable;
> + u8 drzh2n_r5_tuning_enable;
> + u8 drzh2n_r6_tuning_enable;
> + u8 drzh2n_r7_tuning_enable;
> + u8 drzh2n_r8_tuning_enable;
> + u8 drzs4n_r1_tuning_enable;
> + u8 drzs4n_r2_tuning_enable;
> + u8 drzs4n_r3_tuning_enable;
> + u8 dm_tuning_enable;
> + u8 drzs8t_r1_tuning_enable;
> + u8 drzs8t_r2_tuning_enable;
> + u8 ggm_r1_tuning_enable;
> + u8 ggm_r2_tuning_enable;
> + u8 ggm_r3_tuning_enable;
> + u8 bpc_r1_enable;
> + u8 bpc_r2_enable;
> + u8 ccm_r1_enable;
> + u8 ccm_r2_enable;
> + u8 ccm_r3_enable;
> + u8 fus_enable;
> + u8 g2c_r1_enable;
> + u8 g2c_r2_enable;
> + u8 g2c_r3_enable;
> + u8 hlr_enable;
> + u8 lsc_enable;
> + u8 ltm_enable;
> + u8 ltms_enable;
> + u8 obc_r1_enable;
> + u8 obc_r2_enable;
> + u8 tcy_r1_enable;
> + u8 tcy_r2_enable;
> + u8 tcy_r3_enable;
> + u8 tncs_r1_enable;
> +
> + struct mtk_cam_uapi_ccm_param_prot ccm_r1_param;
> + struct mtk_cam_uapi_ccm_param_prot ccm_r2_param;
> + struct mtk_cam_uapi_ccm_param_prot ccm_r3_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r1_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r2_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r3_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r4_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r5_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r6_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r7_param;
> + struct mtk_cam_uapi_drzh2n_param_prot drzh2n_r8_param;
> + struct mtk_cam_uapi_drzs4n_param_prot drzs4n_r1_param;
> + struct mtk_cam_uapi_drzs4n_param_prot drzs4n_r2_param;
> + struct mtk_cam_uapi_drzs4n_param_prot drzs4n_r3_param;
> + struct mtk_cam_uapi_tncs_param_prot tncs_param;
> + /* script generation done */
> + struct mtk_cam_uapi_drzs8t_param_prot drzs8t_r1_param;
> + struct mtk_cam_uapi_drzs8t_param_prot drzs8t_r2_param;
> + struct mtk_cam_uapi_awb_param_prot awb_param;
> + struct mtk_cam_uapi_bpc_param_prot bpc_param;
> + struct mtk_cam_uapi_lsc_param_prot lsc_param;
> + struct mtk_cam_uapi_slk_param_prot slk_param;
> + struct mtk_cam_uapi_wb_param_prot wb_param;
> + struct mtk_cam_uapi_ltms_param_prot ltms_param;
> + struct mtk_cam_uapi_yuvo_param_prot yuvo_r2_param;
> + struct mtk_cam_uapi_yuvo_param_prot yuvo_r4_param;
> + /* The following module stuctures are generated by script */
> + struct mtk_cam_uapi_regmap_raw_bpc bpc_r1;
> + struct mtk_cam_uapi_regmap_raw_bpc bpc_r2;
> + struct mtk_cam_uapi_regmap_raw_ccm ccm_r1;
> + struct mtk_cam_uapi_regmap_raw_ccm ccm_r2;
> + struct mtk_cam_uapi_regmap_raw_ccm ccm_r3;
> + struct mtk_cam_uapi_regmap_raw_dm dm_r1;
> + u8 rsv1[116];
> + struct mtk_cam_uapi_regmap_raw_g2c g2c_r1;
> + struct mtk_cam_uapi_regmap_raw_g2c g2c_r2;
> + struct mtk_cam_uapi_regmap_raw_g2c g2c_r3;
> + struct mtk_cam_uapi_regmap_raw_ggm ggm_r1;
> + struct mtk_cam_uapi_regmap_raw_ggm ggm_r2;
> + struct mtk_cam_uapi_regmap_raw_ggm ggm_r3;
> + u8 rsv2[68];
> + struct mtk_cam_uapi_regmap_raw_lsc lsc_r1;
> + struct mtk_cam_uapi_regmap_raw_ltm ltm_r1;
> + struct mtk_cam_uapi_regmap_raw_ltms ltms_r1;
> + struct mtk_cam_uapi_regmap_raw_obc obc_r1;
> + struct mtk_cam_uapi_regmap_raw_obc obc_r2;
> + u8 rsv3[1420];
> + struct mtk_cam_uapi_regmap_raw_tsfs tsfs_r1;
> + u8 rsv4[50080];
> + /* script generation done */
> + } __packed prot;
> +} __packed;
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-10-09 11:15 ` [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api Shu-hsiang Yang
2024-10-11 7:47 ` CK Hu (胡俊光)
@ 2024-10-14 5:56 ` CK Hu (胡俊光)
2024-11-06 13:04 ` Laurent Pinchart
2024-11-05 5:36 ` CK Hu (胡俊光)
2 siblings, 1 reply; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-14 5:56 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Add UAPI for MediaTek ISP platform, providing user-space
> interfaces for the new camsys driver.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +/* MTK ISP camsys controls */
> +#define V4L2_CID_MTK_CAM_USED_ENGINE_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 1)
> +#define V4L2_CID_MTK_CAM_BIN_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 2)
> +#define V4L2_CID_MTK_CAM_FRZ_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 3)
> +#define V4L2_CID_MTK_CAM_RESOURCE_PLAN_POLICY (V4L2_CID_USER_MTK_CAM_BASE + 4)
> +#define V4L2_CID_MTK_CAM_USED_ENGINE (V4L2_CID_USER_MTK_CAM_BASE + 5)
> +#define V4L2_CID_MTK_CAM_BIN (V4L2_CID_USER_MTK_CAM_BASE + 6)
> +#define V4L2_CID_MTK_CAM_FRZ (V4L2_CID_USER_MTK_CAM_BASE + 7)
> +#define V4L2_CID_MTK_CAM_USED_ENGINE_TRY (V4L2_CID_USER_MTK_CAM_BASE + 8)
> +#define V4L2_CID_MTK_CAM_BIN_TRY (V4L2_CID_USER_MTK_CAM_BASE + 9)
> +#define V4L2_CID_MTK_CAM_FRZ_TRY (V4L2_CID_USER_MTK_CAM_BASE + 10)
> +#define V4L2_CID_MTK_CAM_PIXEL_RATE (V4L2_CID_USER_MTK_CAM_BASE + 11)
> +#define V4L2_CID_MTK_CAM_FEATURE (V4L2_CID_USER_MTK_CAM_BASE + 12)
> +#define V4L2_CID_MTK_CAM_SYNC_ID (V4L2_CID_USER_MTK_CAM_BASE + 13)
> +#define V4L2_CID_MTK_CAM_RAW_PATH_SELECT (V4L2_CID_USER_MTK_CAM_BASE + 14)
> +#define V4L2_CID_MTK_CAM_HSF_EN (V4L2_CID_USER_MTK_CAM_BASE + 15)
> +#define V4L2_CID_MTK_CAM_PDE_INFO (V4L2_CID_USER_MTK_CAM_BASE + 16)
> +#define V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE (V4L2_CID_USER_MTK_CAM_BASE + 17)
> +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_CALC (V4L2_CID_USER_MTK_CAM_BASE + 18)
> +#define V4L2_CID_MTK_CAM_TG_FLASH_CFG (V4L2_CID_USER_MTK_CAM_BASE + 19)
> +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_UPDATE (V4L2_CID_USER_MTK_CAM_BASE + 20)
> +#define V4L2_CID_MTK_CAM_CAMSYS_HW_MODE (V4L2_CID_USER_MTK_CAM_BASE + 21)
> +
Please give introduction of how to use these user space interface.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
@ 2024-10-14 9:25 ` CK Hu (胡俊光)
2024-10-18 8:54 ` CK Hu (胡俊光)
` (8 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-14 9:25 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int set_test_model(struct seninf_ctx *ctx, char enable)
> +{
Without test code, this driver still work, so test code is advanced function.
Separate test code to a test patch.
Regards,
CK
> + struct seninf_vc *vc[] = { NULL, NULL, NULL, NULL, NULL };
> + int i = 0, ret = 0, vc_used = 0;
> + struct seninf_mux *mux;
> + int pref_idx[] = { 0, 1, 2, 3, 4 };
> +
> + if (ctx->is_test_model == 1) {
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
> + } else if (ctx->is_test_model == 2) {
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW1);
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW2);
> + } else if (ctx->is_test_model == 3) {
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_RAW0);
> + vc[vc_used++] = mtk_cam_seninf_get_vc_by_pad(ctx, PAD_SRC_PDAF0);
> + } else {
> + dev_info(ctx->dev, "testmodel%d invalid\n", ctx->is_test_model);
> + return -1;
> + }
> +
> + for (; i < vc_used; ++i) {
> + if (!vc[i]) {
> + dev_info(ctx->dev, "vc not found\n");
> + return -1;
> + }
> + }
> +
> + if (enable) {
> + ret = pm_runtime_resume_and_get(ctx->dev);
> + if (ret < 0) {
> + dev_info(ctx->dev, "failed at pm_runtime_resume_and_get\n");
> + return ret;
> + }
> +
> + if (ctx->core->clk[CLK_TOP_CAMTM])
> + ret = clk_prepare_enable(ctx->core->clk[CLK_TOP_CAMTM]);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < vc_used; ++i) {
> + mux = mtk_cam_seninf_mux_get_pref(ctx,
> + pref_idx,
> + ARRAY_SIZE(pref_idx));
> + if (!mux)
> + return -EBUSY;
> + vc[i]->mux = mux->idx;
> + vc[i]->cam = ctx->pad2cam[vc[i]->out_pad];
> + vc[i]->enable = 1;
> +
> + dev_info(ctx->dev,
> + "test mode mux %d, cam %d, pixel mode %d\n",
> + vc[i]->mux, vc[i]->cam, vc[i]->pixel_mode);
> +
> + mtk_cam_seninf_set_test_model(ctx, vc[i]->mux,
> + vc[i]->cam,
> + vc[i]->pixel_mode);
> +
> + if (vc[i]->out_pad == PAD_SRC_PDAF0)
> + mdelay(40);
> + else
> + usleep_range(40, 60);
> + }
> + } else {
> + mtk_cam_seninf_set_idle(ctx);
> + mtk_cam_seninf_release_mux(ctx);
> +
> + if (ctx->core->clk[CLK_TOP_CAMTM])
> + clk_disable_unprepare(ctx->core->clk[CLK_TOP_CAMTM]);
> +
> + pm_runtime_put_sync(ctx->dev);
> + }
> +
> + ctx->streaming = enable;
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-14 9:40 ` CK Hu (胡俊光)
2024-10-16 3:43 ` CK Hu (胡俊光)
` (11 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-14 9:40 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +static int mtk_cam_fill_img_buf(struct mtkcam_ipi_img_output *img_out,
> + const struct v4l2_format *f, dma_addr_t daddr)
> +{
> + u32 pixelformat = f->fmt.pix_mp.pixelformat;
> + u32 width = f->fmt.pix_mp.width;
> + u32 height = f->fmt.pix_mp.height;
> + const struct v4l2_plane_pix_format *plane = &f->fmt.pix_mp.plane_fmt[0];
> + u32 stride = plane->bytesperline;
> + u32 aligned_width;
> + unsigned int addr_offset = 0;
> + int i;
> +
> + if (is_mtk_format(pixelformat)) {
> + const struct mtk_format_info *info;
> +
> + info = mtk_format_info(pixelformat);
> + if (!info)
> + return -EINVAL;
> +
> + aligned_width = stride / info->bpp[0];
> + if (info->mem_planes == 1) {
> + if (is_yuv_ufo(pixelformat)) {
> + aligned_width = ALIGN(width, 64);
> + img_out->buf[0][0].iova = daddr;
> + img_out->fmt.stride[0] = aligned_width * info->bit_r_num
> + / info->bit_r_den;
> + img_out->buf[0][0].size = img_out->fmt.stride[0] * height;
> + img_out->buf[0][0].size += img_out->fmt.stride[0] * height / 2;
> + img_out->buf[0][0].size += ALIGN((aligned_width / 64), 8) * height;
> + img_out->buf[0][0].size += ALIGN((aligned_width / 64), 8) * height
> + / 2;
> + img_out->buf[0][0].size += sizeof(struct ufbc_buffer_header);
> +
> + pr_debug("plane:%d stride:%d plane_size:%d addr:0x%lx\n",
> + 0, img_out->fmt.stride[0], img_out->buf[0][0].size,
> + (unsigned long)img_out->buf[0][0].iova);
> + } else if (is_raw_ufo(pixelformat)) {
> + aligned_width = ALIGN(width, 64);
> + img_out->buf[0][0].iova = daddr;
> + img_out->fmt.stride[0] = aligned_width * info->bit_r_num /
> + info->bit_r_den;
> + img_out->buf[0][0].size = img_out->fmt.stride[0] * height;
> + img_out->buf[0][0].size += ALIGN((aligned_width / 64), 8) * height;
> + img_out->buf[0][0].size += sizeof(struct ufbc_buffer_header);
> +
> + pr_debug("plane:%d stride:%d plane_size:%d addr:0x%lx\n",
> + 0, img_out->fmt.stride[0],
> + img_out->buf[0][0].size,
> + (unsigned long)img_out->buf[0][0].iova);
> + } else {
> + for (i = 0; i < info->comp_planes; i++) {
> + unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
> + unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
> +
> + img_out->buf[0][i].iova = daddr + addr_offset;
> + img_out->fmt.stride[i] = info->bpp[i] *
> + DIV_ROUND_UP(aligned_width, hdiv);
> + img_out->buf[0][i].size = img_out->fmt.stride[i]
> + * DIV_ROUND_UP(height, vdiv);
> + addr_offset += img_out->buf[0][i].size;
> +
> + pr_debug("plane:%d stride:%d plane_size:%d addr:0x%lx\n",
> + i, img_out->fmt.stride[i],
> + img_out->buf[0][i].size,
> + (unsigned long)img_out->buf[0][i].iova);
> + }
> + }
> + } else {
> + pr_debug("do not support non contiguous mplane\n");
> + }
> + } else {
> + const struct v4l2_format_info *info;
> +
> + info = v4l2_format_info(pixelformat);
> + if (!info)
> + return -EINVAL;
> +
> + aligned_width = stride / info->bpp[0];
> + if (info->mem_planes == 1) {
> + for (i = 0; i < info->comp_planes; i++) {
This for-loop is identical with the for-loop in is_mtk_format-is-true block.
So the checking of is_mtk_format is redundant.
Regards,
CK
> + unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
> + unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
> +
> + img_out->buf[0][i].iova = daddr + addr_offset;
> + img_out->fmt.stride[i] = info->bpp[i] *
> + DIV_ROUND_UP(aligned_width, hdiv);
> + img_out->buf[0][i].size = img_out->fmt.stride[i]
> + * DIV_ROUND_UP(height, vdiv);
> + addr_offset += img_out->buf[0][i].size;
> +
> + pr_debug("stride:%d plane_size:%d addr:0x%lx\n",
> + img_out->fmt.stride[i],
> + img_out->buf[0][i].size,
> + (unsigned long)img_out->buf[0][i].iova);
> + }
> + } else {
> + pr_debug("do not support non contiguous mplane\n");
> + }
> + }
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 00/10] Add MediaTek ISP7 camera system driver
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
` (5 preceding siblings ...)
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-15 18:40 ` Nicolas Dufresne
[not found] ` <20241009111551.27052-9-Shu-hsiang.Yang@mediatek.com>
` (4 subsequent siblings)
11 siblings, 0 replies; 88+ messages in thread
From: Nicolas Dufresne @ 2024-10-15 18:40 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
Hi,
Le mercredi 09 octobre 2024 à 19:15 +0800, Shu-hsiang Yang a écrit :
> Based on linux-next/master, tag: next-20241008
>
> The patch set adds the MediaTek ISP7.x camera system hardware driver.
>
> This driver sets up ISP hardware, handles interrupts, and initializes
> V4L2 device nodes and functions. Moreover, implement V4L2 standard
> video driver that utilizes media framework APIs. It also connects
> the sensors and ISP, bridging with the seninf interface. Communicate
> with SCP co-processor to compose ISP registers in the firmware.
Thanks for this work. If I read you correctly, this will depends on an scp
firmware update. Its probably early at rev1, but we appreciate if you can cross-
reference your associated linux-firmware submission (or document which MT
flavour of SCP firmware) contains this support already.
For ISP drivers reviewers, we have the experience with SCP that the IPC is not
versioned, making it difficult to maintain backward compatibility. Won't matter
until this is merged, but be aware that unless this SCP IPC design issue has
been fixed, any change to the -if headers means a modification to the SCP has
been made, and often we have had to ask MTK to revisit the firmware code to
unbreak backward compatibility.
If this specific part of the SCP IPC is versioned, please let us know. I don't
want this to be alarming message, just something we need to collectively be
aware of not to break userspace, which may not update their firmwares in lock
step with the kernel.
regards,
Nicolas
p.s. for those new to MTK architecture, the SCP firmware provides services to
everything multimedia in the platform, including CODECs, color converter and
scalers, etc.
>
> These patches include CSI received data from sensors, sensor interface
> bridge, raw/YUV image pre-processing, ISP utility and ISP control parts.
>
> Thank you for reviewing these patches.
>
> Shu-hsiang Yang (10):
> dt-bindings: media: mediatek: add camsys device
> media: platform: mediatek: add seninf controller
> media: platform: mediatek: add isp_7x seninf unit
> media: platform: mediatek: add isp_7x cam-raw unit
> media: platform: mediatek: add isp_7x camsys unit
> media: platform: mediatek: add isp_7x utility
> media: platform: mediatek: add isp_7x video ops
> media: platform: mediatek: add isp_7x state ctrl
> media: platform: mediatek: add isp_7x build config
> uapi: linux: add mediatek isp_7x camsys user api
>
> .../media/mediatek/mediatek,cam-raw.yaml | 169 +
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +
> .../media/mediatek/mediatek,camisp.yaml | 71 +
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +
> .../media/mediatek/mediatek,seninf.yaml | 88 +
> drivers/media/platform/mediatek/Kconfig | 1 +
> drivers/media/platform/mediatek/Makefile | 2 +
> drivers/media/platform/mediatek/isp/Kconfig | 21 +
> .../platform/mediatek/isp/isp_7x/Makefile | 7 +
> .../mediatek/isp/isp_7x/camsys/Makefile | 16 +
> .../isp_7x/camsys/kd_imgsensor_define_v4l2.h | 87 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c | 1797 ++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h | 140 +
> .../isp/isp_7x/camsys/mtk_cam-debug.c | 1271 ++++
> .../isp/isp_7x/camsys/mtk_cam-debug.h | 273 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-defs.h | 168 +
> .../isp/isp_7x/camsys/mtk_cam-dmadbg.h | 721 +++
> .../isp/isp_7x/camsys/mtk_cam-feature.c | 40 +
> .../isp/isp_7x/camsys/mtk_cam-feature.h | 26 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h | 87 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h | 233 +
> .../isp/isp_7x/camsys/mtk_cam-meta-mt8188.h | 2436 ++++++++
> .../isp/isp_7x/camsys/mtk_cam-plat-util.c | 207 +
> .../isp/isp_7x/camsys/mtk_cam-plat-util.h | 16 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.c | 393 ++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.h | 28 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 +
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 +
> .../isp/isp_7x/camsys/mtk_cam-regs-mt8188.h | 382 ++
> .../isp/isp_7x/camsys/mtk_cam-seninf-def.h | 193 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-drv.c | 1741 ++++++
> .../isp/isp_7x/camsys/mtk_cam-seninf-drv.h | 16 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-hw.h | 120 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-if.h | 28 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-regs.h | 40 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-route.c | 356 ++
> .../isp/isp_7x/camsys/mtk_cam-seninf-route.h | 23 +
> .../isp/isp_7x/camsys/mtk_cam-seninf.h | 170 +
> .../isp/isp_7x/camsys/mtk_cam-timesync.c | 125 +
> .../isp/isp_7x/camsys/mtk_cam-timesync.h | 12 +
> .../isp/isp_7x/camsys/mtk_cam-ufbc-def.h | 59 +
> .../isp/isp_7x/camsys/mtk_cam-video.c | 1817 ++++++
> .../isp/isp_7x/camsys/mtk_cam-video.h | 224 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam.c | 4168 +++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam.h | 733 +++
> .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 +
> .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 +++
> .../mtk_cam-seninf-csi0-cphy.h | 69 +
> .../mtk_cam-seninf-csi0-dphy.h | 139 +
> .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++
> .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 +
> .../mtk_cam-seninf-seninf1-csi2.h | 415 ++
> .../mtk_cam-seninf-seninf1-mux.h | 147 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 +
> include/uapi/linux/mtkisp_camsys.h | 227 +
> 60 files changed, 30194 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-defs.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-dmadbg.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-meta-mt8188.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-regs-mt8188.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ufbc-def.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h
> create mode 100644 include/uapi/linux/mtkisp_camsys.h
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl
[not found] ` <20241009111551.27052-9-Shu-hsiang.Yang@mediatek.com>
@ 2024-10-16 1:35 ` CK Hu (胡俊光)
2024-10-28 5:20 ` CK Hu (胡俊光)
2024-10-28 5:34 ` CK Hu (胡俊光)
2 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-16 1:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces state management and debugging mechanisms for the MediaTek
> ISP7.x camsys platform. State management establishes control over ISP
> operations and events, defining distinct states for request handling,
> sensor control, and frame synchronization, ensuring event processing.
> The debugging mechanism ensures stable operation and timely data
> collection during anomalies.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static bool mtk_cam_req_frame_sync_start(struct mtk_cam_request *req)
> +{
> + /* All ctx with sensor is in ready state */
> + struct mtk_cam_device *cam =
> + container_of(req->req.mdev, struct mtk_cam_device, media_dev);
> + struct mtk_cam_ctx *ctx;
> + struct mtk_cam_ctx *sync_ctx[MTKCAM_SUBDEV_MAX];
> + int i;
> + u32 ctx_cnt = 0, synced_cnt = 0;
> + bool ret = false;
> +
> + /* pick out the used ctxs */
> + for (i = 0; i < cam->max_stream_num; i++) {
> + if (!(1 << i & req->ctx_used))
> + continue;
> +
> + sync_ctx[ctx_cnt] = &cam->ctxs[i];
> + ctx_cnt++;
> + }
> +
> + mutex_lock(&req->fs.op_lock);
> + if (ctx_cnt > 1) {
> + /* multi sensor case */
multi sensor is advanced function, so separate multi sensor related code to a multi sensor patch.
Regards,
CK
> + req->fs.on_cnt++;
> + /* not first time */
> + if (req->fs.on_cnt != 1)
> + goto EXIT;
> +
> + for (i = 0; i < ctx_cnt; i++) {
> + ctx = sync_ctx[i];
> + spin_lock(&ctx->streaming_lock);
> + if (!ctx->streaming) {
> + spin_unlock(&ctx->streaming_lock);
> + dev_info(cam->dev,
> + "%s: ctx(%d): is streamed off\n",
> + __func__, ctx->stream_id);
> + continue;
> + }
> + spin_unlock(&ctx->streaming_lock);
> +
> + /* update sensor frame sync */
> + if (ctx->synced)
> + synced_cnt++;
> + }
> +
> + /*
> + * the prepared sensor is no enough, skip
> + * frame sync set failed or stream off
> + */
> + if (synced_cnt < 2) {
> + mtk_cam_fs_reset(&req->fs);
> + dev_info(cam->dev, "%s:%s: sensor is not ready\n",
> + __func__, req->req.debug_str);
> + goto EXIT;
> + }
> +
> + dev_dbg(cam->dev, "%s:%s:fs_sync_frame(1): ctxs: 0x%x\n",
> + __func__, req->req.debug_str, req->ctx_used);
> +
> + ret = true;
> + goto EXIT;
> + }
> + /* single sensor case: unsupported sensor hardware sync */
> +
> +EXIT:
> + dev_dbg(cam->dev, "%s:%s:target/on/off(%d/%d/%d)\n", __func__,
> + req->req.debug_str, req->fs.target, req->fs.on_cnt,
> + req->fs.off_cnt);
> + mutex_unlock(&req->fs.op_lock);
> + return ret;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config
2024-10-09 11:15 ` [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config Shu-hsiang Yang
@ 2024-10-16 1:56 ` CK Hu (胡俊光)
0 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-16 1:56 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Add Kconfig and Makefile to include MTK ISP CAMSYS, integrating
> the driver into the kernel build and configuration process.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +subdir-ccflags-y += -Werror
> +
> +subdir-ccflags-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += -DISP7_1
> +
> +obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += camsys/
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
> new file mode 100644
> index 000000000000..8e758cf6877f
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (C) 2022 MediaTek Inc.
> +
> +mtk-cam-isp-objs := mtk_cam.o mtk_cam-raw.o mtk_cam-pool.o \
> + mtk_cam-video.o mtk_cam-ctrl.o \
> + mtk_cam-seninf-route.o mtk_cam-seninf-drv.o \
When you add mtk_cam-seninf-route.c and mtk_cam-seninf-drv.c in patch [3/10],
you should create this Makefile so these two .c file could be compiled.
Regards,
CK
> + mtk_cam-debug.o \
> + mtk_cam-raw_debug.o \
> + mtk_cam-feature.o mtk_cam-timesync.o
> +
> +mtk-cam-plat-util-objs := mtk_cam-plat-util.o
> +
> +include $(src)/mtk_csi_phy_2_0/Makefile
> +
> +obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += mtk-cam-plat-util.o
> +obj-$(CONFIG_VIDEO_MTK_ISP_71_CAMSYS) += mtk-cam-isp.o
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
2024-10-14 9:40 ` [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit CK Hu (胡俊光)
@ 2024-10-16 3:43 ` CK Hu (胡俊光)
2024-11-19 5:56 ` CK Hu (胡俊光)
2024-10-22 5:44 ` Krzysztof Kozlowski
` (10 subsequent siblings)
12 siblings, 1 reply; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-16 3:43 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int mtk_cam_probe(struct platform_device *pdev)
> +{
> + struct mtk_cam_device *cam_dev;
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + int ret;
> + unsigned int i;
> +
> + dev_dbg(dev, "camsys | start %s\n", __func__);
> +
> + /* initialize structure */
> + cam_dev = devm_kzalloc(dev, sizeof(*cam_dev), GFP_KERNEL);
> + if (!cam_dev)
> + return -ENOMEM;
> +
> + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) {
> + dev_err(dev, "%s: No suitable DMA available\n", __func__);
> + return -EIO;
> + }
> +
> + if (!dev->dma_parms) {
> + dev->dma_parms =
> + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
> + if (!dev->dma_parms)
> + return -ENOMEM;
> + }
> +
> + dma_set_max_seg_size(dev, UINT_MAX);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get mem\n");
> + return -ENODEV;
> + }
> +
> + cam_dev->base = devm_ioremap_resource(dev, res);
I can not find any where to write register of this device.
If so, I think we need not to probe this driver.
The rest software control can be setup by other driver.
Regards,
CK
> + if (IS_ERR(cam_dev->base)) {
> + dev_err(dev, "failed to map register base\n");
> + return PTR_ERR(cam_dev->base);
> + }
> +
> + cam_dev->dev = dev;
> + dev_set_drvdata(dev, cam_dev);
> +
> + cam_dev->composer_cnt = 0;
> + cam_dev->num_seninf_devices = 0;
> +
> + cam_dev->max_stream_num = MTKCAM_SUBDEV_MAX;
> + cam_dev->ctxs = devm_kcalloc(dev, cam_dev->max_stream_num,
> + sizeof(*cam_dev->ctxs), GFP_KERNEL);
> + if (!cam_dev->ctxs)
> + return -ENOMEM;
> +
> + cam_dev->streaming_ctx = 0;
> + for (i = 0; i < cam_dev->max_stream_num; i++)
> + mtk_cam_ctx_init(cam_dev->ctxs + i, cam_dev, i);
> +
> + cam_dev->running_job_count = 0;
> + spin_lock_init(&cam_dev->pending_job_lock);
> + spin_lock_init(&cam_dev->running_job_lock);
> + INIT_LIST_HEAD(&cam_dev->pending_job_list);
> + INIT_LIST_HEAD(&cam_dev->running_job_list);
> +
> + cam_dev->dma_processing_count = 0;
> + spin_lock_init(&cam_dev->dma_pending_lock);
> + spin_lock_init(&cam_dev->dma_processing_lock);
> + INIT_LIST_HEAD(&cam_dev->dma_pending);
> + INIT_LIST_HEAD(&cam_dev->dma_processing);
> +
> + mutex_init(&cam_dev->queue_lock);
> +
> + pm_runtime_enable(dev);
> +
> + ret = mtk_cam_of_rproc(cam_dev, pdev);
> + if (ret)
> + goto fail_destroy_mutex;
> +
> + ret = register_sub_drivers(dev);
> + if (ret) {
> + dev_err(dev, "fail to register_sub_drivers\n");
> + goto fail_destroy_mutex;
> + }
> +
> + /* register mtk_cam as all isp subdev async parent */
> + cam_dev->notifier.ops = &mtk_cam_async_nf_ops;
> + v4l2_async_nf_init(&cam_dev->notifier, &cam_dev->v4l2_dev);
> + ret = mtk_cam_async_subdev_add(dev); /* wait all isp sub drivers */
> + if (ret) {
> + dev_err(dev, "%s failed mtk_cam_async_subdev_add\n", __func__);
> + goto fail_unregister_sub_drivers;
> + }
> +
> + ret = v4l2_async_nf_register(&cam_dev->notifier);
> + if (ret) {
> + dev_err(dev, "%s async_nf_register ret:%d\n", __func__, ret);
> + v4l2_async_nf_cleanup(&cam_dev->notifier);
> + goto fail_unregister_sub_drivers;
> + }
> +
> + ret = mtk_cam_debug_fs_init(cam_dev);
> + if (ret < 0)
> + goto fail_unregister_async_nf;
> +
> + dev_info(dev, "camsys | [%s] success\n", __func__);
> +
> + return 0;
> +
> +fail_unregister_async_nf:
> + v4l2_async_nf_unregister(&cam_dev->notifier);
> +
> +fail_unregister_sub_drivers:
> + unregister_sub_drivers(dev);
> +
> +fail_destroy_mutex:
> + mutex_destroy(&cam_dev->queue_lock);
> +
> + return ret;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
2024-10-14 9:25 ` CK Hu (胡俊光)
@ 2024-10-18 8:54 ` CK Hu (胡俊光)
2024-10-28 1:27 ` CK Hu (胡俊光)
` (7 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-18 8:54 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static ssize_t debug_ops_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
Separate debug related code to debug patch.
> + int len = 0;
> +
> + len += snprintf(buf + len, PAGE_SIZE - len, "This is debug ops message\n");
> +
> + return len;
> +}
> +
> +enum REG_OPS_CMD {
> + REG_OPS_CMD_ID,
> + REG_OPS_CMD_CSI,
> + REG_OPS_CMD_RG,
> + REG_OPS_CMD_VAL,
> + REG_OPS_CMD_MAX_NUM,
> +};
> +
> +static ssize_t debug_ops_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
Ditto.
Regards,
CK
> + char delim[] = " ";
> + char csi_names[20];
> + char *token = NULL;
> + char *sbuf = kcalloc(count + 1, sizeof(char), GFP_KERNEL);
> + char *s = sbuf;
> + int ret;
> + char *arg[REG_OPS_CMD_MAX_NUM];
> + struct seninf_core *core = dev_get_drvdata(dev);
> + struct seninf_ctx *ctx;
> + int csi_port = -1;
> + int rg_idx = -1;
> + u32 val, i, num_para = 0;
> +
> + if (!sbuf)
> + goto ERR_DEBUG_OPS_STORE;
> +
> + memcpy(sbuf, buf, count);
> +
> + token = strsep(&s, delim);
> + while (token && num_para < REG_OPS_CMD_MAX_NUM) {
> + if (strlen(token)) {
> + arg[num_para] = token;
> + num_para++;
> + }
> +
> + token = strsep(&s, delim);
> + }
> +
> + if (num_para != REG_OPS_CMD_MAX_NUM) {
> + dev_info(dev, "Wrong command parameter number\n");
> + goto ERR_DEBUG_OPS_STORE;
> + }
> +
> + if (strncmp("SET_REG", arg[REG_OPS_CMD_ID], sizeof("SET_REG")) == 0) {
> + for (i = 0; i < REG_KEY_MAX_NUM; i++) {
> + if (!strcasecmp(arg[REG_OPS_CMD_RG], set_reg_names[i]))
> + rg_idx = i;
> + }
> + if (rg_idx < 0)
> + goto ERR_DEBUG_OPS_STORE;
> +
> + ret = kstrtouint(arg[REG_OPS_CMD_VAL], 0, &val);
> + if (ret)
> + goto ERR_DEBUG_OPS_STORE;
> +
> + for (i = 0; i < CSI_PORT_MAX_NUM; i++) {
> + memset(csi_names, 0, ARRAY_SIZE(csi_names));
> + snprintf(csi_names, 10, "csi-%s", csi_port_names[i]);
> + if (!strcasecmp(arg[REG_OPS_CMD_CSI], csi_names))
> + csi_port = i;
> + }
> +
> + if (csi_port < 0)
> + goto ERR_DEBUG_OPS_STORE;
> +
> + /* reg call */
> + mutex_lock(&core->mutex);
> +
> + list_for_each_entry(ctx, &core->list, list) {
> + if (csi_port == ctx->port)
> + mtk_cam_seninf_set_reg(ctx, rg_idx, val);
> + }
> +
> + mutex_unlock(&core->mutex);
> + }
> +
> +ERR_DEBUG_OPS_STORE:
> +
> + kfree(sbuf);
> +
> + return count;
> +}
> +
> +static DEVICE_ATTR_RW(debug_ops);
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
` (2 preceding siblings ...)
2024-10-11 2:38 ` CK Hu (胡俊光)
@ 2024-10-22 4:16 ` CK Hu (胡俊光)
2024-10-28 1:55 ` CK Hu (胡俊光)
4 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-22 4:16 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +int mtk_cam_seninf_init_iomem(struct seninf_ctx *ctx, void __iomem *if_base,
> + void __iomem *ana_base)
> +{
This function is defined in this patch but only used by patch [3/10].
There are many function defined in this patch but used only in patch [3/10].
I think this patch and patch [3/10] should be merged into one patch which is a complete sensor interface driver.
To prevent this patch to be too big, separate advanced function to another patches.
Regards,
CK
> + u32 i;
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_0] =
> + ctx->reg_ana_csi_rx[CSI_PORT_0A] = ana_base + 0;
> + ctx->reg_ana_csi_rx[CSI_PORT_0B] = ana_base + 0x1000;
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_1] =
> + ctx->reg_ana_csi_rx[CSI_PORT_1A] = ana_base + 0x4000;
> + ctx->reg_ana_csi_rx[CSI_PORT_1B] = ana_base + 0x5000;
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_2] =
> + ctx->reg_ana_csi_rx[CSI_PORT_2A] = ana_base + 0x8000;
> + ctx->reg_ana_csi_rx[CSI_PORT_2B] = ana_base + 0x9000;
> +
> + ctx->reg_ana_csi_rx[CSI_PORT_3] =
> + ctx->reg_ana_csi_rx[CSI_PORT_3A] = ana_base + 0xc000;
> + ctx->reg_ana_csi_rx[CSI_PORT_3B] = ana_base + 0xd000;
> +
> + ctx->reg_ana_dphy_top[CSI_PORT_0A] =
> + ctx->reg_ana_dphy_top[CSI_PORT_0B] =
> + ctx->reg_ana_dphy_top[CSI_PORT_0] = ana_base + 0x2000;
> +
> + ctx->reg_ana_dphy_top[CSI_PORT_1A] =
> + ctx->reg_ana_dphy_top[CSI_PORT_1B] =
> + ctx->reg_ana_dphy_top[CSI_PORT_1] = ana_base + 0x6000;
> +
> + ctx->reg_ana_dphy_top[CSI_PORT_2A] =
> + ctx->reg_ana_dphy_top[CSI_PORT_2B] =
> + ctx->reg_ana_dphy_top[CSI_PORT_2] = ana_base + 0xa000;
> +
> + ctx->reg_ana_dphy_top[CSI_PORT_3A] =
> + ctx->reg_ana_dphy_top[CSI_PORT_3B] =
> + ctx->reg_ana_dphy_top[CSI_PORT_3] = ana_base + 0xe000;
> +
> + ctx->reg_ana_cphy_top[CSI_PORT_0A] =
> + ctx->reg_ana_cphy_top[CSI_PORT_0B] =
> + ctx->reg_ana_cphy_top[CSI_PORT_0] = ana_base + 0x3000;
> +
> + ctx->reg_ana_cphy_top[CSI_PORT_1A] =
> + ctx->reg_ana_cphy_top[CSI_PORT_1B] =
> + ctx->reg_ana_cphy_top[CSI_PORT_1] = ana_base + 0x7000;
> +
> + ctx->reg_ana_cphy_top[CSI_PORT_2A] =
> + ctx->reg_ana_cphy_top[CSI_PORT_2B] =
> + ctx->reg_ana_cphy_top[CSI_PORT_2] = ana_base + 0xb000;
> +
> + ctx->reg_ana_cphy_top[CSI_PORT_3A] =
> + ctx->reg_ana_cphy_top[CSI_PORT_3B] =
> + ctx->reg_ana_cphy_top[CSI_PORT_3] = ana_base + 0xf000;
> +
> + ctx->reg_if_top = if_base;
> +
> + for (i = SENINF_1; i < _seninf_cfg.seninf_num; i++) {
> + ctx->reg_if_ctrl[i] = if_base + 0x0200 + (0x1000 * i);
> + ctx->reg_if_tg[i] = if_base + 0x0F00 + (0x1000 * i);
> + ctx->reg_if_csi2[i] = if_base + 0x0a00 + (0x1000 * i);
> + }
> +
> + for (i = SENINF_MUX1; i < _seninf_cfg.mux_num; i++)
> + ctx->reg_if_mux[i] = if_base + 0x0d00 + (0x1000 * i);
> +
> + ctx->reg_if_cam_mux = if_base + 0x0400;
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
2024-10-14 5:21 ` [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility CK Hu (胡俊光)
@ 2024-10-22 5:30 ` CK Hu (胡俊光)
2024-10-28 3:46 ` CK Hu (胡俊光)
` (14 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-22 5:30 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * A U T O W H I T E B A L A N C E
> + */
> +
> +/* Maximum blocks that MediaTek AWB supports */
> +#define MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM (10)
> +
> +/*
> + * struct mtk_cam_uapi_awb_param - parameters for AWB configurtion
> + *
> + * @stat_en: AWB stat enable
> + * @windownum_x: Number of horizontal AWB windows
> + * @windownum_y: Number of vertical AWB windows
> + * @lowthreshold_r: Low threshold of R
> + * @lowthreshold_g: Low threshold of G
> + * @lowthreshold_b: Low threshold of B
> + * @highthreshold_r: High threshold of R
> + * @highthreshold_g: High threshold of G
> + * @highthreshold_b: High threshold of B
> + * @lightsrc_lowthreshold_r: Low threshold of R for light source estimation
> + * @lightsrc_lowthreshold_g: Low threshold of G for light source estimation
> + * @lightsrc_lowthreshold_b: Low threshold of B for light source estimation
> + * @lightsrc_highthreshold_r: High threshold of R for light source estimation
> + * @lightsrc_highthreshold_g: High threshold of G for light source estimation
> + * @lightsrc_highthreshold_b: High threshold of B for light source estimation
> + * @pregainlimit_r: Maximum limit clipping for R color
> + * @pregainlimit_g: Maximum limit clipping for G color
> + * @pregainlimit_b: Maximum limit clipping for B color
> + * @pregain_r: unit module compensation gain for R color
> + * @pregain_g: unit module compensation gain for G color
> + * @pregain_b: unit module compensation gain for B color
> + * @valid_datawidth: valid bits of statistic data
> + * @hdr_support_en: support HDR mode
> + * @stat_mode: Output format select <1>sum mode <0>average mode
> + * @error_ratio: Programmable error pixel count by AWB window size
> + * (base : 256)
> + * @awbxv_win_r: light area of right bound, the size is defined in
> + * MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM
> + * @awbxv_win_l: light area of left bound the size is defined in
> + * MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM
> + * @awbxv_win_d: light area of lower bound the size is defined in
> + * MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM
> + * @awbxv_win_u: light area of upper bound the size is defined in
> + * MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM
> + * @pregain2_r: white balance gain of R color
> + * @pregain2_g: white balance gain of G color
> + * @pregain2_b: white balance gain of B color
> + */
> +struct mtk_cam_uapi_awb_param {
> + u32 stat_en;
> + u32 windownum_x;
windownum_x is useless, so drop it.
Regards,
CK
> + u32 windownum_y;
> + u32 lowthreshold_r;
> + u32 lowthreshold_g;
> + u32 lowthreshold_b;
> + u32 highthreshold_r;
> + u32 highthreshold_g;
> + u32 highthreshold_b;
> + u32 lightsrc_lowthreshold_r;
> + u32 lightsrc_lowthreshold_g;
> + u32 lightsrc_lowthreshold_b;
> + u32 lightsrc_highthreshold_r;
> + u32 lightsrc_highthreshold_g;
> + u32 lightsrc_highthreshold_b;
> + u32 pregainlimit_r;
> + u32 pregainlimit_g;
> + u32 pregainlimit_b;
> + u32 pregain_r;
> + u32 pregain_g;
> + u32 pregain_b;
> + u32 valid_datawidth;
> + u32 hdr_support_en;
> + u32 stat_mode;
> + u32 format_shift;
> + u32 error_ratio;
> + u32 postgain_r;
> + u32 postgain_g;
> + u32 postgain_b;
> + u32 postgain2_hi_r;
> + u32 postgain2_hi_g;
> + u32 postgain2_hi_b;
> + u32 postgain2_med_r;
> + u32 postgain2_med_g;
> + u32 postgain2_med_b;
> + u32 postgain2_low_r;
> + u32 postgain2_low_g;
> + u32 postgain2_low_b;
> + s32 awbxv_win_r[MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM];
> + s32 awbxv_win_l[MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM];
> + s32 awbxv_win_d[MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM];
> + s32 awbxv_win_u[MTK_CAM_UAPI_AWB_MAX_LIGHT_AREA_NUM];
> + u32 csc_ccm[9];
> + u32 acc;
> + u32 med_region[4];
> + u32 low_region[4];
> + u32 pregain2_r;
> + u32 pregain2_g;
> + u32 pregain2_b;
> +} __packed;
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
` (2 preceding siblings ...)
2024-10-11 3:20 ` CK Hu (胡俊光)
@ 2024-10-22 5:36 ` Krzysztof Kozlowski
2024-11-11 1:37 ` CK Hu (胡俊光)
2024-11-11 2:38 ` CK Hu (胡俊光)
5 siblings, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-22 5:36 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
On 09/10/2024 13:15, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
> .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
> .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
> 5 files changed, 582 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> new file mode 100644
> index 000000000000..c709e4bf0a18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
Drop blank line
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
SoC specific compatible instead. I see Rob gave you review, so few more
points.
...
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
Drop assigned-clock*
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
e.g. isp
Also, underscores are not allowed in node names. Please do not send to
us your downstream code. Read DTS coding style and write code maching
upstream style.
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
Messed alignment.
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
Also misaligned.
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
Also misaligned.
All comments apply to other files as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (4 preceding siblings ...)
2024-10-11 6:03 ` CK Hu (胡俊光)
@ 2024-10-22 5:43 ` Krzysztof Kozlowski
2024-10-22 6:14 ` CK Hu (胡俊光)
` (7 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-22 5:43 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
On 09/10/2024 13:15, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
...
> +
> +static int mtk_yuv_of_probe(struct platform_device *pdev,
> + struct mtk_yuv_device *drvdata)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + int irq, ret;
> + int n_clks;
> +
> + ret = of_property_read_u32(dev->of_node, "mediatek,cam-id",
> + &drvdata->id);
> + if (ret) {
> + dev_dbg(dev, "missing camid property\n");
Debug? Or error?
> + return ret;
> + }
> +
> + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) {
> + dev_err(dev, "%s: No suitable DMA available\n", __func__);
> + return -EIO;
> + }
> +
> + if (!dev->dma_parms) {
> + dev->dma_parms =
> + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
> + if (!dev->dma_parms)
> + return -ENOMEM;
> + }
> +
> + dma_set_max_seg_size(dev, UINT_MAX);
> +
> + /* base outer register */
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
> + if (!res) {
> + dev_err(dev, "failed to get mem\n");
> + return -ENODEV;
> + }
> +
> + drvdata->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(drvdata->base)) {
> + dev_dbg(dev, "failed to map register base\n");
Dbg? What?
> + return PTR_ERR(drvdata->base);
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(dev, "failed to get irq\n");
> + return -ENODEV;
> + }
> +
> + ret = devm_request_irq(dev, irq, mtk_irq_yuv, 0,
> + dev_name(dev), drvdata);
> + if (ret) {
> + dev_err(dev, "failed to request irq=%d\n", irq);
> + return ret;
> + }
> + dev_dbg(dev, "registered irq=%d\n", irq);
Drop
> +
> + n_clks = devm_clk_bulk_get_all(dev, &drvdata->clk_b);
> + if (n_clks < 0) {
> + dev_err(dev, "failed to devm_clk_bulk_get_all=%d\n", n_clks);
Syntax is: return dev_err_probe()
> + return n_clks;
> + }
> +
> + drvdata->num_clks = n_clks;
> + dev_info(dev, "clk_num:%d\n", drvdata->num_clks);
Drop
> +
> +#ifdef CONFIG_PM_SLEEP
> + drvdata->pm_notifier.notifier_call = yuv_pm_notifier;
> + ret = register_pm_notifier(&drvdata->pm_notifier);
> + if (ret) {
> + dev_err(dev, "failed to register notifier block.\n");
> + return ret;
> + }
> +#endif
> +
> + return 0;
> +}
> +
> +static int mtk_yuv_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_yuv_device *drvdata;
> + struct v4l2_subdev *sd;
> + int ret;
> +
> + dev_dbg(dev, "camsys | start %s\n", __func__);
NAK
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> +
> + drvdata->dev = dev;
> + dev_set_drvdata(dev, drvdata);
> +
> + ret = mtk_yuv_of_probe(pdev, drvdata);
> + if (ret) {
> + dev_info(dev, "mtk_yuv_of_probe failed\n");
NAK. Neither info nor proper for memory allocation errors. Drop.
> + return ret;
> + }
> +
> + /* register yuv as mtk_cam async child */
> + sd = &drvdata->subdev;
> + v4l2_subdev_init(sd, &mtk_raw_subdev_ops);
> + sd->internal_ops = &mtk_raw_subdev_internal_ops;
> + snprintf(sd->name, sizeof(sd->name), "%s",
> + of_node_full_name(dev->of_node));
> + sd->dev = dev;
> + sd->owner = THIS_MODULE;
> +
> + ret = v4l2_async_register_subdev(sd);
> + if (ret) {
> + dev_err(dev, "%s failed on async_register_subdev\n", __func__);
> + return ret;
> + }
> +
> + pm_runtime_enable(dev);
> +
> + dev_info(dev, "camsys | [%s] success\n", __func__);
NAK
> +
> + return 0;
> +}
> +
> +static void mtk_yuv_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_yuv_device *yuv_dev = dev_get_drvdata(dev);
> + struct v4l2_subdev *sd = &yuv_dev->subdev;
> +
> + dev_dbg(dev, "camsys | start %s\n", __func__);
NAK
> +
> + unregister_pm_notifier(&yuv_dev->pm_notifier);
> +
> + pm_runtime_disable(dev);
> +
> + v4l2_async_unregister_subdev(sd);
> +}
> +
> +/* driver for yuv part */
> +static int mtk_yuv_runtime_suspend(struct device *dev)
> +{
> + struct mtk_yuv_device *drvdata = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s:disable clock\n", __func__);
NAK
> +
> + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clk_b);
> +
> + return 0;
> +}
> +
> +static int mtk_yuv_runtime_resume(struct device *dev)
> +{
> + struct mtk_yuv_device *drvdata = dev_get_drvdata(dev);
> + int ret;
> +
> + dev_info(dev, "%s:enable clock\n", __func__);
NAK. Not even dev_dbg. Please don't ever post such code.
> +
> + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clk_b);
> + if (ret) {
> + dev_info(dev, "failed at clk_bulk_prepare_enable, ret = %d\n", ret);
> + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clk_b);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops mtk_yuv_pm_ops = {
> + SET_RUNTIME_PM_OPS(mtk_yuv_runtime_suspend, mtk_yuv_runtime_resume,
> + NULL)
> +};
> +
> +static const struct of_device_id mtk_yuv_of_ids[] = {
> + {.compatible = "mediatek,cam-yuv",},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, mtk_yuv_of_ids);
> +
> +struct platform_driver mtk_cam_yuv_driver = {
> + .probe = mtk_yuv_probe,
> + .remove = mtk_yuv_remove,
> + .driver = {
> + .name = "mtk-cam yuv",
> + .of_match_table = of_match_ptr(mtk_yuv_of_ids),
Drop of_match_ptr(), you will have here warnings.
> + .pm = &mtk_yuv_pm_ops,
> + }
> +};
...
> diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
> new file mode 100644
> index 000000000000..b775e6c30aa1
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_CAMERA_V4l2_CONTROLS_H
> +#define __MTK_CAMERA_V4l2_CONTROLS_H
> +
> +#include <linux/videodev2.h>
> +#include <linux/v4l2-controls.h>
> +#include <linux/mtkisp_camsys.h>
How these headers are used here? I don't see. Don't include unrelated
stuff in your files.
> +
> +/* Allowed value of V4L2_CID_MTK_CAM_RAW_PATH_SELECT */
> +#define V4L2_MTK_CAM_RAW_PATH_SELECT_BPC 1
> +#define V4L2_MTK_CAM_RAW_PATH_SELECT_FUS 3
> +#define V4L2_MTK_CAM_RAW_PATH_SELECT_DGN 4
> +#define V4L2_MTK_CAM_RAW_PATH_SELECT_LSC 5
> +#define V4L2_MTK_CAM_RAW_PATH_SELECT_LTM 7
> +
> +#define V4L2_MBUS_FRAMEFMT_PAD_ENABLE BIT(1)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
2024-10-14 9:40 ` [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit CK Hu (胡俊光)
2024-10-16 3:43 ` CK Hu (胡俊光)
@ 2024-10-22 5:44 ` Krzysztof Kozlowski
2024-10-22 6:48 ` CK Hu (胡俊光)
` (9 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-22 5:44 UTC (permalink / raw)
To: Shu-hsiang Yang, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sumit Semwal, Christian Konig
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, dri-devel, linaro-mm-sig,
Project_Global_Chrome_Upstream_Group, yaya.chang, teddy.chen,
hidenorik, yunkec, shun-yi.wang
On 09/10/2024 13:15, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
...
> +
> +static int mtk_cam_probe(struct platform_device *pdev)
> +{
> + struct mtk_cam_device *cam_dev;
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + int ret;
> + unsigned int i;
> +
> + dev_dbg(dev, "camsys | start %s\n", __func__);
NAK. Same issues.
> +
> + /* initialize structure */
> + cam_dev = devm_kzalloc(dev, sizeof(*cam_dev), GFP_KERNEL);
> + if (!cam_dev)
> + return -ENOMEM;
> +
> + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) {
> + dev_err(dev, "%s: No suitable DMA available\n", __func__);
> + return -EIO;
> + }
> +
> + if (!dev->dma_parms) {
> + dev->dma_parms =
> + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
> + if (!dev->dma_parms)
> + return -ENOMEM;
> + }
> +
> + dma_set_max_seg_size(dev, UINT_MAX);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get mem\n");
> + return -ENODEV;
> + }
> +
> + cam_dev->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(cam_dev->base)) {
> + dev_err(dev, "failed to map register base\n");
> + return PTR_ERR(cam_dev->base);
> + }
> +
> + cam_dev->dev = dev;
> + dev_set_drvdata(dev, cam_dev);
> +
> + cam_dev->composer_cnt = 0;
> + cam_dev->num_seninf_devices = 0;
> +
> + cam_dev->max_stream_num = MTKCAM_SUBDEV_MAX;
> + cam_dev->ctxs = devm_kcalloc(dev, cam_dev->max_stream_num,
> + sizeof(*cam_dev->ctxs), GFP_KERNEL);
> + if (!cam_dev->ctxs)
> + return -ENOMEM;
> +
> + cam_dev->streaming_ctx = 0;
> + for (i = 0; i < cam_dev->max_stream_num; i++)
> + mtk_cam_ctx_init(cam_dev->ctxs + i, cam_dev, i);
> +
> + cam_dev->running_job_count = 0;
> + spin_lock_init(&cam_dev->pending_job_lock);
> + spin_lock_init(&cam_dev->running_job_lock);
> + INIT_LIST_HEAD(&cam_dev->pending_job_list);
> + INIT_LIST_HEAD(&cam_dev->running_job_list);
> +
> + cam_dev->dma_processing_count = 0;
> + spin_lock_init(&cam_dev->dma_pending_lock);
> + spin_lock_init(&cam_dev->dma_processing_lock);
> + INIT_LIST_HEAD(&cam_dev->dma_pending);
> + INIT_LIST_HEAD(&cam_dev->dma_processing);
> +
> + mutex_init(&cam_dev->queue_lock);
> +
> + pm_runtime_enable(dev);
> +
> + ret = mtk_cam_of_rproc(cam_dev, pdev);
> + if (ret)
> + goto fail_destroy_mutex;
> +
> + ret = register_sub_drivers(dev);
> + if (ret) {
> + dev_err(dev, "fail to register_sub_drivers\n");
> + goto fail_destroy_mutex;
> + }
> +
> + /* register mtk_cam as all isp subdev async parent */
> + cam_dev->notifier.ops = &mtk_cam_async_nf_ops;
> + v4l2_async_nf_init(&cam_dev->notifier, &cam_dev->v4l2_dev);
> + ret = mtk_cam_async_subdev_add(dev); /* wait all isp sub drivers */
> + if (ret) {
> + dev_err(dev, "%s failed mtk_cam_async_subdev_add\n", __func__);
> + goto fail_unregister_sub_drivers;
> + }
> +
> + ret = v4l2_async_nf_register(&cam_dev->notifier);
> + if (ret) {
> + dev_err(dev, "%s async_nf_register ret:%d\n", __func__, ret);
> + v4l2_async_nf_cleanup(&cam_dev->notifier);
> + goto fail_unregister_sub_drivers;
> + }
> +
> + ret = mtk_cam_debug_fs_init(cam_dev);
> + if (ret < 0)
> + goto fail_unregister_async_nf;
> +
> + dev_info(dev, "camsys | [%s] success\n", __func__);
NAK. Same issues.
> +
> + return 0;
> +
> +fail_unregister_async_nf:
> + v4l2_async_nf_unregister(&cam_dev->notifier);
> +
> +fail_unregister_sub_drivers:
> + unregister_sub_drivers(dev);
> +
> +fail_destroy_mutex:
> + mutex_destroy(&cam_dev->queue_lock);
> +
> + return ret;
> +}
> +
> +static void mtk_cam_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_cam_device *cam_dev = dev_get_drvdata(dev);
> +
> + pm_runtime_disable(dev);
> +
> + mtk_cam_debug_fs_deinit(cam_dev);
> +
> + v4l2_async_nf_unregister(&cam_dev->notifier);
> +
> + unregister_sub_drivers(dev);
> +
> + mutex_destroy(&cam_dev->queue_lock);
> +}
> +
> +static const struct dev_pm_ops mtk_cam_pm_ops = {
> + SET_RUNTIME_PM_OPS(mtk_cam_runtime_suspend, mtk_cam_runtime_resume,
> + NULL)
> +};
> +
> +static struct platform_driver mtk_cam_driver = {
> + .probe = mtk_cam_probe,
> + .remove = mtk_cam_remove,
> + .driver = {
> + .name = "mtk-cam",
> + .of_match_table = of_match_ptr(mtk_cam_of_ids),
Same issues as in previous patch.
All my comments apply to all your patches in this thread.
> + .pm = &mtk_cam_pm_ops,
> + }
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (5 preceding siblings ...)
2024-10-22 5:43 ` Krzysztof Kozlowski
@ 2024-10-22 6:14 ` CK Hu (胡俊光)
2024-10-22 6:30 ` CK Hu (胡俊光)
` (6 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-22 6:14 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static bool mtk_cam_raw_resource_calc(struct mtk_cam_device *cam,
> + struct mtk_cam_resource_config *res,
> + s64 pixel_rate, int res_plan,
> + int in_w, int in_h, int *out_w, int *out_h)
> +{
> + int res_step_type = 0;
> + int tgo_pxl_mode = 1;
> + int pixel_mode[MTK_CAMSYS_RES_STEP_NUM] = {0};
> + int bin_temp = 0, frz_temp = 0, hwn_temp = 0;
> + int bin_en = 0, frz_en = 0, twin_en = 0, clk_cur = 0;
> + int idx = 0, clk_res = 0, idx_res = 0;
> + bool res_found = false;
> + int lb_chk_res = -1;
> + int frz_ratio = 100;
> + int p;
> +
> + res->res_plan = res_plan;
> + res->pixel_rate = pixel_rate;
> + /* test pattern */
> + if (res->pixel_rate == 0)
> + res->pixel_rate = 450 * MHz;
> + dev_dbg(cam->dev,
> + "[Res] PR = %lld, w/h=%d/%d HWN(%d)/BIN(%d)/FRZ(%d),Plan:%d\n",
> + res->pixel_rate, in_w, in_h,
> + res->hwn_limit_max, res->bin_limit, res->frz_limit, res->res_plan);
> +
> + memcpy(res->res_strategy, raw_resource_strategy_plan + res->res_plan,
> + MTK_CAMSYS_RES_STEP_NUM * sizeof(int));
> + res->bin_enable = 0;
> + res->raw_num_used = 1;
> + res->frz_enable = 0;
> + res->frz_ratio = frz_ratio;
> + for (idx = 0; idx < MTK_CAMSYS_RES_STEP_NUM ; idx++) {
> + res_step_type = res->res_strategy[idx] & MTK_CAMSYS_RES_IDXMASK;
> + switch (res_step_type) {
> + case MTK_CAMSYS_RES_BIN_TAG:
> + bin_temp = res->res_strategy[idx] - E_RES_BIN_S;
> + if (bin_temp <= res->bin_limit)
> + bin_en = bin_temp;
> + if (bin_en && frz_en)
> + frz_en = 0;
> + break;
> + case MTK_CAMSYS_RES_FRZ_TAG:
> + frz_temp = res->res_strategy[idx] - E_RES_FRZ_S;
> + if (res->frz_limit < 100)
> + frz_en = frz_temp;
> + break;
> + case MTK_CAMSYS_RES_HWN_TAG:
> + hwn_temp = res->res_strategy[idx] - E_RES_HWN_S;
> + if (hwn_temp + 1 <= res->hwn_limit_max)
> + twin_en = hwn_temp;
> + break;
> + case MTK_CAMSYS_RES_CLK_TAG:
> + clk_cur = res->res_strategy[idx] - E_RES_CLK_S;
> + break;
> + default:
> + break;
> + }
> +
> + /* 1 for force bin on */
> + if (res->bin_limit >= 1)
> + bin_en = 1;
> +
> + if (res->hwn_limit_min > 1)
> + twin_en = 1;
> +
> + /* max line buffer check*/
> + lb_chk_res = mtk_raw_linebuf_chk(twin_en, res->bin_limit & BIN_ON,
> + frz_en, res->bin_limit & QBND_ON,
> + is_cbn_en(res->bin_limit),
> + in_w, &frz_ratio);
> + /* frz ratio*/
> + if (res_step_type == MTK_CAMSYS_RES_FRZ_TAG) {
> + res->frz_ratio = res->frz_limit < FRZ_PXLMODE_THRES ?
> + res->frz_limit : FRZ_PXLMODE_THRES;
> + }
> + /*try 1-pixel mode first*/
> + for (p = 1; p <= MTK_CAMSYS_PROC_DEFAULT_PIXELMODE; p++) {
MTK_CAMSYS_PROC_DEFAULT_PIXELMODE is 1, so this for-loop could be dropped.
> + tgo_pxl_mode = mtk_raw_pixelmode_calc(p, twin_en,
> + bin_en, frz_en,
> + res->frz_ratio);
mtk_raw_pixelmode_calc() would always return 1, so mtk_raw_pixelmode_calc() could be dropped.
Regards,
CK
> + /**
> + * isp throughput along resource strategy
> + * (compared with pixel rate)
> + */
> + pixel_mode[idx] = tgo_pxl_mode;
> +
> + /* only support 1-pixel mode */
> + if (p == 1 && lb_chk_res == LB_CHECK_OK) {
> + if (!res_found) {
> + res->bin_enable = bin_en;
> + res->frz_enable = frz_en;
> + res->raw_num_used = twin_en + 1;
> + clk_res = clk_cur;
> + idx_res = idx;
> + res_found = true;
> + break;
> + }
> + }
> + }
> + dev_dbg(cam->dev,
> + "Res-%d B/F/H/C=%d/%d/%d/%d -> %d/%d/%d/%d (%d)(%d)\n",
> + idx, bin_temp, frz_temp, hwn_temp, clk_cur, bin_en,
> + frz_en, twin_en, clk_cur, lb_chk_res, pixel_mode[idx]);
> + }
> +
> + tgo_pxl_mode = pixel_mode[idx_res];
> + switch (tgo_pxl_mode) {
> + case 1:
> + res->tgo_pxl_mode = 0;
> + break;
> + case 2:
> + res->tgo_pxl_mode = 1;
> + break;
> + case 4:
> + res->tgo_pxl_mode = 2;
> + break;
> + case 8:
> + res->tgo_pxl_mode = 3;
> + break;
> + default:
> + break;
> + }
> +
> + mtk_raw_update_debug_param(cam, res, &clk_res);
> +
> + if (res_found) {
> + dev_info(cam->dev,
> + "Res-end:%d BIN/FRZ/HWN/CLK/pxl=%d/%d(%d)/%d/%d/%d, clk:%d\n",
> + idx_res, res->bin_enable, res->frz_enable, res->frz_ratio,
> + res->raw_num_used, clk_res, res->tgo_pxl_mode,
> + res->clk_target);
> + } else {
> + dev_dbg(cam->dev, "[%s] Error resource result\n", __func__);
> + }
> + if (res->bin_enable) {
> + *out_w = in_w >> 1;
> + *out_h = in_h >> 1;
> + } else if (res->frz_enable) {
> + *out_w = in_w * res->frz_ratio / 100;
> + *out_h = in_h * res->frz_ratio / 100;
> + } else {
> + *out_w = in_w;
> + *out_h = in_h;
> + }
> +
> + return res_found;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (6 preceding siblings ...)
2024-10-22 6:14 ` CK Hu (胡俊光)
@ 2024-10-22 6:30 ` CK Hu (胡俊光)
2024-10-23 10:05 ` CK Hu (胡俊光)
` (5 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-22 6:30 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> sizeof(u32))
> +
> +enum MTK_CAMSYS_RES_STEP {
> + E_RES_BASIC,
> + E_RES_BIN_S = MTK_CAMSYS_RES_BIN_TAG,
> + E_RES_BIN0 = E_RES_BIN_S,
> + E_RES_BIN1,
> + E_RES_BIN_E,
> + E_RES_FRZ_S = MTK_CAMSYS_RES_FRZ_TAG,
> + E_RES_FRZ0 = E_RES_FRZ_S,
> + E_RES_FRZ1,
> + E_RES_FRZ_E,
> + E_RES_HWN_S = MTK_CAMSYS_RES_HWN_TAG,
> + E_RES_HWN0 = E_RES_HWN_S,
> + E_RES_HWN1,
> + E_RES_HWN2,
> + E_RES_HWN_E,
> + E_RES_CLK_S = MTK_CAMSYS_RES_CLK_TAG,
> + E_RES_CLK0 = E_RES_CLK_S,
> + E_RES_CLK1,
> + E_RES_CLK2,
> + E_RES_CLK3,
> + E_RES_CLK_E,
E_RES_CLK_E is useless, so drop it.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (2 preceding siblings ...)
2024-10-22 5:44 ` Krzysztof Kozlowski
@ 2024-10-22 6:48 ` CK Hu (胡俊光)
2024-10-29 2:35 ` CK Hu (胡俊光)
` (8 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-22 6:48 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static void mtk_cam_config_raw_path(struct mtk_cam_device *cam,
> + struct mtkcam_ipi_frame_param *frame_param,
> + struct mtk_cam_buffer *buf)
> +{
> + struct mtk_cam_video_device *node;
> + struct mtk_raw_pipeline *raw_pipeline;
> +
> + node = mtk_cam_vbq_to_vdev(buf->vbb.vb2_buf.vb2_queue);
> + raw_pipeline = mtk_cam_dev_get_raw_pipeline(cam, node->uid.pipe_id);
> + if (!raw_pipeline) {
> + dev_err(cam->dev, "%s: cannot find raw_pipeline, pipe_id:%d\n",
> + __func__, node->uid.pipe_id);
> + return;
> + }
> +
> + if (raw_pipeline->res_config.raw_path == V4L2_MTK_CAM_RAW_PATH_SELECT_BPC)
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_AFTER_BPC;
> + else if (raw_pipeline->res_config.raw_path == V4L2_MTK_CAM_RAW_PATH_SELECT_FUS)
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_AFTER_FUS;
> + else if (raw_pipeline->res_config.raw_path == V4L2_MTK_CAM_RAW_PATH_SELECT_DGN)
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_AFTER_DGN;
> + else if (raw_pipeline->res_config.raw_path == V4L2_MTK_CAM_RAW_PATH_SELECT_LSC)
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_AFTER_LSC;
> + else if (raw_pipeline->res_config.raw_path == V4L2_MTK_CAM_RAW_PATH_SELECT_LTM)
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_AFTER_LTM;
> + else
> + /* un-processed raw frame */
> + frame_param->raw_param.imgo_path_sel = MTKCAM_IPI_IMGO_UNPROCESSED;
This patch is too big, so let this patch support basic function first.
Let this patch support only MTKCAM_IPI_IMGO_UNPROCESSED,
and add other path by other patch. Maybe one patch for one path.
Regards,
CK
> +
> + dev_dbg(cam->dev, "%s: node:%d fd:%d idx:%d raw_path(%d) ipi imgo_path_sel(%d))\n",
> + __func__, node->desc.id, buf->vbb.request_fd, buf->vbb.vb2_buf.index,
> + raw_pipeline->res_config.raw_path, frame_param->raw_param.imgo_path_sel);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (7 preceding siblings ...)
2024-10-22 6:30 ` CK Hu (胡俊光)
@ 2024-10-23 10:05 ` CK Hu (胡俊光)
2024-10-25 6:30 ` CK Hu (胡俊光)
` (4 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-23 10:05 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int mtk_cam_raw_try_res_ctrl(struct mtk_raw_pipeline *pipeline,
> + struct mtk_cam_resource *res_user,
> + struct mtk_cam_resource_config *res_cfg,
> + struct v4l2_mbus_framefmt *sink_fmt)
> +{
> + s64 prate = 0;
> + int width, height;
> + struct device *dev = pipeline->raw->devs[pipeline->id];
> +
> + res_cfg->bin_limit = res_user->raw_res.bin; /* 1: force bin on */
> + res_cfg->frz_limit = 0;
> + res_cfg->hwn_limit_max = res_user->raw_res.raw_max;
> + res_cfg->hwn_limit_min = res_user->raw_res.raw_min;
> + res_cfg->hblank = res_user->sensor_res.hblank;
> + res_cfg->vblank = res_user->sensor_res.vblank;
> + res_cfg->sensor_pixel_rate = res_user->sensor_res.pixel_rate;
> + res_cfg->res_plan = res_user->raw_res.strategy;
> + res_cfg->raw_feature = res_user->raw_res.feature;
> + res_cfg->raw_path = res_user->raw_res.path_sel;
> +
> + if (res_user->sensor_res.cust_pixel_rate)
> + prate = res_user->sensor_res.cust_pixel_rate;
> + else if (mtk_cam_feature_is_pure_m2m(res_cfg->raw_feature))
> + prate = mtk_cam_calc_pure_m2m_pixelrate(sink_fmt->width,
> + sink_fmt->height,
> + &res_cfg->interval);
> + else
> + prate = mtk_cam_seninf_calc_pixelrate(pipeline->raw->cam_dev,
> + sink_fmt->width,
> + sink_fmt->height,
> + res_user->sensor_res.hblank,
> + res_user->sensor_res.vblank,
> + res_user->sensor_res.interval.denominator,
> + res_user->sensor_res.interval.numerator,
> + res_user->sensor_res.pixel_rate);
> +
> + mtk_cam_raw_resource_calc(dev_get_drvdata(pipeline->raw->cam_dev),
> + res_cfg, prate, res_cfg->res_plan,
> + sink_fmt->width, sink_fmt->height,
> + &width, &height);
If the basic function support only imgo unprocessed, does the unprocessed path imply the resource could be fixed?
I mean it's not necessary to calculate resource when imgo unprocessed path.
If so, remove resource calculation related code in this basic patch and add it back in advance function patch.
Regards,
CK
> +
> + if (res_user->raw_res.bin && !res_cfg->bin_enable) {
> + dev_err(dev,
> + "%s:pipe(%d): res calc failed on fource bin: user(%d)/bin_enable(%d)\n",
> + __func__, pipeline->id, res_user->raw_res.bin,
> + res_cfg->bin_enable);
> + return -EINVAL;
> + }
> +
> + if (res_cfg->raw_num_used > res_user->raw_res.raw_max ||
> + res_cfg->raw_num_used < res_user->raw_res.raw_min) {
> + dev_err(dev,
> + "%s:pipe(%d): res calc failed on raw used: user(%d/%d)/raw_num_used(%d)\n",
> + __func__, pipeline->id, res_user->raw_res.raw_max,
> + res_user->raw_res.raw_min, res_cfg->raw_num_used);
> + }
> +
> + res_user->raw_res.pixel_mode = res_cfg->tgo_pxl_mode;
> + res_user->raw_res.raw_used = res_cfg->raw_num_used;
> + if (res_cfg->bin_limit == BIN_AUTO)
> + res_user->raw_res.bin = res_cfg->bin_enable;
> + else
> + res_user->raw_res.bin = res_cfg->bin_limit;
> +
> + dev_info(dev,
> + "%s:pipe(%d): res calc result: raw_used(%d)/bin(%d)/pixelmode(%d)/strategy(%d)\n",
> + __func__, pipeline->id, res_user->raw_res.raw_used,
> + res_user->raw_res.bin, res_user->raw_res.pixel_mode,
> + res_user->raw_res.strategy);
> +
> + /**
> + * Other output not reveal to user:
> + * res_cfg->res_strategy[MTK_CAMSYS_RES_STEP_NUM];
> + * res_cfg->clk_target;
> + * res_cfg->frz_enable;
> + * res_cfg->frz_ratio;
> + * res_cfg->tgo_pxl_mode;
> + */
> + if (width != sink_fmt->width || height != sink_fmt->height) {
> + dev_info(dev,
> + "%s:pipe(%d): size adjust info: raw: sink(%d,%d) res:(%d,%d)\n",
> + __func__, pipeline->id, sink_fmt->width,
> + sink_fmt->height, width, height);
> + }
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (8 preceding siblings ...)
2024-10-23 10:05 ` CK Hu (胡俊光)
@ 2024-10-25 6:30 ` CK Hu (胡俊光)
2024-10-28 6:48 ` CK Hu (胡俊光)
` (3 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-25 6:30 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static const
> +char *capture_queue_names[RAW_PIPELINE_NUM][MTK_RAW_TOTAL_CAPTURE_QUEUES] = {
> + {"mtk-cam raw-0 main-stream",
Let the basic function support only one capture queue and add additional capture queue by other patch.
Maybe one patch for one queue.
The basic function support only "mtk-cam raw-0 main-stream" queue.
Regards,
CK
> + "mtk-cam raw-0 yuvo-1", "mtk-cam raw-0 yuvo-2",
> + "mtk-cam raw-0 yuvo-3", "mtk-cam raw-0 yuvo-4",
> + "mtk-cam raw-0 yuvo-5",
> + "mtk-cam raw-0 drzs4no-1", "mtk-cam raw-0 drzs4no-2", "mtk-cam raw-0 drzs4no-3",
> + "mtk-cam raw-0 rzh1n2to-1", "mtk-cam raw-0 rzh1n2to-2", "mtk-cam raw-0 rzh1n2to-3",
> + "mtk-cam raw-0 partial-meta-0", "mtk-cam raw-0 partial-meta-1",
> + "mtk-cam raw-0 partial-meta-2",
> + },
> + {"mtk-cam raw-1 main-stream",
> + "mtk-cam raw-1 yuvo-1", "mtk-cam raw-1 yuvo-2",
> + "mtk-cam raw-1 yuvo-3", "mtk-cam raw-1 yuvo-4",
> + "mtk-cam raw-1 yuvo-5",
> + "mtk-cam raw-1 drzs4no-1", "mtk-cam raw-1 drzs4no-2", "mtk-cam raw-1 drzs4no-3",
> + "mtk-cam raw-1 rzh1n2to-1", "mtk-cam raw-1 rzh1n2to-2", "mtk-cam raw-1 rzh1n2to-3",
> + "mtk-cam raw-1 partial-meta-0", "mtk-cam raw-1 partial-meta-1",
> + "mtk-cam raw-1 partial-meta-2",
> + },
> +
> + {"mtk-cam raw-2 main-stream",
> + "mtk-cam raw-2 yuvo-1", "mtk-cam raw-2 yuvo-2",
> + "mtk-cam raw-2 yuvo-3", "mtk-cam raw-2 yuvo-4",
> + "mtk-cam raw-2 yuvo-5",
> + "mtk-cam raw-2 drzs4no-1", "mtk-cam raw-2 drzs4no-2", "mtk-cam raw-2 drzs4no-3",
> + "mtk-cam raw-2 rzh1n2to-1", "mtk-cam raw-2 rzh1n2to-2", "mtk-cam raw-2 rzh1n2to-3",
> + "mtk-cam raw-2 partial-meta-0", "mtk-cam raw-2 partial-meta-1",
> + "mtk-cam raw-2 partial-meta-2",
> + },
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
2024-10-14 9:25 ` CK Hu (胡俊光)
2024-10-18 8:54 ` CK Hu (胡俊光)
@ 2024-10-28 1:27 ` CK Hu (胡俊光)
2024-10-28 1:30 ` CK Hu (胡俊光)
` (6 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 1:27 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +enum {
> + CLK_CAM_SENINF = 0,
CLK_CAM_SENINF is useless, so drop it.
Regards,
CK
> + CLK_TOP_SENINF,
> + CLK_TOP_SENINF1,
> + CLK_TOP_SENINF2,
> + CLK_TOP_SENINF3,
> + CLK_TOP_SENINF4,
> + CLK_TOP_SENINF5,
> + CLK_TOP_SENINF_END,
> + CLK_TOP_CAMTM = CLK_TOP_SENINF_END,
> + CLK_MAXCNT,
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (2 preceding siblings ...)
2024-10-28 1:27 ` CK Hu (胡俊光)
@ 2024-10-28 1:30 ` CK Hu (胡俊光)
2024-11-06 5:58 ` CK Hu (胡俊光)
` (5 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 1:30 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +enum VC_FEATURE {
> + VC_NONE = 0,
> + VC_MIN_NUM,
> + VC_RAW_DATA = VC_MIN_NUM,
> + VC_RAW_DATA_MAX,
> +
> + VC_PDAF_MIN_NUM = VC_RAW_DATA_MAX,
> + VC_PDAF_STATS = VC_PDAF_MIN_NUM,
> + VC_PDAF_STATS_NE,
> + VC_PDAF_STATS_ME,
> + VC_PDAF_STATS_SE,
> + VC_PDAF_STATS_PIX_1,
> + VC_PDAF_STATS_PIX_2,
> + VC_PDAF_STATS_NE_PIX_1 = VC_PDAF_STATS_PIX_1,
> + VC_PDAF_STATS_NE_PIX_2 = VC_PDAF_STATS_PIX_2,
> + VC_PDAF_STATS_ME_PIX_1,
> + VC_PDAF_STATS_ME_PIX_2,
> + VC_PDAF_STATS_SE_PIX_1,
VC_PDAF_STATS_SE_PIX_1 is useless, so drop it.
Regards,
CK
> + VC_PDAF_STATS_SE_PIX_2,
> + VC_PDAF_MAX_NUM,
> +
> + VC_HDR_MIN_NUM = VC_PDAF_MAX_NUM,
> + VC_HDR_MVHDR = VC_HDR_MIN_NUM,
> + VC_HDR_MAX_NUM,
> +
> + VC_3HDR_MIN_NUM = VC_HDR_MAX_NUM,
> + VC_3HDR_EMBEDDED = VC_3HDR_MIN_NUM,
> + VC_3HDR_FLICKER,
> + VC_3HDR_Y,
> + VC_3HDR_AE,
> + VC_3HDR_MAX_NUM,
> +
> + VC_STAGGER_MIN_NUM = VC_3HDR_MAX_NUM,
> + VC_STAGGER_EMBEDDED = VC_STAGGER_MIN_NUM,
> + VC_STAGGER_NE,
> + VC_STAGGER_ME,
> + VC_STAGGER_SE,
> + VC_STAGGER_MAX_NUM,
> +
> + VC_YUV_MIN_NUM = VC_STAGGER_MAX_NUM,
> + VC_YUV_Y = VC_YUV_MIN_NUM,
> + VC_YUV_UV,
> + VC_YUV_MAX_NUM,
> +
> + VC_RAW_EXT_MIN_NUM = VC_YUV_MAX_NUM,
> + VC_RAW_W_DATA = VC_RAW_EXT_MIN_NUM,
> + VC_RAW_PROCESSED_DATA,
> + VC_RAW_EXT_MAX_NUM,
> +
> + VC_GENERAL_DATA_MIN_NUM = VC_RAW_EXT_MAX_NUM,
> + VC_GENERAL_EMBEDDED = VC_GENERAL_DATA_MIN_NUM,
> + VC_GENERAL_DATA_MAX_NUM,
> +
> + VC_MAX_NUM = VC_GENERAL_DATA_MAX_NUM,
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
` (3 preceding siblings ...)
2024-10-22 4:16 ` CK Hu (胡俊光)
@ 2024-10-28 1:55 ` CK Hu (胡俊光)
4 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 1:55 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +#define SENINF_CAM_MUX0_CHK_CTL_1 0x0104
> +#define RG_SENINF_CAM_MUX0_EXP_HSIZE_SHIFT 0
> +#define RG_SENINF_CAM_MUX0_EXP_HSIZE_MASK (0xffff << 0)
> +#define RG_SENINF_CAM_MUX0_EXP_VSIZE_SHIFT 16
> +#define RG_SENINF_CAM_MUX0_EXP_VSIZE_MASK (0xffff << 16)
#define SENINF_CAM_MUX_CHK_CTL_1(n) (0x0104 + 0x10 * n)
#define RG_SENINF_CAM_MUX_EXP_HSIZE_SHIFT 0
#define RG_SENINF_CAM_MUX_EXP_HSIZE_MASK (0xffff << 0)
#define RG_SENINF_CAM_MUX_EXP_VSIZE_SHIFT 16
#define RG_SENINF_CAM_MUX_EXP_VSIZE_MASK (0xffff << 16)
> +int mtk_cam_seninf_set_cammux_src(struct seninf_ctx *ctx, int src,
> + int target, int exp_hsize, int exp_vsize)
> +{
> + void __iomem *seninf_cam_mux_base = ctx->reg_if_cam_mux;
> +
>
[snip]
> +
> + switch (target) {
> + case SENINF_CAM_MUX0:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0,
> + RG_SENINF_CAM_MUX0_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX0_CHK_CTL_1,
> + RG_SENINF_CAM_MUX0_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX0_CHK_CTL_1,
> + RG_SENINF_CAM_MUX0_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX1:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0,
> + RG_SENINF_CAM_MUX1_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX1_CHK_CTL_1,
> + RG_SENINF_CAM_MUX1_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX1_CHK_CTL_1,
> + RG_SENINF_CAM_MUX1_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX2:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0,
> + RG_SENINF_CAM_MUX2_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX2_CHK_CTL_1,
> + RG_SENINF_CAM_MUX2_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX2_CHK_CTL_1,
> + RG_SENINF_CAM_MUX2_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX3:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0,
> + RG_SENINF_CAM_MUX3_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX3_CHK_CTL_1,
> + RG_SENINF_CAM_MUX3_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX3_CHK_CTL_1,
> + RG_SENINF_CAM_MUX3_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX4:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1,
> + RG_SENINF_CAM_MUX4_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX4_CHK_CTL_1,
> + RG_SENINF_CAM_MUX4_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX4_CHK_CTL_1,
> + RG_SENINF_CAM_MUX4_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX5:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1,
> + RG_SENINF_CAM_MUX5_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX5_CHK_CTL_1,
> + RG_SENINF_CAM_MUX5_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX5_CHK_CTL_1,
> + RG_SENINF_CAM_MUX5_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX6:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1,
> + RG_SENINF_CAM_MUX6_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX6_CHK_CTL_1,
> + RG_SENINF_CAM_MUX6_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX6_CHK_CTL_1,
> + RG_SENINF_CAM_MUX6_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX7:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1,
> + RG_SENINF_CAM_MUX7_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX7_CHK_CTL_1,
> + RG_SENINF_CAM_MUX7_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX7_CHK_CTL_1,
> + RG_SENINF_CAM_MUX7_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX8:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2,
> + RG_SENINF_CAM_MUX8_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX8_CHK_CTL_1,
> + RG_SENINF_CAM_MUX8_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX8_CHK_CTL_1,
> + RG_SENINF_CAM_MUX8_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX9:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2,
> + RG_SENINF_CAM_MUX9_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX9_CHK_CTL_1,
> + RG_SENINF_CAM_MUX9_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX9_CHK_CTL_1,
> + RG_SENINF_CAM_MUX9_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX10:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2,
> + RG_SENINF_CAM_MUX10_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX10_CHK_CTL_1,
> + RG_SENINF_CAM_MUX10_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX10_CHK_CTL_1,
> + RG_SENINF_CAM_MUX10_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX11:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2,
> + RG_SENINF_CAM_MUX11_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX11_CHK_CTL_1,
> + RG_SENINF_CAM_MUX11_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX11_CHK_CTL_1,
> + RG_SENINF_CAM_MUX11_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX12:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3,
> + RG_SENINF_CAM_MUX12_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX12_CHK_CTL_1,
> + RG_SENINF_CAM_MUX12_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX12_CHK_CTL_1,
> + RG_SENINF_CAM_MUX12_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX13:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3,
> + RG_SENINF_CAM_MUX13_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX13_CHK_CTL_1,
> + RG_SENINF_CAM_MUX13_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX13_CHK_CTL_1,
> + RG_SENINF_CAM_MUX13_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX14:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3,
> + RG_SENINF_CAM_MUX14_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX14_CHK_CTL_1,
> + RG_SENINF_CAM_MUX14_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX14_CHK_CTL_1,
> + RG_SENINF_CAM_MUX14_EXP_VSIZE, exp_vsize);
> + break;
> + case SENINF_CAM_MUX15:
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3,
> + RG_SENINF_CAM_MUX15_SRC_SEL, src);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX15_CHK_CTL_1,
> + RG_SENINF_CAM_MUX15_EXP_HSIZE, exp_hsize);
> + SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX15_CHK_CTL_1,
> + RG_SENINF_CAM_MUX15_EXP_VSIZE, exp_vsize);
> + break;
> + default:
> + dev_dbg(ctx->dev, "invalid src %d target %d", src, target);
> + return -EINVAL;
> + }
Replace the switch like this:
SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CHK_CTL_1(target),
RG_SENINF_CAM_MUX_EXP_HSIZE, exp_hsize);
SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CHK_CTL_1(target),
RG_SENINF_CAM_MUX_EXP_VSIZE, exp_vsize);
Regards,
CK
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
2024-10-14 5:21 ` [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility CK Hu (胡俊光)
2024-10-22 5:30 ` CK Hu (胡俊光)
@ 2024-10-28 3:46 ` CK Hu (胡俊光)
2024-10-29 5:35 ` CK Hu (胡俊光)
` (13 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 3:46 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * struct mtkcam_ipi_hw_buffer - DMA buffer for CAM DMA device.
> + *
> + * @iova: DMA address for CAM DMA device. isp7_1: u64.
> + * @size: buffer size.
> + */
> +struct mtkcam_ipi_hw_buffer {
> + u64 iova;
> + u32 size;
> +} __packed;
> +
mtkcam_ipi_hw_buffer is useless, so drop it.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl
[not found] ` <20241009111551.27052-9-Shu-hsiang.Yang@mediatek.com>
2024-10-16 1:35 ` [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl CK Hu (胡俊光)
@ 2024-10-28 5:20 ` CK Hu (胡俊光)
2024-10-28 5:25 ` CK Hu (胡俊光)
2024-10-28 5:34 ` CK Hu (胡俊光)
2 siblings, 1 reply; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 5:20 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces state management and debugging mechanisms for the MediaTek
> ISP7.x camsys platform. State management establishes control over ISP
> operations and events, defining distinct states for request handling,
> sensor control, and frame synchronization, ensuring event processing.
> The debugging mechanism ensures stable operation and timely data
> collection during anomalies.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +int mtk_camsys_isr_event(struct mtk_cam_device *cam,
> + enum MTK_CAMSYS_ENGINE_TYPE engine_type,
> + unsigned int engine_id,
> + struct mtk_camsys_irq_info *irq_info)
> +{
> + int ret = 0;
> +
> + switch (engine_type) {
> + case CAMSYS_ENGINE_RAW:
> + ret = mtk_camsys_event_handle_raw(cam, engine_id, irq_info);
> + break;
> + case CAMSYS_ENGINE_SENINF:
> + if (irq_info->irq_type & (1 << CAMSYS_IRQ_FRAME_DROP))
CAMSYS_IRQ_FRAME_DROP is never set, so drop it.
Regards,
CK
> + dev_info(cam->dev,
> + "MTK_CAMSYS_ENGINE_SENINF_TAG engine:%d type:0x%x\n",
> + engine_id, irq_info->irq_type);
> + break;
> + default:
> + break;
> + }
> +
> + return ret;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl
2024-10-28 5:20 ` CK Hu (胡俊光)
@ 2024-10-28 5:25 ` CK Hu (胡俊光)
0 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 5:25 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
On Mon, 2024-10-28 at 13:20 +0800, CK Hu wrote:
> Hi, Shu-hsiang:
>
> On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > Introduces state management and debugging mechanisms for the MediaTek
> > ISP7.x camsys platform. State management establishes control over ISP
> > operations and events, defining distinct states for request handling,
> > sensor control, and frame synchronization, ensuring event processing.
> > The debugging mechanism ensures stable operation and timely data
> > collection during anomalies.
> >
> > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > ---
>
> [snip]
>
> > +int mtk_camsys_isr_event(struct mtk_cam_device *cam,
> > + enum MTK_CAMSYS_ENGINE_TYPE engine_type,
> > + unsigned int engine_id,
> > + struct mtk_camsys_irq_info *irq_info)
> > +{
> > + int ret = 0;
> > +
> > + switch (engine_type) {
> > + case CAMSYS_ENGINE_RAW:
> > + ret = mtk_camsys_event_handle_raw(cam, engine_id, irq_info);
> > + break;
> > + case CAMSYS_ENGINE_SENINF:
CAMSYS_ENGINE_SENINF is also never set, so drop it.
Regards,
CK
> > + if (irq_info->irq_type & (1 << CAMSYS_IRQ_FRAME_DROP))
>
> CAMSYS_IRQ_FRAME_DROP is never set, so drop it.
>
> Regards,
> CK
>
> > + dev_info(cam->dev,
> > + "MTK_CAMSYS_ENGINE_SENINF_TAG engine:%d type:0x%x\n",
> > + engine_id, irq_info->irq_type);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + return ret;
> > +}
> > +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl
[not found] ` <20241009111551.27052-9-Shu-hsiang.Yang@mediatek.com>
2024-10-16 1:35 ` [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl CK Hu (胡俊光)
2024-10-28 5:20 ` CK Hu (胡俊光)
@ 2024-10-28 5:34 ` CK Hu (胡俊光)
2 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 5:34 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces state management and debugging mechanisms for the MediaTek
> ISP7.x camsys platform. State management establishes control over ISP
> operations and events, defining distinct states for request handling,
> sensor control, and frame synchronization, ensuring event processing.
> The debugging mechanism ensures stable operation and timely data
> collection during anomalies.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +enum MTK_CAMSYS_ENGINE_TYPE {
> + CAMSYS_ENGINE_RAW,
> + CAMSYS_ENGINE_MRAW,
> + CAMSYS_ENGINE_CAMSV,
> + CAMSYS_ENGINE_SENINF,
Only CAMSYS_ENGINE_RAW is used, so it's not necessary to define MTK_CAMSYS_ENGINE_TYPE because only one type.
CAMSYS_ENGINE_RAW could also be dropped because only this type so it's not necessary to define it.
Regards,
CK
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (9 preceding siblings ...)
2024-10-25 6:30 ` CK Hu (胡俊光)
@ 2024-10-28 6:48 ` CK Hu (胡俊光)
2024-11-04 2:35 ` CK Hu (胡俊光)
` (2 subsequent siblings)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-28 6:48 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +static const struct mtk_cam_format_desc yuv_out_group2_fmts[] = {
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
I don't know why you define width and height here.
All width/height of yuv_out_group2_fmts are the same.
And the max width/height is define in capture_queues[].frmsizes.
So the width/height could be dropped here.
Regards,
CK
> + .pixelformat = V4L2_PIX_FMT_NV12,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_NV21,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_NV12_10,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_NV21_10,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_MTISP_NV12_10P,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_MTISP_NV21_10P,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_NV12_12,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_NV21_12,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_MTISP_NV12_12P,
> + },
> + },
> + {
> + .vfmt.fmt.pix_mp = {
> + .width = YUV_GROUP2_MAX_WIDTH,
> + .height = YUV_GROUP2_MAX_HEIGHT,
> + .pixelformat = V4L2_PIX_FMT_MTISP_NV21_12P,
> + },
> + }
> +};
> +
[snip]
> +#define MTK_RAW_TOTAL_CAPTURE_QUEUES 15
> +static const struct
> +mtk_cam_dev_node_desc capture_queues[] = {
>
[snip]
> + {
> + .id = MTK_RAW_YUVO_2_OUT,
> + .name = "yuvo 2",
> + .cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
> + .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
> + .link_flags = MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE,
> + .image = true,
> + .smem_alloc = false,
> + .dma_port = MTKCAM_IPI_RAW_YUVO_2,
> + .fmts = yuv_out_group2_fmts,
> + .num_fmts = ARRAY_SIZE(yuv_out_group2_fmts),
> + .default_fmt_idx = 0,
> + .pad_ops = &source_pad_ops_yuv,
> + .ioctl_ops = &mtk_cam_v4l2_vcap_ioctl_ops,
> + .frmsizes = &(struct v4l2_frmsizeenum) {
> + .index = 0,
> + .type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
> + .stepwise = {
> + .max_width = YUV_GROUP2_MAX_WIDTH,
> + .min_width = IMG_MIN_WIDTH,
> + .max_height = YUV_GROUP2_MAX_HEIGHT,
> + .min_height = IMG_MIN_HEIGHT,
> + .step_height = 1,
> + .step_width = 1,
> + },
> + },
> + },
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (3 preceding siblings ...)
2024-10-22 6:48 ` CK Hu (胡俊光)
@ 2024-10-29 2:35 ` CK Hu (胡俊光)
2024-10-29 6:47 ` CK Hu (胡俊光)
` (7 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-29 2:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +/**
> + * MediaTek Universal Frame Buffer Compression (UFBC) buffer header
> + * Caller must follow the bit stream buffer size and length table buffer size.
> + *
> + * Header Size
> + * Fixed size of 4096 bytes. Caller SHOULD NOT edit it.
> + *
> + * Bit Stream Size
> + * Bit stream width must be aligned to 64 pixel.
> + */
> +
> +struct ufbc_buf_header {
> + /** Describe image resolution, unit in pixel. */
> + u32 width;
> + /** Describe image resolution, unit in pixel. */
> + u32 height;
> + /** Describe UFBC data plane count, UFBC supports maximum 2 planes. */
> + u32 plane_count;
> + /** Describe the original image data bits per pixel of the given plane. */
> + u32 bits_per_pixel[3];
> +
> + /**
> + * Describe the offset of the given plane bit stream data in bytes,
> + * including header size.
> + */
> + u32 bitstream_offset[3];
> + /** Describe the bit stream data size in bytes of the given plane. */
> + u32 bitstream_size[3];
> + /** Describe the encoded data size in bytes of the given plane. */
> + u32 bitstream_data_size[3];
> +
> + /**
> + * Describe the offset of length table of the given plane, including
> + * header size.
> + */
> + u32 table_offset[3];
> + /** Describe the length table size of the given plane */
> + u32 table_size[3];
> + /** Describe the total buffer size, including buffer header. */
> + u32 buffer_size;
> +};
> +
> +struct ufbc_buffer_header {
> + union {
> + struct ufbc_buf_header header;
'struct ufbc_buf_header' is never used, so drop it.
Regards,
CK
> + u8 bits[4096];
> + };
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (2 preceding siblings ...)
2024-10-28 3:46 ` CK Hu (胡俊光)
@ 2024-10-29 5:35 ` CK Hu (胡俊光)
2024-11-04 2:26 ` CK Hu (胡俊光)
` (12 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-29 5:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * Bit Feild of LTMS_BLKHIST_INT: LTMS_BLKHIST_INT1
> + * MTK_CAM_LTMS_BLKHIST_INT_LTMS_BLKHIST_INT1: [0, 13]
> + * block histogram interval 1
> + */
> +#define MTK_CAM_LTMS_BLKHIST_INT_LTMS_BLKHIST_INT1_MASK 0x00003fff
> +#define MTK_CAM_LTMS_BLKHIST_INT_LTMS_BLKHIST_INT1_SHIFT 0
> +
MTK_CAM_LTMS_BLKHIST_INT_LTMS_BLKHIST_INT1_MASK and MTK_CAM_LTMS_BLKHIST_INT_LTMS_BLKHIST_INT1_SHIFT are never used, so drop them.
Regards,
CK
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (4 preceding siblings ...)
2024-10-29 2:35 ` CK Hu (胡俊光)
@ 2024-10-29 6:47 ` CK Hu (胡俊光)
2024-10-29 7:03 ` CK Hu (胡俊光)
` (6 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-29 6:47 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +void mtk_cam_buf_try_queue(struct mtk_cam_ctx *ctx)
> +{
> + struct mtk_cam_device *cam;
> + struct mtk_cam_buffer *buf, *buf_prev;
> + struct mtkcam_ipi_event event;
> + struct mtkcam_ipi_session_cookie *session = &event.cookie;
> + struct mtkcam_ipi_frame_info *frame_info = &event.frame_data;
> + struct mtkcam_ipi_frame_param *frame_param;
> + struct mtkcam_ipi_frame_param *frame_data;
> + struct mtk_cam_working_buf_entry *buf_entry;
> + struct list_head equeue_list;
> + unsigned int processing_cnt, enque_cnt;
> +
> + cam = ctx->cam;
> + if (!cam->streaming_ctx) {
> + dev_info(cam->dev, "streams are off\n");
> + return;
> + }
> +
> + INIT_LIST_HEAD(&equeue_list);
> +
> + spin_lock(&cam->dma_processing_lock);
> + processing_cnt = cam->dma_processing_count;
> + spin_unlock(&cam->dma_processing_lock);
> +
> + enque_cnt = 0;
> + spin_lock(&cam->dma_pending_lock);
> + list_for_each_entry_safe(buf, buf_prev, &cam->dma_pending, list) {
> + if (processing_cnt + enque_cnt >= MTK_CAM_MAX_PROCESSING_BUFS) {
> + dev_dbg(cam->dev,
> + "processing bufs are full, buf cnt(%d)\n",
> + processing_cnt);
> + break;
> + }
> + dev_dbg(cam->dev, "%s buf cnt(%d)\n",
> + __func__, processing_cnt + enque_cnt);
> +
> + enque_cnt++;
> + list_del(&buf->list);
> + list_add_tail(&buf->list, &equeue_list);
> + }
> + spin_unlock(&cam->dma_pending_lock);
> +
> + if (!enque_cnt)
> + return;
> +
> + frame_param = kzalloc(sizeof(*frame_param), GFP_KERNEL);
> + if (!frame_param)
> + return;
> +
> + list_for_each_entry_safe(buf, buf_prev, &equeue_list, list) {
> + if (buf->state.estate == E_BUF_STATE_COMPOSED)
This would never happened.
buf in equeue_list is moved from cam->dma_pending and buf's state is E_BUF_STATE_QUEUED.
So drop this checking.
Regards,
CK
> + continue;
> +
> + memset(&event, 0, sizeof(event));
> + event.cmd_id = CAM_CMD_FRAME;
> + session->session_id = ctx->stream_id;
> + /* prepare working buffer */
> + buf_entry = mtk_cam_working_buf_get(ctx);
> + if (!buf_entry) {
> + dev_info(cam->dev,
> + "%s: No CQ buf availablle: enqueued_frame_seq_no:%d\n",
> + __func__, atomic_read(&ctx->enqueued_frame_seq_no));
> + WARN_ON(1);
> + goto EXIT;
> + }
> +
> + spin_lock(&ctx->using_buffer_list.lock);
> + list_add_tail(&buf_entry->list_entry, &ctx->using_buffer_list.list);
> + ctx->using_buffer_list.cnt++;
> + spin_unlock(&ctx->using_buffer_list.lock);
> +
> + spin_lock(&cam->dma_processing_lock);
> + list_del(&buf->list);
> + list_add_tail(&buf->list, &cam->dma_processing);
> + cam->dma_processing_count++;
> + spin_unlock(&cam->dma_processing_lock);
> +
> + /* Prepare rp message */
> + frame_info->cur_msgbuf_offset =
> + buf_entry->msg_buffer.va -
> + cam->ctxs[session->session_id].buf_pool.msg_buf_va;
> + frame_info->cur_msgbuf_size = buf_entry->msg_buffer.size;
> + frame_data = (struct mtkcam_ipi_frame_param *)buf_entry->msg_buffer.va;
> + session->frame_no = atomic_inc_return(&ctx->enqueued_frame_seq_no);
> +
> + if (mtk_cam_buf_config(cam, frame_param, buf)) {
> + dev_err(cam->dev, "%s: Buffer config failed\n", __func__);
> + continue;
> + }
> + memcpy(frame_data, frame_param, sizeof(*frame_param));
> + frame_data->cur_workbuf_offset =
> + buf_entry->buffer.iova -
> + cam->ctxs[session->session_id].buf_pool.working_buf_iova;
> + frame_data->cur_workbuf_size = buf_entry->buffer.size;
> +
> + if (ctx->pipe->res_config.bin_limit == BIN_AUTO)
> + frame_data->raw_param.bin_flag = ctx->pipe->res_config.bin_enable;
> + else
> + frame_data->raw_param.bin_flag = ctx->pipe->res_config.bin_limit;
> +
> + scp_ipi_send(cam->scp, SCP_IPI_ISP_FRAME, &event,
> + sizeof(event), MTK_CAM_IPI_SEND_TIMEOUT);
> + buf->state.estate = E_BUF_STATE_COMPOSED;
> + }
> +EXIT:
> + kfree(frame_param);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (5 preceding siblings ...)
2024-10-29 6:47 ` CK Hu (胡俊光)
@ 2024-10-29 7:03 ` CK Hu (胡俊光)
2024-10-30 3:20 ` CK Hu (胡俊光)
2024-10-30 5:43 ` CK Hu (胡俊光)
` (5 subsequent siblings)
12 siblings, 1 reply; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-29 7:03 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtk_cam_device {
> + struct device *dev;
> +
> + struct v4l2_device v4l2_dev;
> + struct v4l2_async_notifier notifier;
> + struct media_device media_dev;
> + void __iomem *base;
> +
> + struct mtk_scp *scp;
> + struct device *smem_dev;
> + phandle rproc_phandle;
> + struct rproc *rproc_handle;
> +
> + unsigned int composer_cnt;
> +
> + unsigned int num_seninf_devices;
> + unsigned int num_raw_devices;
> + unsigned int num_larb_devices;
> +
> + /* raw_pipe controller subdev */
> + struct mtk_raw raw;
> + struct mutex queue_lock; /* protect queue request */
> +
> + unsigned int max_stream_num;
> + unsigned int streaming_ctx;
> + unsigned int streaming_pipe;
> + struct mtk_cam_ctx *ctxs;
> +
> + /* request related */
> + struct list_head pending_job_list;
> + spinlock_t pending_job_lock; /* protect pending_job_list */
> + struct list_head running_job_list;
> + unsigned int running_job_count;
> + spinlock_t running_job_lock; /* protect running_job_list */
> +
> + /* standard v4l2 buffer control */
> + struct list_head dma_pending;
> + spinlock_t dma_pending_lock; /* protect dma_pending_list */
> + struct list_head dma_processing;
> + spinlock_t dma_processing_lock; /* protect dma_processing_list and dma_processing_count */
> + unsigned int dma_processing_count;
I would like scp-related variable has the scp prefix.
struct list_head scp_dma_processing;
spinlock_t scp_dma_processing_lock;
unsigned int scp_dma_processing_count;
So it's easy to understand that scp_dma_processing_count's max value is 2.
One buffer is currently doing dma, and another one is waiting for dma. Both buffer are queued in scp.
Regards,
CK
> +
> + struct mtk_cam_debug_fs *debug_fs;
> + struct workqueue_struct *debug_wq;
> + struct workqueue_struct *debug_exception_wq;
> + wait_queue_head_t debug_exception_waitq;
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
2024-10-29 7:03 ` CK Hu (胡俊光)
@ 2024-10-30 3:20 ` CK Hu (胡俊光)
0 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-30 3:20 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Tue, 2024-10-29 at 15:03 +0800, CK Hu wrote:
> Hi, Shu-hsiang:
>
> On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> > The driver maintains the camera system, including sub-device management,
> > DMA operations, and integration with the V4L2 framework. It handles
> > request stream data, buffer management, and MediaTek-specific features,
> > and pipeline management, streaming control, error handling mechanism.
> > Additionally, it aggregates sub-drivers for the camera interface, raw
> > and yuv pipelines.
> >
> > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > ---
>
> [snip]
>
> > +struct mtk_cam_device {
> > + struct device *dev;
> > +
> > + struct v4l2_device v4l2_dev;
> > + struct v4l2_async_notifier notifier;
> > + struct media_device media_dev;
> > + void __iomem *base;
> > +
> > + struct mtk_scp *scp;
> > + struct device *smem_dev;
> > + phandle rproc_phandle;
> > + struct rproc *rproc_handle;
> > +
> > + unsigned int composer_cnt;
> > +
> > + unsigned int num_seninf_devices;
> > + unsigned int num_raw_devices;
> > + unsigned int num_larb_devices;
> > +
> > + /* raw_pipe controller subdev */
> > + struct mtk_raw raw;
> > + struct mutex queue_lock; /* protect queue request */
> > +
> > + unsigned int max_stream_num;
> > + unsigned int streaming_ctx;
> > + unsigned int streaming_pipe;
> > + struct mtk_cam_ctx *ctxs;
> > +
> > + /* request related */
> > + struct list_head pending_job_list;
> > + spinlock_t pending_job_lock; /* protect pending_job_list */
> > + struct list_head running_job_list;
> > + unsigned int running_job_count;
> > + spinlock_t running_job_lock; /* protect running_job_list */
> > +
> > + /* standard v4l2 buffer control */
> > + struct list_head dma_pending;
> > + spinlock_t dma_pending_lock; /* protect dma_pending_list */
> > + struct list_head dma_processing;
> > + spinlock_t dma_processing_lock; /* protect dma_processing_list and dma_processing_count */
> > + unsigned int dma_processing_count;
>
> I would like scp-related variable has the scp prefix.
>
> struct list_head scp_dma_processing;
> spinlock_t scp_dma_processing_lock;
> unsigned int scp_dma_processing_count;
>
> So it's easy to understand that scp_dma_processing_count's max value is 2.
> One buffer is currently doing dma, and another one is waiting for dma. Both buffer are queued in scp.
Forget previous comment. After review the buffer control, I think the buffer list should be simplified.
dma_pending, dma_processing, using_buffer_list, composed_buffer_list, processing_buffer_list could be merge into one buf_list.
The buffer in buf_list has different status.
In init, the buffer is queued into driver and status is waiting.
buf_list-> buf0(waiting)-> buf1(waiting)-> buf2(waiting)-> buf3(waiting)-> buf4(waiting)
In mtk_cam_buf_try_queue(), use scp to generate cq buffer content of buf0 and buf1, so the status is scp_generate_cq.
buf_list-> buf0(scp_generate_cq)-> buf1(scp_generate_cq)-> buf2(waiting)-> buf3(waiting)-> buf4(waiting)
So the buf_entry is bound to buf0 and buf1, it's not necessary have using_buffer_list, composed_buffer_list, processing_buffer_list to manage buf_entry.
In isp_composer_handler_ack(), scp has finish generating cq buffer content, so the status is cq_ready.
In the meantime, use scp to generate cq buffer content of buf2.
buf_list-> buf0(cq_ready)-> buf1(scp_generate_cq)-> buf2(scp_generate_cq)-> buf3(waiting)-> buf4(waiting)
In mtk_camsys_raw_frame_start(), apply cq buffer to hardware, so the status is cq_apply
buf_list-> buf0(cq_apply)-> buf1(scp_generate_cq)-> buf2(scp_generate_cq)-> buf3(waiting)-> buf4(waiting)
In mtk_camsys_frame_done(), hardware has finished writing video into buffer, so the status is done
buf_list-> buf0(done)-> buf1(scp_generate_cq)-> buf2(scp_generate_cq)-> buf3(waiting)-> buf4(waiting)
In this design, just need one buf_list with status.
The code would be more simple.
Simple code would has less bug.
Maybe you could drop so many debug utility.
Regards,
CK
>
> Regards,
> CK
>
> > +
> > + struct mtk_cam_debug_fs *debug_fs;
> > + struct workqueue_struct *debug_wq;
> > + struct workqueue_struct *debug_exception_wq;
> > + wait_queue_head_t debug_exception_waitq;
> > +};
> > +
>
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (6 preceding siblings ...)
2024-10-29 7:03 ` CK Hu (胡俊光)
@ 2024-10-30 5:43 ` CK Hu (胡俊光)
2024-11-04 6:08 ` CK Hu (胡俊光)
` (4 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-10-30 5:43 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtk_cam_device {
> + struct device *dev;
> +
> + struct v4l2_device v4l2_dev;
> + struct v4l2_async_notifier notifier;
> + struct media_device media_dev;
> + void __iomem *base;
> +
> + struct mtk_scp *scp;
> + struct device *smem_dev;
> + phandle rproc_phandle;
rproc_phandle is useless, so drop it.
> + struct rproc *rproc_handle;
> +
> + unsigned int composer_cnt;
> +
> + unsigned int num_seninf_devices;
> + unsigned int num_raw_devices;
> + unsigned int num_larb_devices;
num_larb_devices is useless, so drop it.
Regards,
CK
> +
> + /* raw_pipe controller subdev */
> + struct mtk_raw raw;
> + struct mutex queue_lock; /* protect queue request */
> +
> + unsigned int max_stream_num;
> + unsigned int streaming_ctx;
> + unsigned int streaming_pipe;
> + struct mtk_cam_ctx *ctxs;
> +
> + /* request related */
> + struct list_head pending_job_list;
> + spinlock_t pending_job_lock; /* protect pending_job_list */
> + struct list_head running_job_list;
> + unsigned int running_job_count;
> + spinlock_t running_job_lock; /* protect running_job_list */
> +
> + /* standard v4l2 buffer control */
> + struct list_head dma_pending;
> + spinlock_t dma_pending_lock; /* protect dma_pending_list */
> + struct list_head dma_processing;
> + spinlock_t dma_processing_lock; /* protect dma_processing_list and dma_processing_count */
> + unsigned int dma_processing_count;
> +
> + struct mtk_cam_debug_fs *debug_fs;
> + struct workqueue_struct *debug_wq;
> + struct workqueue_struct *debug_exception_wq;
> + wait_queue_head_t debug_exception_waitq;
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (3 preceding siblings ...)
2024-10-29 5:35 ` CK Hu (胡俊光)
@ 2024-11-04 2:26 ` CK Hu (胡俊光)
2024-11-05 3:33 ` CK Hu (胡俊光)
` (11 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-04 2:26 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static __maybe_unused struct dma_debug_item dbg_PDI_R1[] = {
> + {0x00000014, "pdi_r1 32(hex) 0000"},
You print this register value, but how to use this value to debug?
What's the error value? Each error value means what kind of error?
Add comment about how to use this value to debug.
If no one knows how to use this value, the debug method is redundant.
> + {0x00000114, "pdi_r1 state_checksum"},
Ditto.
> + {0x00000214, "pdi_r1 line_pix_cnt_tmp"},
Ditto.
> + {0x00000314, "pdi_r1 line_pix_cnt"},
Ditto.
> + {0x00000414, "pdi_r1 important_status"},
Ditto.
> + {0x00000514, "pdi_r1 cmd_data_cnt"},
Ditto.
> + {0x00000614, "pdi_r1 tilex_byte_cnt"},
Ditto.
> + {0x00000714, "pdi_r1 tiley_cnt"},
Ditto.
> + {0x00000814, "pdi_r1 burst_line_cnt"},
Ditto.
Regards,
CK
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (10 preceding siblings ...)
2024-10-28 6:48 ` CK Hu (胡俊光)
@ 2024-11-04 2:35 ` CK Hu (胡俊光)
2024-11-04 8:04 ` CK Hu (胡俊光)
2024-11-05 3:01 ` CK Hu (胡俊光)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-04 2:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +void mtk_cam_dump_req_rdy_status(struct device *dev,
> + void __iomem *base, void __iomem *yuvbase)
> +{
This function is useless, so drop it.
Regards,
CK
> + dev_dbg_ratelimited(dev,
> + "REQ RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_REQ_STAT));
> + dev_dbg_ratelimited(dev,
> + "RDY RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_RDY_STAT));
> + dev_dbg_ratelimited(dev,
> + "REQ YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_REQ_STAT));
> + dev_dbg_ratelimited(dev,
> + "RDY YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_RDY_STAT));
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops
2024-10-09 11:15 ` [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops Shu-hsiang Yang
@ 2024-11-04 3:24 ` CK Hu (胡俊光)
2024-11-20 1:05 ` CK Hu (胡俊光)
1 sibling, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-04 3:24 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the V4L2 video interface and feature management for the
> MediaTek ISP7x CAMSYS. These interfaces include various functionalities,
> such as video operation initialization and registration. They also
> manage MediaTek-specific formats and handle buffers for MediaTek camera
> video devices. This integrates CAMSYS functionalities to be compatible
> with the V4L2 framework.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +static void mtk_cam_fill_ext_fmtdesc(struct v4l2_fmtdesc *fmt)
> +{
> + const char *descr = NULL;
> + const unsigned int sz = sizeof(fmt->description);
> +
> + switch (fmt->pixelformat) {
> + case V4L2_PIX_FMT_MTISP_SBGGR8:
> + descr = "8-bit Bayer BGGR MTISP Packed";
V4L2_PIX_FMT_PISP_COMP1_RGGB is a Raspberry Pi format, and its fmtdesc is filled in v4l_fill_fmtdesc().
So move these fill code into v4l_fill_fmtdesc().
Regards,
CK
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG8:
> + descr = "8-bit Bayer GBRG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG8:
> + descr = "8-bit Bayer GRBG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB8:
> + descr = "8-bit Bayer RGGB MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR10:
> + descr = "10-bit Bayer BGGR MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG10:
> + descr = "10-bit Bayer GBRG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG10:
> + descr = "10-bit Bayer GRBG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB10:
> + descr = "10-bit Bayer RGGB MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR12:
> + descr = "12-bit Bayer BGGR MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG12:
> + descr = "12-bit Bayer GBRG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG12:
> + descr = "12-bit Bayer GRBG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB12:
> + descr = "12-bit Bayer RGGB MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR14:
> + descr = "14-bit Bayer BGGR MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG14:
> + descr = "14-bit Bayer GBRG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG14:
> + descr = "14-bit Bayer GRBG MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB14:
> + descr = "14-bit Bayer RGGB MTISP Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR8F:
> + descr = "8-bit Full-G Bayer BGGR Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG8F:
> + descr = "8-bit Full-G Bayer GBRG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG8F:
> + descr = "8-bit Full-G Bayer GRBG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB8F:
> + descr = "8-bit Full-G Bayer RGGB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR10F:
> + descr = "10-bit Full-G Bayer BGGR Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG10F:
> + descr = "10-bit Full-G Bayer GBRG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG10F:
> + descr = "10-bit Full-G Bayer GRBG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB10F:
> + descr = "10-bit Full-G Bayer RGGB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR12F:
> + descr = "12-bit Full-G Bayer BGGR Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG12F:
> + descr = "12-bit Full-G Bayer GBRG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG12F:
> + descr = "12-bit Full-G Bayer GRBG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB12F:
> + descr = "12-bit Full-G Bayer RGGB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SBGGR14F:
> + descr = "14-bit Full-G Bayer BGGR Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGBRG14F:
> + descr = "14-bit Full-G Bayer GBRG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRBG14F:
> + descr = "14-bit Full-G Bayer GRBG Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SRGGB14F:
> + descr = "14-bit Full-G Bayer RGGB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV12_10P:
> + descr = "Y/CbCr 4:2:0 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV21_10P:
> + descr = "Y/CrCb 4:2:0 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV16_10P:
> + descr = "Y/CbCr 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV61_10P:
> + descr = "Y/CrCb 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_YUYV10P:
> + descr = "YUYV 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_YVYU10P:
> + descr = "YVYU 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_UYVY10P:
> + descr = "UYVY 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_VYUY10P:
> + descr = "VYUY 4:2:2 10 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV12_12P:
> + descr = "Y/CbCr 4:2:0 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV21_12P:
> + descr = "Y/CrCb 4:2:0 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV16_12P:
> + descr = "Y/CbCr 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV61_12P:
> + descr = "Y/CrCb 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_YUYV12P:
> + descr = "YUYV 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_YVYU12P:
> + descr = "YVYU 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_UYVY12P:
> + descr = "UYVY 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_VYUY12P:
> + descr = "VYUY 4:2:2 12 bits packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV12_UFBC:
> + descr = "YCbCr 420 8 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV21_UFBC:
> + descr = "YCrCb 420 8 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV12_10_UFBC:
> + descr = "YCbCr 420 10 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV21_10_UFBC:
> + descr = "YCrCb 420 10 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV12_12_UFBC:
> + descr = "YCbCr 420 12 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_NV21_12_UFBC:
> + descr = "YCrCb 420 12 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_BAYER8_UFBC:
> + descr = "RAW 8 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_BAYER10_UFBC:
> + descr = "RAW 10 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_BAYER12_UFBC:
> + descr = "RAW 12 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_BAYER14_UFBC:
> + descr = "RAW 14 bits compress";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRB8F:
> + descr = "8-bit 3 plane GRB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRB10F:
> + descr = "10-bit 3 plane GRB Packed";
> + break;
> + case V4L2_PIX_FMT_MTISP_SGRB12F:
> + descr = "12-bit 3 plane GRB Packed";
> + break;
> + case V4L2_META_FMT_MTISP_PARAMS:
> + descr = "MTK ISP Tuning Metadata";
> + break;
> + case V4L2_META_FMT_MTISP_3A:
> + descr = "MTK 3A Statistics";
> + break;
> + case V4L2_META_FMT_MTISP_AF:
> + descr = "MTK AF Statistics";
> + break;
> + case V4L2_META_FMT_MTISP_LCS:
> + descr = "MTK LCS Statistics";
> + break;
> + case V4L2_META_FMT_MTISP_LMV:
> + descr = "MTK LMV Statistics";
> + break;
> + default:
> + descr = NULL;
> + break;
> + }
> +
> + if (descr)
> + WARN_ON(strscpy(fmt->description, descr, sz) < 0);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (7 preceding siblings ...)
2024-10-30 5:43 ` CK Hu (胡俊光)
@ 2024-11-04 6:08 ` CK Hu (胡俊光)
2024-11-04 13:06 ` [PATCH " Markus Elfring
` (3 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-04 6:08 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtk_cam_request_stream_data *
> +mtk_cam_get_req_s_data(struct mtk_cam_ctx *ctx, unsigned int pipe_id,
> + unsigned int frame_seq_no)
> +
> +{
> + struct mtk_cam_device *cam = ctx->cam;
> + struct mtk_cam_request *req, *req_prev;
> + struct mtk_cam_request_stream_data *req_stream_data;
> + int i;
> +
> + spin_lock(&cam->running_job_lock);
> + list_for_each_entry_safe(req, req_prev, &cam->running_job_list, list) {
> + if (req->pipe_used & (1 << pipe_id)) {
> + for (i = 0; i < req->p_data[pipe_id].s_data_num; i++) {
> + req_stream_data = &req->p_data[pipe_id].s_data[i];
> + if (req_stream_data->frame_seq_no == frame_seq_no) {
> + spin_unlock(&cam->running_job_lock);
> + return req_stream_data;
> + }
> + }
> + }
> + }
> + spin_unlock(&cam->running_job_lock);
> +
> + return NULL;
> +}
> +
> +struct mtk_cam_request *mtk_cam_get_req(struct mtk_cam_ctx *ctx,
> + unsigned int frame_seq_no)
> +{
> + struct mtk_cam_request_stream_data *req_stream_data;
> +
> + req_stream_data = mtk_cam_get_req_s_data(ctx, ctx->stream_id, frame_seq_no);
In some place, it is called 'stream_id'. In some place, it is called 'pipe_id'.
It's easy to confuse us that stream_id and pipe_id are different and the code readability is bad.
Use the unique name so that we would not get confused.
Regards,
CK
> + if (!req_stream_data)
> + return NULL;
> +
> + return req_stream_data->req;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (11 preceding siblings ...)
2024-11-04 2:35 ` CK Hu (胡俊光)
@ 2024-11-04 8:04 ` CK Hu (胡俊光)
2024-11-05 3:01 ` CK Hu (胡俊光)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-04 8:04 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static bool mtk_raw_fmt_get_res(struct v4l2_subdev *sd,
> + struct v4l2_subdev_format *fmt,
> + struct mtk_cam_resource *res)
> +{
> + void *user_ptr;
> + u64 addr;
> +
> + addr = ((u64)fmt->reserved[1] << 32) | fmt->reserved[2];
The callstack to this function is:
subdev_do_ioctl() -> mtk_raw_set_fmt() -> mtk_raw_try_pad_fmt() -> mtk_raw_set_src_pad_fmt() -> mtk_raw_fmt_get_res()
In subdev_do_ioctl() [1], fmt->reserved[] would be cleared to zero.
I don't know why you could get a non-zero addr value?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/media/v4l2-core/v4l2-subdev.c?h=v6.12-rc6#n753
Regards,
CK
> + user_ptr = (void *)addr;
> + if (!user_ptr) {
> + dev_info(sd->v4l2_dev->dev, "%s: mtk_cam_resource is null\n",
> + __func__);
> + return false;
> + }
> +
> + if (copy_from_user(res, (void __user *)user_ptr, sizeof(*res))) {
> + dev_info(sd->v4l2_dev->dev,
> + "%s: copy_from_user failedm user_ptr:%p\n",
> + __func__, user_ptr);
> + return false;
> + }
> +
> + dev_dbg(sd->v4l2_dev->dev,
> + "%s:sensor:%d/%d/%lld/%d/%d, raw:%lld/%d/%d/%d/%d/%d/%d/%d/%lld\n",
> + __func__,
> + res->sensor_res.hblank, res->sensor_res.vblank,
> + res->sensor_res.pixel_rate, res->sensor_res.interval.denominator,
> + res->sensor_res.interval.numerator,
> + res->raw_res.feature, res->raw_res.bin, res->raw_res.path_sel,
> + res->raw_res.raw_max, res->raw_res.raw_min, res->raw_res.raw_used,
> + res->raw_res.strategy, res->raw_res.pixel_mode,
> + res->raw_res.throughput);
> +
> + return res;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (8 preceding siblings ...)
2024-11-04 6:08 ` CK Hu (胡俊光)
@ 2024-11-04 13:06 ` Markus Elfring
2024-11-06 7:52 ` [PATCH v1 " CK Hu (胡俊光)
` (2 subsequent siblings)
12 siblings, 0 replies; 88+ messages in thread
From: Markus Elfring @ 2024-11-04 13:06 UTC (permalink / raw)
To: Shu-hsiang Yang, Project_Global_Chrome_Upstream_Group,
linux-mediatek, linux-arm-kernel, linux-media, devicetree,
dri-devel, linaro-mm-sig, Angelo Gioacchino Del Regno,
Christian König, Conor Dooley, Krzysztof Kozlowski,
Matthias Brugger, Mauro Carvalho Chehab, Rob Herring,
Sumit Semwal
Cc: LKML, Hidenori Kobayashi, Shun-Yi Wang (王順億),
teddy.chen, yaya.chang, Yunke Cao
…
> +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.c
> @@ -0,0 +1,4168 @@
…
> +void mtk_cam_dev_req_try_queue(struct mtk_cam_device *cam)
> +{
…
> + spin_lock(&cam->running_job_lock);
> + job_count = cam->running_job_count;
> + spin_unlock(&cam->running_job_lock);
…
Under which circumstances would you become interested to apply a statement
like “guard(spinlock)(&cam->running_job_lock);”?
https://elixir.bootlin.com/linux/v6.12-rc6/source/include/linux/spinlock.h#L559
Regards,
Markus
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
` (12 preceding siblings ...)
2024-11-04 8:04 ` CK Hu (胡俊光)
@ 2024-11-05 3:01 ` CK Hu (胡俊光)
13 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-05 3:01 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int mtk_raw_of_probe(struct platform_device *pdev,
> + struct mtk_raw_device *raw)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + int ret;
> + int n_clks;
> +
> + ret = of_property_read_u32(dev->of_node, "mediatek,cam-id", &raw->id);
You don't need raw->id.
I think each raw could work independently.
Each raw has its own 'struct mtk_raw_device' context data.
It's not necessary to know which one it is.
When you use dev_dbg() or dev_err(), it would show register base so you could identify which raw print this message.
Regards,
CK
> + if (ret) {
> + dev_dbg(dev, "missing camid property\n");
> + return ret;
> + }
> +
> + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) {
> + dev_err(dev, "%s: No suitable DMA available\n", __func__);
> + return -EIO;
> + }
> +
> + if (!dev->dma_parms) {
> + dev->dma_parms =
> + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
> + if (!dev->dma_parms)
> + return -ENOMEM;
> + }
> +
> + dma_set_max_seg_size(dev, UINT_MAX);
> +
> + /* base outer register */
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
> + if (!res) {
> + dev_err(dev, "failed to get mem\n");
> + return -ENODEV;
> + }
> +
> + raw->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(raw->base)) {
> + dev_err(dev, "failed to map register base\n");
> + return PTR_ERR(raw->base);
> + }
> +
> + /* base inner register */
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "inner_base");
> + if (!res) {
> + dev_err(dev, "failed to get mem\n");
> + return -ENODEV;
> + }
> +
> + raw->base_inner = devm_ioremap_resource(dev, res);
> + if (IS_ERR(raw->base_inner)) {
> + dev_err(dev, "failed to map register inner base\n");
> + return PTR_ERR(raw->base_inner);
> + }
> +
> + /* will be assigned later */
> + raw->yuv_base = NULL;
> +
> + raw->irq = platform_get_irq(pdev, 0);
> + if (raw->irq < 0) {
> + dev_err(dev, "failed to get irq\n");
> + return -ENODEV;
> + }
> +
> + ret = devm_request_threaded_irq(dev, raw->irq,
> + mtk_irq_raw, mtk_thread_irq_raw,
> + 0, dev_name(dev), raw);
> + if (ret) {
> + dev_err(dev, "failed to request irq=%d\n", raw->irq);
> + return ret;
> + }
> + dev_dbg(dev, "registered irq=%d\n", raw->irq);
> +
> + disable_irq(raw->irq);
> +
> + n_clks = devm_clk_bulk_get_all(dev, &raw->clk_b);
> + if (n_clks < 0) {
> + dev_err(dev, "failed to devm_clk_bulk_get_all=%d\n", n_clks);
> + return n_clks;
> + }
> +
> + raw->num_clks = n_clks;
> + dev_info(dev, "clk_num:%d\n", raw->num_clks);
> +
> +#ifdef CONFIG_PM_SLEEP
> + raw->pm_notifier.notifier_call = raw_pm_notifier;
> + ret = register_pm_notifier(&raw->pm_notifier);
> + if (ret) {
> + dev_info(dev, "failed to register notifier block.\n");
> + return ret;
> + }
> +#endif
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (4 preceding siblings ...)
2024-11-04 2:26 ` CK Hu (胡俊光)
@ 2024-11-05 3:33 ` CK Hu (胡俊光)
2024-11-05 8:43 ` CK Hu (胡俊光)
` (10 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-05 3:33 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* RAW input trigger ctrl*/
> +#define RAWI_R2_TRIG BIT(0)
> +#define RAWI_R3_TRIG BIT(1)
> +#define RAWI_R4_TRIG BIT(2)
RAWI_R4_TRIG is not used, so drop it.
Regards,
CK
> +#define RAWI_R5_TRIG BIT(3)
> +#define RAWI_R6_TRIG BIT(4)
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-10-09 11:15 ` [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api Shu-hsiang Yang
2024-10-11 7:47 ` CK Hu (胡俊光)
2024-10-14 5:56 ` CK Hu (胡俊光)
@ 2024-11-05 5:36 ` CK Hu (胡俊光)
2 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-05 5:36 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Add UAPI for MediaTek ISP platform, providing user-space
> interfaces for the new camsys driver.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +#define V4L2_CID_MTK_CAM_RAW_PATH_SELECT (V4L2_CID_USER_MTK_CAM_BASE + 14)
> +#define V4L2_CID_MTK_CAM_HSF_EN (V4L2_CID_USER_MTK_CAM_BASE + 15)
> +#define V4L2_CID_MTK_CAM_PDE_INFO (V4L2_CID_USER_MTK_CAM_BASE + 16)
> +#define V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE (V4L2_CID_USER_MTK_CAM_BASE + 17)
V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE is useless, so drop it.
Regards,
CK
> +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_CALC (V4L2_CID_USER_MTK_CAM_BASE + 18)
> +#define V4L2_CID_MTK_CAM_TG_FLASH_CFG (V4L2_CID_USER_MTK_CAM_BASE + 19)
> +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_UPDATE (V4L2_CID_USER_MTK_CAM_BASE + 20)
> +#define V4L2_CID_MTK_CAM_CAMSYS_HW_MODE (V4L2_CID_USER_MTK_CAM_BASE + 21)
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (5 preceding siblings ...)
2024-11-05 3:33 ` CK Hu (胡俊光)
@ 2024-11-05 8:43 ` CK Hu (胡俊光)
2024-11-05 9:14 ` CK Hu (胡俊光)
` (9 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-05 8:43 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* Control flags of CAM_CMD_CONFIG */
> +#define MTK_CAM_IPI_CONFIG_TYPE_INIT 0x0001
> +#define MTK_CAM_IPI_CONFIG_TYPE_INPUT_CHANGE 0x0002
> +#define MTK_CAM_IPI_CONFIG_TYPE_EXEC_TWICE 0x0004
MTK_CAM_IPI_CONFIG_TYPE_EXEC_TWICE is useless, so drop it.
> +#define MTK_CAM_IPI_CONFIG_TYPE_SMVR_PREVIEW 0x0008
Ditto for MTK_CAM_IPI_CONFIG_TYPE_SMVR_PREVIEW.
Regards,
CK
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (6 preceding siblings ...)
2024-11-05 8:43 ` CK Hu (胡俊光)
@ 2024-11-05 9:14 ` CK Hu (胡俊光)
2024-11-06 3:35 ` CK Hu (胡俊光)
` (8 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-05 9:14 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +#define MTK_CAM_IPI_VERSION_MAJOR (0)
MTK_CAM_IPI_VERSION_MAJOR is useless, so drop it.
> +#define MTK_CAM_IPI_VERSION_MINOR (1)
Ditto.
Regards,
CK
> +
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (7 preceding siblings ...)
2024-11-05 9:14 ` CK Hu (胡俊光)
@ 2024-11-06 3:35 ` CK Hu (胡俊光)
2024-11-06 3:41 ` CK Hu (胡俊光)
` (7 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 3:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * Bit Feild of LTM_GAIN_MAP: LTM_TRAN_WGT_TYPE
> + * MTK_CAM_LTM_GAIN_MAP_LTM_TRAN_WGT_TYPE: [12, 13]
> + * type of tran weight
> + */
> +#define MTK_CAM_LTM_GAIN_MAP_LTM_TRAN_WGT_TYPE_MASK 0x00003000
MTK_CAM_LTM_GAIN_MAP_LTM_TRAN_WGT_TYPE_MASK is useless, so drop it.
Regards,
CK
> +#define MTK_CAM_LTM_GAIN_MAP_LTM_TRAN_WGT_TYPE_SHIFT 12
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (8 preceding siblings ...)
2024-11-06 3:35 ` CK Hu (胡俊光)
@ 2024-11-06 3:41 ` CK Hu (胡俊光)
2024-11-06 3:48 ` CK Hu (胡俊光)
` (6 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 3:41 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtkcam_ipi_hw_mapping {
> + u8 pipe_id; /* ref. to mtkcam_pipe_subdev */
> + u16 dev_mask; /* ref. to mtkcam_pipe_dev */
> + u8 exp_order;
exp_order is useless, so drop it.
Regards,
CK
> +} __packed;
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (9 preceding siblings ...)
2024-11-06 3:41 ` CK Hu (胡俊光)
@ 2024-11-06 3:48 ` CK Hu (胡俊光)
2024-11-06 7:01 ` CK Hu (胡俊光)
` (5 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 3:48 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* CAMSYS_RAW 0x1a03 */
> +#define OFFSET_OBC_R1_R_SUM_L 0x1178
> +#define OFFSET_OBC_R1_R_SUM_H 0x117c
> +#define OFFSET_OBC_R1_B_SUM_L 0x1180
> +#define OFFSET_OBC_R1_B_SUM_H 0x1184
> +#define OFFSET_OBC_R1_GR_SUM_L 0x1188
> +#define OFFSET_OBC_R1_GR_SUM_H 0x118c
> +#define OFFSET_OBC_R1_GB_SUM_L 0x1190
> +#define OFFSET_OBC_R1_GB_SUM_H 0x1194
> +#define OFFSET_OBC_R1_ACT_WIN_X 0x1198
OFFSET_OBC_R1_ACT_WIN_X is useless, so drop it.
Regards,
CK
> +#define OFFSET_OBC_R1_ACT_WIN_Y 0x119c
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (3 preceding siblings ...)
2024-10-28 1:30 ` CK Hu (胡俊光)
@ 2024-11-06 5:58 ` CK Hu (胡俊光)
2024-11-18 9:23 ` CK Hu (胡俊光)
` (4 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 5:58 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int get_pixel_rate(struct seninf_ctx *ctx, struct v4l2_subdev *sd,
> + s64 *result)
> +{
> + struct v4l2_ctrl *ctrl;
> +
> + ctrl = v4l2_ctrl_find(sd->ctrl_handler, V4L2_CID_PIXEL_RATE);
V4L2_CID_PIXEL_RATE is never set, so this function is redundant. Drop this function.
Regards,
CK
> + if (!ctrl) {
> + dev_info(ctx->dev, "no pixel rate in subdev %s\n", sd->name);
> + return -EINVAL;
> + }
> +
> + *result = v4l2_ctrl_g_ctrl_int64(ctrl);
> +
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (10 preceding siblings ...)
2024-11-06 3:48 ` CK Hu (胡俊光)
@ 2024-11-06 7:01 ` CK Hu (胡俊光)
2024-11-19 8:23 ` CK Hu (胡俊光)
` (4 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 7:01 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* CAM DMA done status */
> +#define IMGO_DONE_ST BIT(0)
IMGO_DONE_ST is useless, so drop it.
Regards,
CK
> +#define AFO_DONE_ST BIT(8)
> +#define CQI_R1_DONE_ST BIT(15)
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (9 preceding siblings ...)
2024-11-04 13:06 ` [PATCH " Markus Elfring
@ 2024-11-06 7:52 ` CK Hu (胡俊光)
2024-11-13 7:24 ` CK Hu (胡俊光)
2024-11-20 6:10 ` CK Hu (胡俊光)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-06 7:52 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* flags of mtk_cam_request */
> +#define MTK_CAM_REQ_FLAG_SENINF_CHANGED BIT(0)
MTK_CAM_REQ_FLAG_SENINF_CHANGED is never used, so drop it.
> +#define MTK_CAM_REQ_FLAG_SENINF_IMMEDIATE_UPDATE BIT(1)
> +
> +/* flags of mtk_cam_request_stream_data */
> +#define MTK_CAM_REQ_S_DATA_FLAG_TG_FLASH BIT(0)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_META1_INDEPENDENT BIT(1)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_SINK_FMT_UPDATE BIT(2)
> +/* Apply sensor mode and the timing is 1 vsync before */
> +#define MTK_CAM_REQ_S_DATA_FLAG_SENSOR_MODE_UPDATE_T1 BIT(3)
MTK_CAM_REQ_S_DATA_FLAG_SENSOR_MODE_UPDATE_T1 is useless, so drop it.
Regards,
CK
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_SENSOR_HDL_EN BIT(4)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_RAW_HDL_EN BIT(5)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_SENSOR_HDL_COMPLETE BIT(6)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_RAW_HDL_COMPLETE BIT(7)
> +
> +#define MTK_CAM_REQ_S_DATA_FLAG_SENSOR_HDL_DELAYED BIT(8)
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-10-14 5:56 ` CK Hu (胡俊光)
@ 2024-11-06 13:04 ` Laurent Pinchart
2024-11-18 9:58 ` Laurent Pinchart
0 siblings, 1 reply; 88+ messages in thread
From: Laurent Pinchart @ 2024-11-06 13:04 UTC (permalink / raw)
To: CK Hu (胡俊光)
Cc: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔),
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
On Mon, Oct 14, 2024 at 05:56:40AM +0000, CK Hu (胡俊光) wrote:
> Hi, Shu-hsiang:
>
> On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > Add UAPI for MediaTek ISP platform, providing user-space
> > interfaces for the new camsys driver.
> >
> > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > ---
>
> [snip]
>
> > +
> > +/* MTK ISP camsys controls */
> > +#define V4L2_CID_MTK_CAM_USED_ENGINE_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 1)
> > +#define V4L2_CID_MTK_CAM_BIN_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 2)
> > +#define V4L2_CID_MTK_CAM_FRZ_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 3)
> > +#define V4L2_CID_MTK_CAM_RESOURCE_PLAN_POLICY (V4L2_CID_USER_MTK_CAM_BASE + 4)
> > +#define V4L2_CID_MTK_CAM_USED_ENGINE (V4L2_CID_USER_MTK_CAM_BASE + 5)
> > +#define V4L2_CID_MTK_CAM_BIN (V4L2_CID_USER_MTK_CAM_BASE + 6)
> > +#define V4L2_CID_MTK_CAM_FRZ (V4L2_CID_USER_MTK_CAM_BASE + 7)
> > +#define V4L2_CID_MTK_CAM_USED_ENGINE_TRY (V4L2_CID_USER_MTK_CAM_BASE + 8)
> > +#define V4L2_CID_MTK_CAM_BIN_TRY (V4L2_CID_USER_MTK_CAM_BASE + 9)
> > +#define V4L2_CID_MTK_CAM_FRZ_TRY (V4L2_CID_USER_MTK_CAM_BASE + 10)
> > +#define V4L2_CID_MTK_CAM_PIXEL_RATE (V4L2_CID_USER_MTK_CAM_BASE + 11)
> > +#define V4L2_CID_MTK_CAM_FEATURE (V4L2_CID_USER_MTK_CAM_BASE + 12)
> > +#define V4L2_CID_MTK_CAM_SYNC_ID (V4L2_CID_USER_MTK_CAM_BASE + 13)
> > +#define V4L2_CID_MTK_CAM_RAW_PATH_SELECT (V4L2_CID_USER_MTK_CAM_BASE + 14)
> > +#define V4L2_CID_MTK_CAM_HSF_EN (V4L2_CID_USER_MTK_CAM_BASE + 15)
> > +#define V4L2_CID_MTK_CAM_PDE_INFO (V4L2_CID_USER_MTK_CAM_BASE + 16)
> > +#define V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE (V4L2_CID_USER_MTK_CAM_BASE + 17)
> > +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_CALC (V4L2_CID_USER_MTK_CAM_BASE + 18)
> > +#define V4L2_CID_MTK_CAM_TG_FLASH_CFG (V4L2_CID_USER_MTK_CAM_BASE + 19)
> > +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_UPDATE (V4L2_CID_USER_MTK_CAM_BASE + 20)
> > +#define V4L2_CID_MTK_CAM_CAMSYS_HW_MODE (V4L2_CID_USER_MTK_CAM_BASE + 21)
> > +
>
> Please give introduction of how to use these user space interface.
I'm very, very *not* thrilled by all this. It looks like a big pile of
hacks really. Every single parameter used by those controls needs to be
clearly documented, including explaining how they are used, in order for
us to review the API. I suspect that many of the parameters should
instead be handled through the ISP parameters buffers, or be controlled
from standard V4L2 APIs.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
` (3 preceding siblings ...)
2024-10-22 5:36 ` Krzysztof Kozlowski
@ 2024-11-11 1:37 ` CK Hu (胡俊光)
2024-11-11 2:38 ` CK Hu (胡俊光)
5 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-11 1:37 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +...
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> new file mode 100644
> index 000000000000..ce378ddbd5bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPg8zy568$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The camisp unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,camisp
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + mediatek,scp:
> + description: MediaTek co-process unit for ISP system
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camisp: camisp@16000000 {
In mt8188.dtsi [1], there is already a clock controller at address 16000000.
It should not have two device at the same address.
It should have one device which has multiple function.
mmsys controller [2] is a syscon (system controller) device which has multiple function.
It has a main driver (mmsys driver) [3] and two sub driver: clock driver [4] and display driver [5].
The main driver would probe the sub drivers.
Refer to mmsys device to refine the device at address 16000000.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8188.dtsi?h=v6.12-rc7#n1847
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v6.12-rc7
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v6.12-rc7
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8188-vdo0.c?h=v6.12-rc7
[5] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.c?h=v6.12-rc7
Regards,
CK
> + compatible = "mediatek,camisp";
> + reg = <0 0x16000000 0 0x1000>;
> + reg-names = "base";
> + mediatek,scp = <&scp_dual>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
> + };
> + };
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
` (4 preceding siblings ...)
2024-11-11 1:37 ` CK Hu (胡俊光)
@ 2024-11-11 2:38 ` CK Hu (胡俊光)
5 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-11 2:38 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPnhKvzWQ$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + minItems: 1
> + maxItems: 2
> +
> + mediatek,cam-id:
> + description:
> + Describes the index of MediaTek cam-raw unit for ISP
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + mediatek,larbs:
> + description:
> + Describes MediaTek bus infrastructure unit for ISP system.
> + List of phandle to the local arbiters in the current SoCs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + maxItems: 32
> +
> + interrupts:
> + minItems: 1
> +
> + dma-ranges:
> + description:
> + Describes the address information of IOMMU mapping to memory.
> + Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
> + minItems: 1
> +
> + power-domains:
> + minItems: 1
> +
> + clocks:
> + minItems: 4
> + maxItems: 16
> +
> + clock-names:
> + minItems: 4
> + maxItems: 16
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
It could be
reg = <0 0x16030000 0 0x10000>;
Why do you break it into two part?
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
larb information is inside iommu device, so it's not necessary to have a larb property here.
Regards,
CK
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> + };
> + };
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (10 preceding siblings ...)
2024-11-06 7:52 ` [PATCH v1 " CK Hu (胡俊光)
@ 2024-11-13 7:24 ` CK Hu (胡俊光)
2024-11-20 6:10 ` CK Hu (胡俊光)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-13 7:24 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtk_cam_ctx *mtk_cam_start_ctx(struct mtk_cam_device *cam,
> + struct mtk_cam_video_device *node)
> +{
> + struct mtk_cam_ctx *ctx = node->ctx;
> + struct device *dev;
> + struct v4l2_subdev **target_sd;
> + int ret, i, is_first_ctx;
> + struct media_entity *entity = &node->vdev.entity;
> + struct media_graph graph;
> +
> + dev_info(cam->dev, "%s:ctx(%d): triggered by %s\n",
> + __func__, ctx->stream_id, entity->name);
> +
> + atomic_set(&ctx->enqueued_frame_seq_no, 0);
> + ctx->composed_frame_seq_no = 0;
> + ctx->dequeued_frame_seq_no = 0;
> + atomic_set(&ctx->running_s_data_cnt, 0);
> + init_completion(&ctx->session_complete);
> + init_completion(&ctx->m2m_complete);
> +
> + is_first_ctx = !cam->composer_cnt;
> + if (is_first_ctx) {
> + spin_lock(&cam->dma_processing_lock);
> + cam->dma_processing_count = 0;
> + spin_unlock(&cam->dma_processing_lock);
> +
> + spin_lock(&cam->running_job_lock);
> + cam->running_job_count = 0;
> + spin_unlock(&cam->running_job_lock);
> +
> + dev_info(cam->dev, "%s: power on camsys\n", __func__);
> + ret = pm_runtime_resume_and_get(cam->dev);
> + if (ret < 0) {
> + dev_info(cam->dev, "%s: power on camsys failed\n",
> + __func__);
> + return NULL;
> + }
> +
> + ret = isp_composer_init(cam);
> + if (ret)
> + goto fail_shutdown;
> +
> + /* To catch camsys exception and trigger dump */
> + if (cam->debug_fs)
> + cam->debug_fs->ops->exp_reinit(cam->debug_fs);
> + }
> + cam->composer_cnt++;
> + if (is_yuv_node(node->desc.id))
> + dev = cam->raw.yuvs[0];
> + else
> + dev = cam->raw.devs[0];
> +
> + ret = mtk_cam_working_buf_pool_init(ctx, dev);
> + if (ret) {
> + dev_info(cam->dev, "failed to reserve DMA memory:%d\n", ret);
> + goto fail_uninit_composer;
> + }
> +
> + kthread_init_worker(&ctx->sensor_worker);
> + ctx->sensor_worker_task = kthread_run(kthread_worker_fn,
> + &ctx->sensor_worker,
> + "sensor_worker-%d",
> + ctx->stream_id);
> + if (IS_ERR(ctx->sensor_worker_task)) {
> + dev_info(cam->dev,
> + "%s:ctx(%d): could not create sensor_worker_task\n",
> + __func__, ctx->stream_id);
> + goto fail_release_buffer_pool;
> + }
> +
> + sched_set_fifo(ctx->sensor_worker_task);
> +
> + ctx->composer_wq = alloc_ordered_workqueue(dev_name(cam->dev),
> + WQ_HIGHPRI | WQ_FREEZABLE);
> + if (!ctx->composer_wq) {
> + dev_info(cam->dev, "failed to alloc composer workqueue\n");
> + goto fail_uninit_sensor_worker_task;
> + }
> +
> + ctx->frame_done_wq = alloc_ordered_workqueue(dev_name(cam->dev),
> + WQ_HIGHPRI | WQ_FREEZABLE);
> + if (!ctx->frame_done_wq) {
> + dev_info(cam->dev, "failed to alloc frame_done workqueue\n");
> + goto fail_uninit_composer_wq;
> + }
> +
> + ret = media_pipeline_start(&entity->pads[0], &ctx->pipeline);
> + if (ret) {
> + dev_warn(cam->dev,
> + "%s:pipe(%d):failed in media_pipeline_start:%d\n",
> + __func__, node->uid.pipe_id, ret);
> + goto fail_uninit_frame_done_wq;
> + }
> +
> + /* traverse to update used subdevs & number of nodes */
> + i = 0;
> + ret = media_graph_walk_init(&graph, entity->graph_obj.mdev);
> + if (ret)
> + goto fail_stop_pipeline;
> +
> + media_graph_walk_start(&graph, entity);
> + while ((entity = media_graph_walk_next(&graph))) {
> + dev_dbg(cam->dev, "linked entity %s\n", entity->name);
> +
> + target_sd = NULL;
> +
> + switch (entity->function) {
> + case MEDIA_ENT_F_IO_V4L:
> + ctx->enabled_node_cnt++;
> + break;
> + case MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER: /* pipeline */
> + if (i >= MAX_PIPES_PER_STREAM)
> + goto fail_stop_pipeline;
> + target_sd = ctx->pipe_subdevs + i;
> + i++;
> + break;
> + case MEDIA_ENT_F_VID_IF_BRIDGE: /* seninf */
> + target_sd = &ctx->seninf;
> + break;
> + case MEDIA_ENT_F_CAM_SENSOR:
This does not exist, so drop ctx->sensor.
Regards,
CK
> + target_sd = &ctx->sensor;
> + break;
> + default:
> + break;
> + }
> +
> + if (!target_sd)
> + continue;
> +
> + if (*target_sd) {
> + dev_info(cam->dev, "duplicated subdevs!!!\n");
> + goto fail_traverse_subdev;
> + }
> +
> + if (is_media_entity_v4l2_subdev(entity))
> + *target_sd = media_entity_to_v4l2_subdev(entity);
> + }
> + media_graph_walk_cleanup(&graph);
> +
> + return ctx;
> +
> +fail_traverse_subdev:
> + media_graph_walk_cleanup(&graph);
> +fail_stop_pipeline:
> + media_pipeline_stop(&entity->pads[0]);
> +fail_uninit_frame_done_wq:
> + destroy_workqueue(ctx->frame_done_wq);
> +fail_uninit_composer_wq:
> + destroy_workqueue(ctx->composer_wq);
> +fail_uninit_sensor_worker_task:
> + kthread_stop(ctx->sensor_worker_task);
> + ctx->sensor_worker_task = NULL;
> +fail_release_buffer_pool:
> + mtk_cam_working_buf_pool_release(ctx, dev);
> +fail_uninit_composer:
> + isp_composer_uninit(cam);
> + cam->composer_cnt--;
> +fail_shutdown:
> + if (is_first_ctx)
> + rproc_shutdown(cam->rproc_handle);
> +
> + return NULL;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (4 preceding siblings ...)
2024-11-06 5:58 ` CK Hu (胡俊光)
@ 2024-11-18 9:23 ` CK Hu (胡俊光)
2024-11-18 9:28 ` CK Hu (胡俊光)
` (3 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-18 9:23 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct seninf_vc {
> + u8 vc;
> + u8 dt;
> + u8 feature;
> + u8 out_pad;
> + u8 pixel_mode;
> + u8 group;
group is always zero, so drop this.
Regards,
CK
> + u8 mux; /* allocated per group */
> + u8 cam; /* assigned by cam driver */
> + u8 enable;
> + u16 exp_hsize;
> + u16 exp_vsize;
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (5 preceding siblings ...)
2024-11-18 9:23 ` CK Hu (胡俊光)
@ 2024-11-18 9:28 ` CK Hu (胡俊光)
2024-11-19 1:46 ` CK Hu (胡俊光)
` (2 subsequent siblings)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-18 9:28 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct seninf_vc {
> + u8 vc;
vc is always zero, so drop it.
Regards,
CK
> + u8 dt;
> + u8 feature;
> + u8 out_pad;
> + u8 pixel_mode;
> + u8 group;
> + u8 mux; /* allocated per group */
> + u8 cam; /* assigned by cam driver */
> + u8 enable;
> + u16 exp_hsize;
> + u16 exp_vsize;
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api
2024-11-06 13:04 ` Laurent Pinchart
@ 2024-11-18 9:58 ` Laurent Pinchart
0 siblings, 0 replies; 88+ messages in thread
From: Laurent Pinchart @ 2024-11-18 9:58 UTC (permalink / raw)
To: CK Hu (胡俊光)
Cc: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔),
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
On Wed, Nov 06, 2024 at 03:04:37PM +0200, Laurent Pinchart wrote:
> On Mon, Oct 14, 2024 at 05:56:40AM +0000, CK Hu (胡俊光) wrote:
> > Hi, Shu-hsiang:
> >
> > On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > > Add UAPI for MediaTek ISP platform, providing user-space
> > > interfaces for the new camsys driver.
> > >
> > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > > ---
> >
> > [snip]
> >
> > > +
> > > +/* MTK ISP camsys controls */
> > > +#define V4L2_CID_MTK_CAM_USED_ENGINE_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 1)
> > > +#define V4L2_CID_MTK_CAM_BIN_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 2)
> > > +#define V4L2_CID_MTK_CAM_FRZ_LIMIT (V4L2_CID_USER_MTK_CAM_BASE + 3)
> > > +#define V4L2_CID_MTK_CAM_RESOURCE_PLAN_POLICY (V4L2_CID_USER_MTK_CAM_BASE + 4)
> > > +#define V4L2_CID_MTK_CAM_USED_ENGINE (V4L2_CID_USER_MTK_CAM_BASE + 5)
> > > +#define V4L2_CID_MTK_CAM_BIN (V4L2_CID_USER_MTK_CAM_BASE + 6)
> > > +#define V4L2_CID_MTK_CAM_FRZ (V4L2_CID_USER_MTK_CAM_BASE + 7)
> > > +#define V4L2_CID_MTK_CAM_USED_ENGINE_TRY (V4L2_CID_USER_MTK_CAM_BASE + 8)
> > > +#define V4L2_CID_MTK_CAM_BIN_TRY (V4L2_CID_USER_MTK_CAM_BASE + 9)
> > > +#define V4L2_CID_MTK_CAM_FRZ_TRY (V4L2_CID_USER_MTK_CAM_BASE + 10)
> > > +#define V4L2_CID_MTK_CAM_PIXEL_RATE (V4L2_CID_USER_MTK_CAM_BASE + 11)
> > > +#define V4L2_CID_MTK_CAM_FEATURE (V4L2_CID_USER_MTK_CAM_BASE + 12)
> > > +#define V4L2_CID_MTK_CAM_SYNC_ID (V4L2_CID_USER_MTK_CAM_BASE + 13)
> > > +#define V4L2_CID_MTK_CAM_RAW_PATH_SELECT (V4L2_CID_USER_MTK_CAM_BASE + 14)
> > > +#define V4L2_CID_MTK_CAM_HSF_EN (V4L2_CID_USER_MTK_CAM_BASE + 15)
> > > +#define V4L2_CID_MTK_CAM_PDE_INFO (V4L2_CID_USER_MTK_CAM_BASE + 16)
> > > +#define V4L2_CID_MTK_CAM_MSTREAM_EXPOSURE (V4L2_CID_USER_MTK_CAM_BASE + 17)
> > > +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_CALC (V4L2_CID_USER_MTK_CAM_BASE + 18)
> > > +#define V4L2_CID_MTK_CAM_TG_FLASH_CFG (V4L2_CID_USER_MTK_CAM_BASE + 19)
> > > +#define V4L2_CID_MTK_CAM_RAW_RESOURCE_UPDATE (V4L2_CID_USER_MTK_CAM_BASE + 20)
> > > +#define V4L2_CID_MTK_CAM_CAMSYS_HW_MODE (V4L2_CID_USER_MTK_CAM_BASE + 21)
> > > +
> >
> > Please give introduction of how to use these user space interface.
>
> I'm very, very *not* thrilled by all this. It looks like a big pile of
> hacks really. Every single parameter used by those controls needs to be
> clearly documented, including explaining how they are used, in order for
> us to review the API. I suspect that many of the parameters should
> instead be handled through the ISP parameters buffers, or be controlled
> from standard V4L2 APIs.
While on the topic of documentation, we also need a high-level
architecture document. This patch series adds 30000 lines of code, it's
very hard for reviewers to understand the architecture of the driver
just by looking at the code. At the very least, a high-level description
of the hardware (at least from the view point of the interface the
firmware exposes) is needed.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 00/10] Add MediaTek ISP7 camera system driver
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
` (10 preceding siblings ...)
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
@ 2024-11-18 10:00 ` Laurent Pinchart
11 siblings, 0 replies; 88+ messages in thread
From: Laurent Pinchart @ 2024-11-18 10:00 UTC (permalink / raw)
To: Shu-hsiang Yang
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sumit Semwal, Christian Konig, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, dri-devel,
linaro-mm-sig, Project_Global_Chrome_Upstream_Group, yaya.chang,
teddy.chen, hidenorik, yunkec, shun-yi.wang
Hi Shu-hsiang,
On Wed, Oct 09, 2024 at 07:15:41PM +0800, Shu-hsiang Yang wrote:
> Based on linux-next/master, tag: next-20241008
>
> The patch set adds the MediaTek ISP7.x camera system hardware driver.
>
> This driver sets up ISP hardware, handles interrupts, and initializes
> V4L2 device nodes and functions. Moreover, implement V4L2 standard
> video driver that utilizes media framework APIs. It also connects
> the sensors and ISP, bridging with the seninf interface. Communicate
> with SCP co-processor to compose ISP registers in the firmware.
>
> These patches include CSI received data from sensors, sensor interface
> bridge, raw/YUV image pre-processing, ISP utility and ISP control parts.
>
> Thank you for reviewing these patches.
Could you please include the v4l2-compliance report for the driver in
the cover letter of the next version ? This is required for all new
drivers. Please use the very latest version of v4l2-compliance, compiled
from the master branch of v4l-utils.
> Shu-hsiang Yang (10):
> dt-bindings: media: mediatek: add camsys device
> media: platform: mediatek: add seninf controller
> media: platform: mediatek: add isp_7x seninf unit
> media: platform: mediatek: add isp_7x cam-raw unit
> media: platform: mediatek: add isp_7x camsys unit
> media: platform: mediatek: add isp_7x utility
> media: platform: mediatek: add isp_7x video ops
> media: platform: mediatek: add isp_7x state ctrl
> media: platform: mediatek: add isp_7x build config
> uapi: linux: add mediatek isp_7x camsys user api
>
> .../media/mediatek/mediatek,cam-raw.yaml | 169 +
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +
> .../media/mediatek/mediatek,camisp.yaml | 71 +
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +
> .../media/mediatek/mediatek,seninf.yaml | 88 +
> drivers/media/platform/mediatek/Kconfig | 1 +
> drivers/media/platform/mediatek/Makefile | 2 +
> drivers/media/platform/mediatek/isp/Kconfig | 21 +
> .../platform/mediatek/isp/isp_7x/Makefile | 7 +
> .../mediatek/isp/isp_7x/camsys/Makefile | 16 +
> .../isp_7x/camsys/kd_imgsensor_define_v4l2.h | 87 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c | 1797 ++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h | 140 +
> .../isp/isp_7x/camsys/mtk_cam-debug.c | 1271 ++++
> .../isp/isp_7x/camsys/mtk_cam-debug.h | 273 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-defs.h | 168 +
> .../isp/isp_7x/camsys/mtk_cam-dmadbg.h | 721 +++
> .../isp/isp_7x/camsys/mtk_cam-feature.c | 40 +
> .../isp/isp_7x/camsys/mtk_cam-feature.h | 26 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h | 87 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h | 233 +
> .../isp/isp_7x/camsys/mtk_cam-meta-mt8188.h | 2436 ++++++++
> .../isp/isp_7x/camsys/mtk_cam-plat-util.c | 207 +
> .../isp/isp_7x/camsys/mtk_cam-plat-util.h | 16 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.c | 393 ++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.h | 28 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 +
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++
> .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 +
> .../isp/isp_7x/camsys/mtk_cam-regs-mt8188.h | 382 ++
> .../isp/isp_7x/camsys/mtk_cam-seninf-def.h | 193 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-drv.c | 1741 ++++++
> .../isp/isp_7x/camsys/mtk_cam-seninf-drv.h | 16 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-hw.h | 120 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-if.h | 28 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-regs.h | 40 +
> .../isp/isp_7x/camsys/mtk_cam-seninf-route.c | 356 ++
> .../isp/isp_7x/camsys/mtk_cam-seninf-route.h | 23 +
> .../isp/isp_7x/camsys/mtk_cam-seninf.h | 170 +
> .../isp/isp_7x/camsys/mtk_cam-timesync.c | 125 +
> .../isp/isp_7x/camsys/mtk_cam-timesync.h | 12 +
> .../isp/isp_7x/camsys/mtk_cam-ufbc-def.h | 59 +
> .../isp/isp_7x/camsys/mtk_cam-video.c | 1817 ++++++
> .../isp/isp_7x/camsys/mtk_cam-video.h | 224 +
> .../mediatek/isp/isp_7x/camsys/mtk_cam.c | 4168 +++++++++++++
> .../mediatek/isp/isp_7x/camsys/mtk_cam.h | 733 +++
> .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 +
> .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 +++
> .../mtk_cam-seninf-csi0-cphy.h | 69 +
> .../mtk_cam-seninf-csi0-dphy.h | 139 +
> .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++
> .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 +
> .../mtk_cam-seninf-seninf1-csi2.h | 415 ++
> .../mtk_cam-seninf-seninf1-mux.h | 147 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 +
> .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 +
> include/uapi/linux/mtkisp_camsys.h | 227 +
> 60 files changed, 30194 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> create mode 100644 drivers/media/platform/mediatek/isp/Kconfig
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-defs.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-dmadbg.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-meta-mt8188.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-regs-mt8188.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ufbc-def.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h
> create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h
> create mode 100644 include/uapi/linux/mtkisp_camsys.h
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (6 preceding siblings ...)
2024-11-18 9:28 ` CK Hu (胡俊光)
@ 2024-11-19 1:46 ` CK Hu (胡俊光)
2024-11-19 1:50 ` CK Hu (胡俊光)
2024-11-20 6:35 ` CK Hu (胡俊光)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 1:46 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct seninf_vc {
> + u8 vc;
> + u8 dt;
> + u8 feature;
> + u8 out_pad;
> + u8 pixel_mode;
> + u8 group;
> + u8 mux; /* allocated per group */
> + u8 cam; /* assigned by cam driver */
> + u8 enable;
> + u16 exp_hsize;
exp_hsize is always zero, so drop it.
> + u16 exp_vsize;
Ditto.
Regards,
CK
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (7 preceding siblings ...)
2024-11-19 1:46 ` CK Hu (胡俊光)
@ 2024-11-19 1:50 ` CK Hu (胡俊光)
2024-11-20 6:35 ` CK Hu (胡俊光)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 1:50 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct seninf_cam_mux {
struct seninf_cam_mux{} is useless, so drop it.
Regards,
CK
> + struct list_head list;
> + int idx;
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
2024-10-16 3:43 ` CK Hu (胡俊光)
@ 2024-11-19 5:56 ` CK Hu (胡俊光)
0 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 5:56 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-16 at 11:43 +0800, CK Hu wrote:
> Hi, Shu-hsiang:
>
> On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> > The driver maintains the camera system, including sub-device management,
> > DMA operations, and integration with the V4L2 framework. It handles
> > request stream data, buffer management, and MediaTek-specific features,
> > and pipeline management, streaming control, error handling mechanism.
> > Additionally, it aggregates sub-drivers for the camera interface, raw
> > and yuv pipelines.
> >
> > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > ---
>
> [snip]
>
> > +static int mtk_cam_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_cam_device *cam_dev;
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + int ret;
> > + unsigned int i;
> > +
> > + dev_dbg(dev, "camsys | start %s\n", __func__);
> > +
> > + /* initialize structure */
> > + cam_dev = devm_kzalloc(dev, sizeof(*cam_dev), GFP_KERNEL);
> > + if (!cam_dev)
> > + return -ENOMEM;
> > +
> > + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) {
> > + dev_err(dev, "%s: No suitable DMA available\n", __func__);
> > + return -EIO;
> > + }
> > +
> > + if (!dev->dma_parms) {
> > + dev->dma_parms =
> > + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
> > + if (!dev->dma_parms)
> > + return -ENOMEM;
> > + }
> > +
> > + dma_set_max_seg_size(dev, UINT_MAX);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "failed to get mem\n");
> > + return -ENODEV;
> > + }
> > +
> > + cam_dev->base = devm_ioremap_resource(dev, res);
>
> I can not find any where to write register of this device.
> If so, I think we need not to probe this driver.
> The rest software control can be setup by other driver.
Ignore my previous comment. I find you need to power on/off this device.
So this probe is necessary.
Regards,
CK
>
> Regards,
> CK
>
> > + if (IS_ERR(cam_dev->base)) {
> > + dev_err(dev, "failed to map register base\n");
> > + return PTR_ERR(cam_dev->base);
> > + }
> > +
> > + cam_dev->dev = dev;
> > + dev_set_drvdata(dev, cam_dev);
> > +
> > + cam_dev->composer_cnt = 0;
> > + cam_dev->num_seninf_devices = 0;
> > +
> > + cam_dev->max_stream_num = MTKCAM_SUBDEV_MAX;
> > + cam_dev->ctxs = devm_kcalloc(dev, cam_dev->max_stream_num,
> > + sizeof(*cam_dev->ctxs), GFP_KERNEL);
> > + if (!cam_dev->ctxs)
> > + return -ENOMEM;
> > +
> > + cam_dev->streaming_ctx = 0;
> > + for (i = 0; i < cam_dev->max_stream_num; i++)
> > + mtk_cam_ctx_init(cam_dev->ctxs + i, cam_dev, i);
> > +
> > + cam_dev->running_job_count = 0;
> > + spin_lock_init(&cam_dev->pending_job_lock);
> > + spin_lock_init(&cam_dev->running_job_lock);
> > + INIT_LIST_HEAD(&cam_dev->pending_job_list);
> > + INIT_LIST_HEAD(&cam_dev->running_job_list);
> > +
> > + cam_dev->dma_processing_count = 0;
> > + spin_lock_init(&cam_dev->dma_pending_lock);
> > + spin_lock_init(&cam_dev->dma_processing_lock);
> > + INIT_LIST_HEAD(&cam_dev->dma_pending);
> > + INIT_LIST_HEAD(&cam_dev->dma_processing);
> > +
> > + mutex_init(&cam_dev->queue_lock);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = mtk_cam_of_rproc(cam_dev, pdev);
> > + if (ret)
> > + goto fail_destroy_mutex;
> > +
> > + ret = register_sub_drivers(dev);
> > + if (ret) {
> > + dev_err(dev, "fail to register_sub_drivers\n");
> > + goto fail_destroy_mutex;
> > + }
> > +
> > + /* register mtk_cam as all isp subdev async parent */
> > + cam_dev->notifier.ops = &mtk_cam_async_nf_ops;
> > + v4l2_async_nf_init(&cam_dev->notifier, &cam_dev->v4l2_dev);
> > + ret = mtk_cam_async_subdev_add(dev); /* wait all isp sub drivers */
> > + if (ret) {
> > + dev_err(dev, "%s failed mtk_cam_async_subdev_add\n", __func__);
> > + goto fail_unregister_sub_drivers;
> > + }
> > +
> > + ret = v4l2_async_nf_register(&cam_dev->notifier);
> > + if (ret) {
> > + dev_err(dev, "%s async_nf_register ret:%d\n", __func__, ret);
> > + v4l2_async_nf_cleanup(&cam_dev->notifier);
> > + goto fail_unregister_sub_drivers;
> > + }
> > +
> > + ret = mtk_cam_debug_fs_init(cam_dev);
> > + if (ret < 0)
> > + goto fail_unregister_async_nf;
> > +
> > + dev_info(dev, "camsys | [%s] success\n", __func__);
> > +
> > + return 0;
> > +
> > +fail_unregister_async_nf:
> > + v4l2_async_nf_unregister(&cam_dev->notifier);
> > +
> > +fail_unregister_sub_drivers:
> > + unregister_sub_drivers(dev);
> > +
> > +fail_destroy_mutex:
> > + mutex_destroy(&cam_dev->queue_lock);
> > +
> > + return ret;
> > +}
> > +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (11 preceding siblings ...)
2024-11-06 7:01 ` CK Hu (胡俊光)
@ 2024-11-19 8:23 ` CK Hu (胡俊光)
2024-11-19 8:29 ` CK Hu (胡俊光)
` (3 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 8:23 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct mtkcam_ipi_config_param {
> + u8 flags;
> + struct mtkcam_ipi_input_param input;
> + u8 n_maps;
Driver always set n_maps = 1, when would it be other value?
If it is always 1, drop it and let firmware just support 1.
> + /* maximum # of pipes per stream */
> + struct mtkcam_ipi_hw_mapping maps[6];
> + /* sub_ratio:8, valid number: 8 */
> + u16 valid_numbers[MTKCAM_IPI_FBCX_LAST];
valid_numbers is useless, so drop it.
Regards,
CK
> + u8 sw_feature;
> +} __packed;
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (12 preceding siblings ...)
2024-11-19 8:23 ` CK Hu (胡俊光)
@ 2024-11-19 8:29 ` CK Hu (胡俊光)
2024-11-19 9:41 ` CK Hu (胡俊光)
` (2 subsequent siblings)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 8:29 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/* For LBIT_MODE G2 */
> +enum mtkcam_ipi_sw_feature_control {
> + MTKCAM_IPI_SW_FEATURE_NORMAL = 0,
> + /* Normal */
> +};
> +
[snip]
> +struct mtkcam_ipi_config_param {
> + u8 flags;
> + struct mtkcam_ipi_input_param input;
> + u8 n_maps;
> + /* maximum # of pipes per stream */
> + struct mtkcam_ipi_hw_mapping maps[6];
> + /* sub_ratio:8, valid number: 8 */
> + u16 valid_numbers[MTKCAM_IPI_FBCX_LAST];
> + u8 sw_feature;
Only one sw_feature (MTKCAM_IPI_SW_FEATURE_NORMAL). So it's not necessary to pass this information to scp.
Drop this and MTKCAM_IPI_SW_FEATURE_NORMAL.
Regards,
CK
> +} __packed;
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (13 preceding siblings ...)
2024-11-19 8:29 ` CK Hu (胡俊光)
@ 2024-11-19 9:41 ` CK Hu (胡俊光)
2024-11-20 2:21 ` CK Hu (胡俊光)
2024-11-20 5:21 ` CK Hu (胡俊光)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-19 9:41 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +/*
> + * The IPI command enumeration.
> + */
> +enum mtkcam_ipi_cmds {
> + /* request for a new streaming: mtkcam_ipi_session_param */
> + CAM_CMD_CREATE_SESSION,
> + /* config the stream: mtkcam_ipi_config_param */
> + CAM_CMD_CONFIG,
> + /* per-frame: mtkcam_ipi_frame_param */
> + CAM_CMD_FRAME,
> + /* release certain streaming: mtkcam_ipi_session_param */
> + CAM_CMD_DESTROY_SESSION,
> + /* ack: mtkcam_ipi_ack_info */
> + CAM_CMD_ACK,
> + CAM_CMD_RESERVED,
It's not necessary to have CAM_CMD_RESERVED. Drop it.
Regards,
CK
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops
2024-10-09 11:15 ` [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops Shu-hsiang Yang
2024-11-04 3:24 ` CK Hu (胡俊光)
@ 2024-11-20 1:05 ` CK Hu (胡俊光)
1 sibling, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 1:05 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the V4L2 video interface and feature management for the
> MediaTek ISP7x CAMSYS. These interfaces include various functionalities,
> such as video operation initialization and registration. They also
> manage MediaTek-specific formats and handle buffers for MediaTek camera
> video devices. This integrates CAMSYS functionalities to be compatible
> with the V4L2 framework.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +int mtk_cam_video_register(struct mtk_cam_video_device *video,
> + struct v4l2_device *v4l2_dev)
> +{
> + struct mtk_cam_device *cam =
> + container_of(v4l2_dev, struct mtk_cam_device, v4l2_dev);
> + struct media_pad *pad = &video->pad;
> + struct video_device *vdev = &video->vdev;
> + struct vb2_queue *q = &video->vb2_q;
> + unsigned int output = V4L2_TYPE_IS_OUTPUT(video->desc.buf_type);
> + int ret;
> +
> + if (video->desc.link_flags & MEDIA_LNK_FL_ENABLED)
> + video->enabled = true;
> + else
> + video->enabled = false;
> +
> + mutex_init(&video->q_lock);
> +
> + /* initialize vb2_queue */
> + q->type = video->desc.buf_type;
> + q->io_modes = VB2_MMAP | VB2_DMABUF;
> +
> + if (q->type == V4L2_BUF_TYPE_META_OUTPUT)
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + else
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_BOOTIME;
Why V4L2_BUF_TYPE_META_OUTPUT use different timestamp flag?
Different output data is generate at the same time,
so use the same timestamp so we are able to link these output data to the same frame.
And I could not find anywhere to define V4L2_BUF_FLAG_TIMESTAMP_BOOTIME.
So drop V4L2_BUF_FLAG_TIMESTAMP_BOOTIME and use V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC for all queue.
Regards,
CK
> +
> + if (video->desc.smem_alloc) {
> + q->bidirectional = 1;
> + /* reserved memory */
> + q->dev = cam->smem_dev;
> + } else if (is_yuv_node(video->desc.id)) {
> + q->dev = cam->raw.yuvs[0];
> + } else {
> + q->dev = cam->raw.devs[0];
> + }
> +
> + q->supports_requests = true;
> + q->lock = &video->q_lock;
> + q->ops = &mtk_cam_vb2_ops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->drv_priv = cam;
> + q->buf_struct_size = sizeof(struct mtk_cam_buffer);
> +
> + if (output)
> + q->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
> + else
> + q->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_SOE;
> +
> + /* No minimum buffers limitation */
> + q->min_queued_buffers = 0;
> +
> + ret = vb2_queue_init(q);
> + if (ret < 0) {
> + dev_info(v4l2_dev->dev, "Failed to init vb2 queue: %d\n", ret);
> + goto error_vb2_init;
> + }
> +
> + pad->flags = output ? MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;
> + ret = media_entity_pads_init(&vdev->entity, 1, pad);
> + if (ret < 0) {
> + dev_info(v4l2_dev->dev, "Failed to init video entity: %d\n", ret);
> + goto error_media_init;
> + }
> +
> + ret = mtk_video_init_format(video);
> + if (ret < 0) {
> + dev_info(v4l2_dev->dev, "Failed to init format: %d\n", ret);
> + goto error_video_register;
> + }
> +
> + vdev->entity.function = MEDIA_ENT_F_IO_V4L;
> + vdev->entity.ops = NULL;
> + vdev->fops = &mtk_cam_v4l2_fops;
> + vdev->device_caps = video->desc.cap | V4L2_CAP_STREAMING;
> + vdev->v4l2_dev = v4l2_dev;
> +
> + vdev->vfl_dir = output ? VFL_DIR_TX : VFL_DIR_RX;
> + vdev->queue = &video->vb2_q;
> + vdev->ioctl_ops = video->desc.ioctl_ops;
> + vdev->release = video_device_release_empty;
> + /* share q_lock */
> + vdev->lock = &video->q_lock;
> + strscpy(vdev->name, video->desc.name, sizeof(vdev->name));
> +
> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> + if (ret < 0) {
> + dev_info(v4l2_dev->dev, "Failed to register video device: %d\n",
> + ret);
> + goto error_video_register;
> + }
> + video_set_drvdata(vdev, cam);
> +
> + dev_dbg(v4l2_dev->dev, "registered vdev:%d:%s\n",
> + video->desc.id, vdev->name);
> +
> + return 0;
> +
> +error_video_register:
> + media_entity_cleanup(&vdev->entity);
> +error_media_init:
> + vb2_queue_release(&video->vb2_q);
> +error_vb2_init:
> + mutex_destroy(&video->q_lock);
> +
> + return ret;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (14 preceding siblings ...)
2024-11-19 9:41 ` CK Hu (胡俊光)
@ 2024-11-20 2:21 ` CK Hu (胡俊光)
2024-11-20 6:03 ` CK Hu (胡俊光)
2024-11-20 5:21 ` CK Hu (胡俊光)
16 siblings, 1 reply; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 2:21 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +
> +enum mtkcam_ipi_raw_video_id {
It's better to use 'scp' instead of 'ipi'.
The interface is provided by scp.
ipi just transfer data between mtkcam and scp and ipi does not care the data content.
> + MTKCAM_IPI_RAW_ID_UNKNOWN = 0,
Ditto.
> + MTKCAM_IPI_RAW_RAWI_2, /* RAWI_R2 */
Ditto.
> + MTKCAM_IPI_RAW_RAWI_3, /* RAWI_R3 */
Ditto.
> + MTKCAM_IPI_RAW_RAWI_5, /* RAWI_R5 */
Ditto.
> + MTKCAM_IPI_RAW_RAWI_6, /* RAWI_R6 */
> + MTKCAM_IPI_RAW_IMGO, /* IMGO_R1 */
> + MTKCAM_IPI_RAW_UFEO, /* UFEO_R1 */
> + MTKCAM_IPI_RAW_RRZO, /* RRZO_R1 */
> + MTKCAM_IPI_RAW_UFGO, /* UFGO_R1 */
> + MTKCAM_IPI_RAW_YUVO_1, /* YUVO_R1 */
> + MTKCAM_IPI_RAW_YUVO_2, /* YUVO_R2 */
> + MTKCAM_IPI_RAW_YUVO_3, /* YUVO_R3 */
> + MTKCAM_IPI_RAW_YUVO_4, /* YUVO_R4 */
> + MTKCAM_IPI_RAW_YUVO_5, /* YUVO_R5 */
> + MTKCAM_IPI_RAW_RZH1N2TO_2, /* RZH1N2TO_R2 */
> + MTKCAM_IPI_RAW_DRZS4NO_1, /* DRZS4NO_R1 */
> + MTKCAM_IPI_RAW_DRZS4NO_2, /* DRZS4NO_R2 */
> + MTKCAM_IPI_RAW_DRZS4NO_3, /* DRZS4NO_R3 */
> + MTKCAM_IPI_RAW_RZH1N2TO_3, /* RZH1N2TO_R3 */
> + MTKCAM_IPI_RAW_RZH1N2TO_1, /* RZH1N2TO_R1 */
> + MTKCAM_IPI_RAW_META_STATS_CFG, /* All settings */
> + MTKCAM_IPI_RAW_META_STATS_0, /* statistics */
> +
> + /*
> + * MTKCAM_IPI_RAW_META_STATS_1 is for AFO only, the buffer can be
> + * dequeued once we got the dma done.
> + */
> + MTKCAM_IPI_RAW_META_STATS_1,
> +
> + /* statistics may be pass to DIP */
> + MTKCAM_IPI_RAW_META_STATS_2,
> + MTKCAM_IPI_RAW_ID_MAX,
> +};
> +
> +/* Supported bayer pixel order */
> +enum mtkcam_ipi_bayer_pxl_id {
Ditto.
Regards,
CK
> + MTKCAM_IPI_BAYER_PXL_ID_B = 0,
> + MTKCAM_IPI_BAYER_PXL_ID_GB = 1,
> + MTKCAM_IPI_BAYER_PXL_ID_GR = 2,
> + MTKCAM_IPI_BAYER_PXL_ID_R = 3,
> + MTKCAM_IPI_BAYER_PXL_ID_UNKNOWN = 4,
> +};
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
` (15 preceding siblings ...)
2024-11-20 2:21 ` CK Hu (胡俊光)
@ 2024-11-20 5:21 ` CK Hu (胡俊光)
16 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 5:21 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces utility files for the MediaTek ISP7.x camsys driver. These
> utilities provide essential platform definitions, debugging tools, and
> management functions to support ISP operations and SCP communication.
> Key functionalities include:
> 1.Hardware pipeline and register definitions for managing image
> processing modules.
> 2.DMA debugging utilities and buffer management functions.
> 3.Definitions of supported image formats for proper data handling.
> 4.IPI and SCP communication structures for module state management and
> configuring ISP.
> 5.Metadata parameters for configuring image processing.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static void vb2_sync_for_device(void *buf_priv)
> +{
> + struct mtk_cam_vb2_buf *buf = buf_priv;
> + struct sg_table *sgt = buf->dma_sgt;
I could not find anywhere to use struct mtk_cam_vb2_buf and set buf->dma_sgt.
I think buf_priv is set by vb2 framework.
Follow the standard vb2 framework to sync for device. (Maybe the vb2 framework already do this)
And drop struct mtk_cam_vb2_buf{}.
Regards,
CK
> +
> + if (!sgt)
> + return;
> +
> + dma_sync_sgtable_for_device(buf->dev, sgt, buf->dma_dir);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility
2024-11-20 2:21 ` CK Hu (胡俊光)
@ 2024-11-20 6:03 ` CK Hu (胡俊光)
0 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 6:03 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-11-20 at 10:21 +0800, CK Hu wrote:
> Hi, Shu-hsiang:
>
> On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> > Introduces utility files for the MediaTek ISP7.x camsys driver. These
> > utilities provide essential platform definitions, debugging tools, and
> > management functions to support ISP operations and SCP communication.
> > Key functionalities include:
> > 1.Hardware pipeline and register definitions for managing image
> > processing modules.
> > 2.DMA debugging utilities and buffer management functions.
> > 3.Definitions of supported image formats for proper data handling.
> > 4.IPI and SCP communication structures for module state management and
> > configuring ISP.
> > 5.Metadata parameters for configuring image processing.
> >
> > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> > ---
>
> [snip]
>
> > +
> > +enum mtkcam_ipi_raw_video_id {
>
> It's better to use 'scp' instead of 'ipi'.
> The interface is provided by scp.
> ipi just transfer data between mtkcam and scp and ipi does not care the data content.
Forget my previous comment.
I find the scp command is SCP_IPI_ISP_CMD or SCP_IPI_ISP_FRAME.
So maybe the prefix should be scp_ipi_isp so some shorter symbol like isp.
Regards,
CK
>
> > + MTKCAM_IPI_RAW_ID_UNKNOWN = 0,
>
> Ditto.
>
> > + MTKCAM_IPI_RAW_RAWI_2, /* RAWI_R2 */
>
> Ditto.
>
> > + MTKCAM_IPI_RAW_RAWI_3, /* RAWI_R3 */
>
> Ditto.
>
> > + MTKCAM_IPI_RAW_RAWI_5, /* RAWI_R5 */
>
> Ditto.
>
> > + MTKCAM_IPI_RAW_RAWI_6, /* RAWI_R6 */
> > + MTKCAM_IPI_RAW_IMGO, /* IMGO_R1 */
> > + MTKCAM_IPI_RAW_UFEO, /* UFEO_R1 */
> > + MTKCAM_IPI_RAW_RRZO, /* RRZO_R1 */
> > + MTKCAM_IPI_RAW_UFGO, /* UFGO_R1 */
> > + MTKCAM_IPI_RAW_YUVO_1, /* YUVO_R1 */
> > + MTKCAM_IPI_RAW_YUVO_2, /* YUVO_R2 */
> > + MTKCAM_IPI_RAW_YUVO_3, /* YUVO_R3 */
> > + MTKCAM_IPI_RAW_YUVO_4, /* YUVO_R4 */
> > + MTKCAM_IPI_RAW_YUVO_5, /* YUVO_R5 */
> > + MTKCAM_IPI_RAW_RZH1N2TO_2, /* RZH1N2TO_R2 */
> > + MTKCAM_IPI_RAW_DRZS4NO_1, /* DRZS4NO_R1 */
> > + MTKCAM_IPI_RAW_DRZS4NO_2, /* DRZS4NO_R2 */
> > + MTKCAM_IPI_RAW_DRZS4NO_3, /* DRZS4NO_R3 */
> > + MTKCAM_IPI_RAW_RZH1N2TO_3, /* RZH1N2TO_R3 */
> > + MTKCAM_IPI_RAW_RZH1N2TO_1, /* RZH1N2TO_R1 */
> > + MTKCAM_IPI_RAW_META_STATS_CFG, /* All settings */
> > + MTKCAM_IPI_RAW_META_STATS_0, /* statistics */
> > +
> > + /*
> > + * MTKCAM_IPI_RAW_META_STATS_1 is for AFO only, the buffer can be
> > + * dequeued once we got the dma done.
> > + */
> > + MTKCAM_IPI_RAW_META_STATS_1,
> > +
> > + /* statistics may be pass to DIP */
> > + MTKCAM_IPI_RAW_META_STATS_2,
> > + MTKCAM_IPI_RAW_ID_MAX,
> > +};
> > +
> > +/* Supported bayer pixel order */
> > +enum mtkcam_ipi_bayer_pxl_id {
>
> Ditto.
>
> Regards,
> CK
>
> > + MTKCAM_IPI_BAYER_PXL_ID_B = 0,
> > + MTKCAM_IPI_BAYER_PXL_ID_GB = 1,
> > + MTKCAM_IPI_BAYER_PXL_ID_GR = 2,
> > + MTKCAM_IPI_BAYER_PXL_ID_R = 3,
> > + MTKCAM_IPI_BAYER_PXL_ID_UNKNOWN = 4,
> > +};
> > +
>
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
` (11 preceding siblings ...)
2024-11-13 7:24 ` CK Hu (胡俊光)
@ 2024-11-20 6:10 ` CK Hu (胡俊光)
12 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 6:10 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the top media device driver for the MediaTek ISP7X CAMSYS.
> The driver maintains the camera system, including sub-device management,
> DMA operations, and integration with the V4L2 framework. It handles
> request stream data, buffer management, and MediaTek-specific features,
> and pipeline management, streaming control, error handling mechanism.
> Additionally, it aggregates sub-drivers for the camera interface, raw
> and yuv pipelines.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static int isp_composer_init(struct mtk_cam_device *cam)
> +{
> + struct device *dev = cam->dev;
> + int ret;
> +
> + ret = rproc_boot(cam->rproc_handle);
> + if (ret) {
> + dev_err(dev, "failed to rproc_boot\n");
> + return ret;
> + }
> +
> + ret = scp_ipi_register(cam->scp, SCP_IPI_ISP_CMD,
> + isp_composer_handler, cam);
> + if (ret) {
> + dev_err(dev, "failed to register IPI cmd\n");
> + return ret;
> + }
> +
> + ret = scp_ipi_register(cam->scp, SCP_IPI_ISP_FRAME,
> + isp_composer_handler, cam);
SCP_IPI_ISP_CMD and SCP_IPI_ISP_FRAME use different way to handler ack.
So do not use the common function isp_composer_handler to handler different command.
Use different handler function.
Regards,
CK
> + if (ret) {
> + dev_err(dev, "failed to register IPI frame\n");
> + goto unreg_ipi_cmd;
> + }
> +
> + return 0;
> +
> +unreg_ipi_cmd:
> + scp_ipi_unregister(cam->scp, SCP_IPI_ISP_CMD);
> +
> + return ret;
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
` (8 preceding siblings ...)
2024-11-19 1:50 ` CK Hu (胡俊光)
@ 2024-11-20 6:35 ` CK Hu (胡俊光)
9 siblings, 0 replies; 88+ messages in thread
From: CK Hu (胡俊光) @ 2024-11-20 6:35 UTC (permalink / raw)
To: sumit.semwal@linaro.org, christian.koenig@amd.com,
mchehab@kernel.org, conor+dt@kernel.org, robh@kernel.org,
matthias.bgg@gmail.com, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Shu-hsiang Yang (楊舒翔)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
yunkec@chromium.org, linaro-mm-sig@lists.linaro.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Yaya Chang (張雅清),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org,
Teddy Chen (陳乾元),
linux-arm-kernel@lists.infradead.org, hidenorik@chromium.org,
Shun-Yi Wang (王順億)
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the driver of the MediaTek Sensor Interface,
> focusing on integration with the MediaTek ISP CAMSYS. The
> seninf device bridges camera sensors and the ISP system,
> providing management for sensor data routing and processing.
> Key features include V4L2 framework control, and dynamic
> handling of stream configurations and virtual channels.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +struct seninf_mux *mtk_cam_seninf_mux_get_pref(struct seninf_ctx *ctx,
> + int *pref_idx, int pref_cnt)
> +{
> + int i;
> + struct seninf_core *core = ctx->core;
> + struct seninf_mux *ent = NULL;
> +
> + mutex_lock(&core->mutex);
> +
> + list_for_each_entry(ent, &core->list_mux, list) {
> + for (i = 0; i < pref_cnt; i++) {
> + if (ent->idx == pref_idx[i]) {
There is only two place to call mtk_cam_seninf_mux_get_pref(), and both place just make sure that pref_idx[i] = i.
So it's not necessary to pass an array as parameter. This code could be
if (ent->idx == i) {
...
}
Regards,
CK
> + list_move_tail(&ent->list, &ctx->list_mux);
> + mutex_unlock(&core->mutex);
> + return ent;
> + }
> + }
> + }
> +
> + mutex_unlock(&core->mutex);
> +
> + return mtk_cam_seninf_mux_get(ctx);
> +}
> +
^ permalink raw reply [flat|nested] 88+ messages in thread
end of thread, other threads:[~2024-11-20 6:37 UTC | newest]
Thread overview: 88+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-09 11:15 [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Shu-hsiang Yang
2024-10-09 11:15 ` [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device Shu-hsiang Yang
2024-10-09 21:00 ` Rob Herring
2024-10-11 1:29 ` CK Hu (胡俊光)
2024-10-11 3:20 ` CK Hu (胡俊光)
2024-10-22 5:36 ` Krzysztof Kozlowski
2024-11-11 1:37 ` CK Hu (胡俊光)
2024-11-11 2:38 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 03/10] media: platform: mediatek: add isp_7x seninf unit Shu-hsiang Yang
2024-10-14 9:25 ` CK Hu (胡俊光)
2024-10-18 8:54 ` CK Hu (胡俊光)
2024-10-28 1:27 ` CK Hu (胡俊光)
2024-10-28 1:30 ` CK Hu (胡俊光)
2024-11-06 5:58 ` CK Hu (胡俊光)
2024-11-18 9:23 ` CK Hu (胡俊光)
2024-11-18 9:28 ` CK Hu (胡俊光)
2024-11-19 1:46 ` CK Hu (胡俊光)
2024-11-19 1:50 ` CK Hu (胡俊光)
2024-11-20 6:35 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 07/10] media: platform: mediatek: add isp_7x video ops Shu-hsiang Yang
2024-11-04 3:24 ` CK Hu (胡俊光)
2024-11-20 1:05 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 09/10] media: platform: mediatek: add isp_7x build config Shu-hsiang Yang
2024-10-16 1:56 ` CK Hu (胡俊光)
2024-10-09 11:15 ` [PATCH v1 10/10] uapi: linux: add mediatek isp_7x camsys user api Shu-hsiang Yang
2024-10-11 7:47 ` CK Hu (胡俊光)
2024-10-14 5:56 ` CK Hu (胡俊光)
2024-11-06 13:04 ` Laurent Pinchart
2024-11-18 9:58 ` Laurent Pinchart
2024-11-05 5:36 ` CK Hu (胡俊光)
[not found] ` <20241009111551.27052-3-Shu-hsiang.Yang@mediatek.com>
2024-10-09 12:50 ` [PATCH v1 02/10] media: platform: mediatek: add seninf controller AngeloGioacchino Del Regno
2024-10-11 1:36 ` CK Hu (胡俊光)
2024-10-11 2:38 ` CK Hu (胡俊光)
2024-10-22 4:16 ` CK Hu (胡俊光)
2024-10-28 1:55 ` CK Hu (胡俊光)
2024-10-15 18:40 ` [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Nicolas Dufresne
[not found] ` <20241009111551.27052-9-Shu-hsiang.Yang@mediatek.com>
2024-10-16 1:35 ` [PATCH v1 08/10] media: platform: mediatek: add isp_7x state ctrl CK Hu (胡俊光)
2024-10-28 5:20 ` CK Hu (胡俊光)
2024-10-28 5:25 ` CK Hu (胡俊光)
2024-10-28 5:34 ` CK Hu (胡俊光)
[not found] ` <20241009111551.27052-6-Shu-hsiang.Yang@mediatek.com>
2024-10-14 9:40 ` [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit CK Hu (胡俊光)
2024-10-16 3:43 ` CK Hu (胡俊光)
2024-11-19 5:56 ` CK Hu (胡俊光)
2024-10-22 5:44 ` Krzysztof Kozlowski
2024-10-22 6:48 ` CK Hu (胡俊光)
2024-10-29 2:35 ` CK Hu (胡俊光)
2024-10-29 6:47 ` CK Hu (胡俊光)
2024-10-29 7:03 ` CK Hu (胡俊光)
2024-10-30 3:20 ` CK Hu (胡俊光)
2024-10-30 5:43 ` CK Hu (胡俊光)
2024-11-04 6:08 ` CK Hu (胡俊光)
2024-11-04 13:06 ` [PATCH " Markus Elfring
2024-11-06 7:52 ` [PATCH v1 " CK Hu (胡俊光)
2024-11-13 7:24 ` CK Hu (胡俊光)
2024-11-20 6:10 ` CK Hu (胡俊光)
[not found] ` <20241009111551.27052-7-Shu-hsiang.Yang@mediatek.com>
2024-10-14 5:21 ` [PATCH v1 06/10] media: platform: mediatek: add isp_7x utility CK Hu (胡俊光)
2024-10-22 5:30 ` CK Hu (胡俊光)
2024-10-28 3:46 ` CK Hu (胡俊光)
2024-10-29 5:35 ` CK Hu (胡俊光)
2024-11-04 2:26 ` CK Hu (胡俊光)
2024-11-05 3:33 ` CK Hu (胡俊光)
2024-11-05 8:43 ` CK Hu (胡俊光)
2024-11-05 9:14 ` CK Hu (胡俊光)
2024-11-06 3:35 ` CK Hu (胡俊光)
2024-11-06 3:41 ` CK Hu (胡俊光)
2024-11-06 3:48 ` CK Hu (胡俊光)
2024-11-06 7:01 ` CK Hu (胡俊光)
2024-11-19 8:23 ` CK Hu (胡俊光)
2024-11-19 8:29 ` CK Hu (胡俊光)
2024-11-19 9:41 ` CK Hu (胡俊光)
2024-11-20 2:21 ` CK Hu (胡俊光)
2024-11-20 6:03 ` CK Hu (胡俊光)
2024-11-20 5:21 ` CK Hu (胡俊光)
[not found] ` <20241009111551.27052-5-Shu-hsiang.Yang@mediatek.com>
2024-10-10 12:49 ` [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit AngeloGioacchino Del Regno
2024-10-11 2:23 ` CK Hu (胡俊光)
2024-10-11 2:55 ` CK Hu (胡俊光)
2024-10-11 5:40 ` CK Hu (胡俊光)
2024-10-11 6:03 ` CK Hu (胡俊光)
2024-10-22 5:43 ` Krzysztof Kozlowski
2024-10-22 6:14 ` CK Hu (胡俊光)
2024-10-22 6:30 ` CK Hu (胡俊光)
2024-10-23 10:05 ` CK Hu (胡俊光)
2024-10-25 6:30 ` CK Hu (胡俊光)
2024-10-28 6:48 ` CK Hu (胡俊光)
2024-11-04 2:35 ` CK Hu (胡俊光)
2024-11-04 8:04 ` CK Hu (胡俊光)
2024-11-05 3:01 ` CK Hu (胡俊光)
2024-11-18 10:00 ` [PATCH v1 00/10] Add MediaTek ISP7 camera system driver Laurent Pinchart
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