From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E08FACEE34F for ; Wed, 9 Oct 2024 21:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HtmrrjWLt/XYMKSHKXvShEhTnkV/YFhRLlOyxU6uA74=; b=uHtoxk8tVP39V4eEOYFpAW/G9+ DTIsU9vdL4chmMs+DwSoc5j3uuknpSDkGHs0Vq87NXf1RqsQDeXZCKS3mAXOwhfOe679CUMPtzd4M Of9rtCPeTN7ODqmjrTcc49OJuxxdYFtgdy9pz4Q+y8ZtGhbjpyjloPHwN37kLqiizdkoE9aZOhmZd 4twrGezglpMnlXs3D5GjQ9MA1fbOEMGj/tL3/ZPE+ghF/WGBZG1fNL/5ti5Ju2bWFQB8nXSgQjteR yftHT0PZDUE2EKIvIkPPdcOyvtv/UPZH2j+tMds4lNbIyQaIYvJ4qkDtHEOic4d28Y1N1TYxzHVlT awcr7tNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sydz8-0000000Ajvc-30yo; Wed, 09 Oct 2024 21:12:42 +0000 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sydxn-0000000Ajii-38hW for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 21:11:21 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id DC49BA445A1; Wed, 9 Oct 2024 21:11:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0B49C4CEC3; Wed, 9 Oct 2024 21:11:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728508278; bh=2qQdeHWaX+qTxGR0KQZi4qkIcfoXEQWS9Egj0Q4nlf4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AGgRIQKNVPuCm/Ouid8MPqRKI3K90ejJcdcKpPB8YxRDkqFsG64eUWGa0uYxlxayn RYHOso+H6e9C0KlL6R1BFsrZrlFp3dFPkB5vhaHIP0VLr3K6IsTxzHwqOPbM5sLTcE b/Ak83oCC9ep8LThG1oxTmU3ai+ewYmbl7biY9noBbyiWXVtwV10kQeZNyD68oqSA1 pHDyLzQu6dqBXY5K9ir2ySoTRPwfS7ArseORsVHhGLh079BfQY3AAsf4zu/vC7fHzR FY8xZ2aXkhG7p4yMWUH1QyMHqcgUmPHmlqEdax0MwsK8ZsW0KQB5pWyZzPyTDy/oj7 v1Ef5s59J/75A== Date: Wed, 9 Oct 2024 16:11:16 -0500 From: Rob Herring To: Kevin Chen Cc: tglx@linutronix.de, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org Subject: Re: [PATCH v3 1/2] dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC Message-ID: <20241009211116.GA676770-robh@kernel.org> References: <20241009115813.2908803-1-kevin_chen@aspeedtech.com> <20241009115813.2908803-2-kevin_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241009115813.2908803-2-kevin_chen@aspeedtech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_141119_939888_BF59C88A X-CRM114-Status: GOOD ( 21.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 09, 2024 at 07:58:12PM +0800, Kevin Chen wrote: > The ASPEED AST27XX interrupt controller(INTC) contain second level and > third level interrupt controller. > > INTC0: > The second level INTC, which used to assert GIC(#192~#197) if interrupt > in INTC1 asserted. There are 6 GIC interrupt number(#192~#197) used in > one INTC0. > > INTC1_x: > The third level INTC, which used to assert GIC(#192~#197) if interrupt in > INTC1 asserted. There are 6 GIC interrupt number(#192~#197) used in one INTC0. > > Signed-off-by: Kevin Chen > --- > .../aspeed,ast2700-intc.yaml | 87 +++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml > new file mode 100644 > index 000000000000..650a1f6e1177 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed AST2700 Interrupt Controller > + > +description: > + This interrupt controller hardware is second level interrupt controller that > + is hooked to a parent interrupt controller. It's useful to combine multiple > + interrupt sources into 1 interrupt to parent interrupt controller. > + > +maintainers: > + - Kevin Chen > + > +properties: > + compatible: > + enum: > + - aspeed,ast2700-intc-ic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 2 Describe the meaning of the cells here. > + > + interrupts: > + maxItems: 10 > + description: You need '|' to preserve formatting. > + Depend to which INTC0 or INTC1 used. > + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw > + status registers for use. > + INTC0 is used to assert GIC if interrupt in INTC1 asserted. > + INTC1 is used to assert INTC0 if interrupt of modules asserted. > + +-----+ +-------+ +---------+---module0 > + | GIC |---| INTC0 |--+--| INTC1_0 |---module2 > + | | | | | | |---... > + +-----+ +-------+ | +---------+---module31 > + | > + | +---------+---module0 > + +---| INTC1_1 |---module2 > + | | |---... > + | +---------+---module31 > + ... > + | +---------+---module0 > + +---| INTC1_5 |---module2 > + | |---... > + +---------+---module31 > + > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - '#interrupt-cells' > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + interrupt-controller@12101b00 { > + compatible = "aspeed,ast2700-intc-ic"; > + reg = <0 0x12101b00 0 0x10>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + }; > -- > 2.34.1 >