[PATCH v7 0/3] PCIe RK3399 clock and reset using new helper functions

[PATCH v7 0/3] PCIe RK3399 clock and reset using new helper functions

[Anand Moon]

Following changes are used to reduce the code and used new
clk_bulk and reset_control_bulk helper functions.

Additional to the PCie core controller changes
added some new PHY changes to help improve and clean up
the code.

Made lots of silly mistakes.

Previous changes.
v6:
https://lore.kernel.org/r/20241006182445.3713-2-linux.amoon@gmail.com/
v5:
https://lore.kernel.org/all/20240901183221.240361-2-linux.amoon@gmail.com/
V4:
 https://lore.kernel.org/all/20240625104039.48311-1-linux.amoon@gmail.com/
V3:
 https://lore.kernel.org/all/20240622061845.3678-1-linux.amoon@gmail.com/
V2:
 https://lore.kernel.org/all/20240621064426.282048-1-linux.amoon@gmail.com/
V1:
 https://lore.kernel.org/all/20240618164133.223194-2-linux.amoon@gmail.com/

Thanks
-Anand

Anand Moon (3):
  PCI: rockchip: Simplify clock handling by using clk_bulk*() function
  PCI: rockchip: Simplify reset control handling by using
    reset_control_bulk*() function
  PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function
    signature

 drivers/pci/controller/pcie-rockchip.c | 219 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  35 ++--
 2 files changed, 61 insertions(+), 193 deletions(-)


base-commit: 09f6b0c8904bfaa1e0601bc102e1b6aa6de8c98f
-- 
2.44.0

[PATCH v7 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function

[Anand Moon]

Refactor the clock handling in the Rockchip PCIe driver,
introducing a more robust and efficient method for enabling and
disabling clocks using clk_bulk*() API. Using the clk_bulk APIs,
the clock handling for the core clocks becomes much simpler.

- Replace devm_clk_get() with devm_clk_bulk_get_all().
- Replace clk_prepare_enable() with clk_bulk_prepare_enable().
- Replace clk_disable_unprepare() with clk_bulk_disable_unprepare().

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
v7: Update the functional change in commmit message.
v6: None.
v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the
       clock names in driver.
v4: use dev_err_probe for error patch.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot.
---
 drivers/pci/controller/pcie-rockchip.c | 65 +++-----------------------
 drivers/pci/controller/pcie-rockchip.h |  7 ++-
 2 files changed, 10 insertions(+), 62 deletions(-)

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index c07d7129f1c7..2777ef0cb599 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 					     "failed to get ep GPIO\n");
 	}
 
-	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
-	if (IS_ERR(rockchip->aclk_pcie)) {
-		dev_err(dev, "aclk clock not found\n");
-		return PTR_ERR(rockchip->aclk_pcie);
-	}
-
-	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
-	if (IS_ERR(rockchip->aclk_perf_pcie)) {
-		dev_err(dev, "aclk_perf clock not found\n");
-		return PTR_ERR(rockchip->aclk_perf_pcie);
-	}
-
-	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
-	if (IS_ERR(rockchip->hclk_pcie)) {
-		dev_err(dev, "hclk clock not found\n");
-		return PTR_ERR(rockchip->hclk_pcie);
-	}
-
-	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
-	if (IS_ERR(rockchip->clk_pcie_pm)) {
-		dev_err(dev, "pm clock not found\n");
-		return PTR_ERR(rockchip->clk_pcie_pm);
-	}
+	rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);
+	if (rockchip->num_clks < 0)
+		return dev_err_probe(dev, err, "failed to get clocks\n");
 
 	return 0;
 }
@@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
 	struct device *dev = rockchip->dev;
 	int err;
 
-	err = clk_prepare_enable(rockchip->aclk_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable aclk_pcie clock\n");
-		return err;
-	}
-
-	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
-		goto err_aclk_perf_pcie;
-	}
-
-	err = clk_prepare_enable(rockchip->hclk_pcie);
-	if (err) {
-		dev_err(dev, "unable to enable hclk_pcie clock\n");
-		goto err_hclk_pcie;
-	}
-
-	err = clk_prepare_enable(rockchip->clk_pcie_pm);
-	if (err) {
-		dev_err(dev, "unable to enable clk_pcie_pm clock\n");
-		goto err_clk_pcie_pm;
-	}
+	err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);
+	if (err)
+		return dev_err_probe(dev, err, "failed to enable clocks\n");
 
 	return 0;
-
-err_clk_pcie_pm:
-	clk_disable_unprepare(rockchip->hclk_pcie);
-err_hclk_pcie:
-	clk_disable_unprepare(rockchip->aclk_perf_pcie);
-err_aclk_perf_pcie:
-	clk_disable_unprepare(rockchip->aclk_pcie);
-	return err;
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
 
@@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data)
 {
 	struct rockchip_pcie *rockchip = data;
 
-	clk_disable_unprepare(rockchip->clk_pcie_pm);
-	clk_disable_unprepare(rockchip->hclk_pcie);
-	clk_disable_unprepare(rockchip->aclk_perf_pcie);
-	clk_disable_unprepare(rockchip->aclk_pcie);
+	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
 
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 6111de35f84c..bebab80c9553 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -11,6 +11,7 @@
 #ifndef _PCIE_ROCKCHIP_H
 #define _PCIE_ROCKCHIP_H
 
+#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/pci-ecam.h>
@@ -299,10 +300,8 @@ struct rockchip_pcie {
 	struct	reset_control *pm_rst;
 	struct	reset_control *aclk_rst;
 	struct	reset_control *pclk_rst;
-	struct	clk *aclk_pcie;
-	struct	clk *aclk_perf_pcie;
-	struct	clk *hclk_pcie;
-	struct	clk *clk_pcie_pm;
+	struct  clk_bulk_data *clks;
+	int	num_clks;
 	struct	regulator *vpcie12v; /* 12V power supply */
 	struct	regulator *vpcie3v3; /* 3.3V power supply */
 	struct	regulator *vpcie1v8; /* 1.8V power supply */
-- 
2.44.0

[PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Anand Moon]

Refactor the reset control handling in the Rockchip PCIe driver,
introducing a more robust and efficient method for assert and
deassert reset controller using reset_control_bulk*() API. Using the
reset_control_bulk APIs, the reset handling for the core clocks reset
unit becomes much simpler.

Spilt the reset controller in two groups as pre the RK3399 TRM.
After power up, the software driver should de-assert the reset of PCIe PHY,
then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the reset simultaneously
driver need to De-assert the reset pins simultionaly.

  PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.

- replace devm_reset_control_get_exclusive() with
	devm_reset_control_bulk_get_exclusive().
- replace reset_control_assert with
	reset_control_bulk_assert().
- replace reset_control_deassert with
	reset_control_bulk_deassert().

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
v7: replace devm_reset_control_bulk_get_optional_exclusive()
        with devm_reset_control_bulk_get_exclusive()
    update the functional changes.
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
    De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
    simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
    fixed checkpatch warning.
---
 drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
 drivers/pci/controller/pcie-rockchip.h |  26 +++--
 2 files changed, 49 insertions(+), 128 deletions(-)

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 2777ef0cb599..9a118e2b8cbd 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct device_node *node = dev->of_node;
 	struct resource *regs;
-	int err;
+	int err, i;
 
 	if (rockchip->is_rc) {
 		regs = platform_get_resource_byname(pdev,
@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
 		rockchip->link_gen = 2;
 
-	rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
-	if (IS_ERR(rockchip->core_rst)) {
-		if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing core reset property in node\n");
-		return PTR_ERR(rockchip->core_rst);
-	}
-
-	rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
-	if (IS_ERR(rockchip->mgmt_rst)) {
-		if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing mgmt reset property in node\n");
-		return PTR_ERR(rockchip->mgmt_rst);
-	}
-
-	rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
-								"mgmt-sticky");
-	if (IS_ERR(rockchip->mgmt_sticky_rst)) {
-		if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing mgmt-sticky reset property in node\n");
-		return PTR_ERR(rockchip->mgmt_sticky_rst);
-	}
-
-	rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
-	if (IS_ERR(rockchip->pipe_rst)) {
-		if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing pipe reset property in node\n");
-		return PTR_ERR(rockchip->pipe_rst);
-	}
+	for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++)
+		rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];
 
-	rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
-	if (IS_ERR(rockchip->pm_rst)) {
-		if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing pm reset property in node\n");
-		return PTR_ERR(rockchip->pm_rst);
-	}
+	err = devm_reset_control_bulk_get_exclusive(dev,
+						    ROCKCHIP_NUM_PM_RSTS,
+						    rockchip->pm_rsts);
+	if (err)
+		return dev_err_probe(dev, err, "cannot get the reset control\n");
 
-	rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
-	if (IS_ERR(rockchip->pclk_rst)) {
-		if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing pclk reset property in node\n");
-		return PTR_ERR(rockchip->pclk_rst);
-	}
+	for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++)
+		rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i];
 
-	rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
-	if (IS_ERR(rockchip->aclk_rst)) {
-		if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing aclk reset property in node\n");
-		return PTR_ERR(rockchip->aclk_rst);
-	}
+	err = devm_reset_control_bulk_get_exclusive(dev,
+						    ROCKCHIP_NUM_CORE_RSTS,
+						    rockchip->core_rsts);
+	if (err)
+		return dev_err_probe(dev, err, "cannot get the reset control\n");
 
 	if (rockchip->is_rc) {
 		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	int err, i;
 	u32 regs;
 
-	err = reset_control_assert(rockchip->aclk_rst);
-	if (err) {
-		dev_err(dev, "assert aclk_rst err %d\n", err);
-		return err;
-	}
-
-	err = reset_control_assert(rockchip->pclk_rst);
-	if (err) {
-		dev_err(dev, "assert pclk_rst err %d\n", err);
-		return err;
-	}
-
-	err = reset_control_assert(rockchip->pm_rst);
-	if (err) {
-		dev_err(dev, "assert pm_rst err %d\n", err);
-		return err;
-	}
+	err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
+					rockchip->pm_rsts);
+	if (err)
+		return dev_err_probe(dev, err, "reset bulk assert pm reset\n");
 
 	for (i = 0; i < MAX_LANE_NUM; i++) {
 		err = phy_init(rockchip->phys[i]);
@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 		}
 	}
 
-	err = reset_control_assert(rockchip->core_rst);
-	if (err) {
-		dev_err(dev, "assert core_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_assert(rockchip->mgmt_rst);
-	if (err) {
-		dev_err(dev, "assert mgmt_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_assert(rockchip->mgmt_sticky_rst);
-	if (err) {
-		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_assert(rockchip->pipe_rst);
-	if (err) {
-		dev_err(dev, "assert pipe_rst err %d\n", err);
-		goto err_exit_phy;
-	}
+	err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
+					rockchip->core_rsts);
+	if (err)
+		return dev_err_probe(dev, err, "reset bulk assert core reset\n");
 
 	udelay(10);
 
-	err = reset_control_deassert(rockchip->pm_rst);
-	if (err) {
-		dev_err(dev, "deassert pm_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_deassert(rockchip->aclk_rst);
+	err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,
+					  rockchip->pm_rsts);
 	if (err) {
-		dev_err(dev, "deassert aclk_rst err %d\n", err);
-		goto err_exit_phy;
-	}
-
-	err = reset_control_deassert(rockchip->pclk_rst);
-	if (err) {
-		dev_err(dev, "deassert pclk_rst err %d\n", err);
+		dev_err(dev, "reset bulk deassert pm err %d\n", err);
 		goto err_exit_phy;
 	}
 
@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	 * Please don't reorder the deassert sequence of the following
 	 * four reset pins.
 	 */
-	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
-	if (err) {
-		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
-		goto err_power_off_phy;
-	}
-
-	err = reset_control_deassert(rockchip->core_rst);
+	err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
+					  rockchip->core_rsts);
 	if (err) {
-		dev_err(dev, "deassert core_rst err %d\n", err);
-		goto err_power_off_phy;
-	}
-
-	err = reset_control_deassert(rockchip->mgmt_rst);
-	if (err) {
-		dev_err(dev, "deassert mgmt_rst err %d\n", err);
-		goto err_power_off_phy;
-	}
-
-	err = reset_control_deassert(rockchip->pipe_rst);
-	if (err) {
-		dev_err(dev, "deassert pipe_rst err %d\n", err);
+		dev_err(dev, "reset bulk deassert core err %d\n", err);
 		goto err_power_off_phy;
 	}
 
 	return 0;
+
 err_power_off_phy:
 	while (i--)
 		phy_power_off(rockchip->phys[i]);
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index bebab80c9553..2761699f670b 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/pci-ecam.h>
+#include <linux/reset.h>
 
 /*
  * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
@@ -288,18 +289,29 @@
 		(((c) << ((b) * 8 + 5)) & \
 		 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
 
+#define ROCKCHIP_NUM_PM_RSTS   ARRAY_SIZE(rockchip_pci_pm_rsts)
+#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts)
+
+static const char * const rockchip_pci_pm_rsts[] = {
+	"pm",
+	"pclk",
+	"aclk",
+};
+
+static const char * const rockchip_pci_core_rsts[] = {
+	"mgmt-sticky",
+	"mgmt",
+	"core",
+	"pipe",
+};
+
 struct rockchip_pcie {
 	void	__iomem *reg_base;		/* DT axi-base */
 	void	__iomem *apb_base;		/* DT apb-base */
 	bool    legacy_phy;
 	struct  phy *phys[MAX_LANE_NUM];
-	struct	reset_control *core_rst;
-	struct	reset_control *mgmt_rst;
-	struct	reset_control *mgmt_sticky_rst;
-	struct	reset_control *pipe_rst;
-	struct	reset_control *pm_rst;
-	struct	reset_control *aclk_rst;
-	struct	reset_control *pclk_rst;
+	struct  reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS];
+	struct  reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS];
 	struct  clk_bulk_data *clks;
 	int	num_clks;
 	struct	regulator *vpcie12v; /* 12V power supply */
-- 
2.44.0

[PATCH v7 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature

[Anand Moon]

Refactor the rockchip_pcie_disable_clocks function to accept a
struct rockchip_pcie pointer instead of a void pointer. This change
improves type safety and code readability by explicitly specifying
the expected data type.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
v7: None
v6: Fix the subject, add the missing () in the function name.
v5: Fix the commit message and add r-b Manivannan.
v4: None
v3: None
v2: No
---
 drivers/pci/controller/pcie-rockchip.c | 3 +--
 drivers/pci/controller/pcie-rockchip.h | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 9a118e2b8cbd..c3147111f1a7 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -269,9 +269,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
 
-void rockchip_pcie_disable_clocks(void *data)
+void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip)
 {
-	struct rockchip_pcie *rockchip = data;
 
 	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
 }
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 2761699f670b..7f0f938e9195 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -347,7 +347,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
-void rockchip_pcie_disable_clocks(void *data);
+void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip);
 void rockchip_pcie_cfg_configuration_accesses(
 		struct rockchip_pcie *rockchip, u32 type);
 
-- 
2.44.0

Re: [PATCH v7 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 10:36:03AM +0530, Anand Moon wrote:
> Refactor the clock handling in the Rockchip PCIe driver,
> introducing a more robust and efficient method for enabling and
> disabling clocks using clk_bulk*() API. Using the clk_bulk APIs,

I think I mentioned earlier to use impreative tone in commit messages.

> the clock handling for the core clocks becomes much simpler.
> 

Could you please elaborate how? i.e., devm_clk_bulk_get_all() allows the driver
to get all clocks defined in the DT thereby removing the hardcoded clock names
in the driver.

> - Replace devm_clk_get() with devm_clk_bulk_get_all().
> - Replace clk_prepare_enable() with clk_bulk_prepare_enable().
> - Replace clk_disable_unprepare() with clk_bulk_disable_unprepare().
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>

With above changes,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
> v7: Update the functional change in commmit message.
> v6: None.
> v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the
>        clock names in driver.
> v4: use dev_err_probe for error patch.
> v3: Fix typo in commit message, dropped reported by.
> v2: Fix compilation error reported by Intel test robot.
> ---
>  drivers/pci/controller/pcie-rockchip.c | 65 +++-----------------------
>  drivers/pci/controller/pcie-rockchip.h |  7 ++-
>  2 files changed, 10 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index c07d7129f1c7..2777ef0cb599 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>  					     "failed to get ep GPIO\n");
>  	}
>  
> -	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
> -	if (IS_ERR(rockchip->aclk_pcie)) {
> -		dev_err(dev, "aclk clock not found\n");
> -		return PTR_ERR(rockchip->aclk_pcie);
> -	}
> -
> -	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
> -	if (IS_ERR(rockchip->aclk_perf_pcie)) {
> -		dev_err(dev, "aclk_perf clock not found\n");
> -		return PTR_ERR(rockchip->aclk_perf_pcie);
> -	}
> -
> -	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
> -	if (IS_ERR(rockchip->hclk_pcie)) {
> -		dev_err(dev, "hclk clock not found\n");
> -		return PTR_ERR(rockchip->hclk_pcie);
> -	}
> -
> -	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
> -	if (IS_ERR(rockchip->clk_pcie_pm)) {
> -		dev_err(dev, "pm clock not found\n");
> -		return PTR_ERR(rockchip->clk_pcie_pm);
> -	}
> +	rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);
> +	if (rockchip->num_clks < 0)
> +		return dev_err_probe(dev, err, "failed to get clocks\n");
>  
>  	return 0;
>  }
> @@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
>  	struct device *dev = rockchip->dev;
>  	int err;
>  
> -	err = clk_prepare_enable(rockchip->aclk_pcie);
> -	if (err) {
> -		dev_err(dev, "unable to enable aclk_pcie clock\n");
> -		return err;
> -	}
> -
> -	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
> -	if (err) {
> -		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
> -		goto err_aclk_perf_pcie;
> -	}
> -
> -	err = clk_prepare_enable(rockchip->hclk_pcie);
> -	if (err) {
> -		dev_err(dev, "unable to enable hclk_pcie clock\n");
> -		goto err_hclk_pcie;
> -	}
> -
> -	err = clk_prepare_enable(rockchip->clk_pcie_pm);
> -	if (err) {
> -		dev_err(dev, "unable to enable clk_pcie_pm clock\n");
> -		goto err_clk_pcie_pm;
> -	}
> +	err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);
> +	if (err)
> +		return dev_err_probe(dev, err, "failed to enable clocks\n");
>  
>  	return 0;
> -
> -err_clk_pcie_pm:
> -	clk_disable_unprepare(rockchip->hclk_pcie);
> -err_hclk_pcie:
> -	clk_disable_unprepare(rockchip->aclk_perf_pcie);
> -err_aclk_perf_pcie:
> -	clk_disable_unprepare(rockchip->aclk_pcie);
> -	return err;
>  }
>  EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
>  
> @@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data)
>  {
>  	struct rockchip_pcie *rockchip = data;
>  
> -	clk_disable_unprepare(rockchip->clk_pcie_pm);
> -	clk_disable_unprepare(rockchip->hclk_pcie);
> -	clk_disable_unprepare(rockchip->aclk_perf_pcie);
> -	clk_disable_unprepare(rockchip->aclk_pcie);
> +	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
>  }
>  EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
>  
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index 6111de35f84c..bebab80c9553 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -11,6 +11,7 @@
>  #ifndef _PCIE_ROCKCHIP_H
>  #define _PCIE_ROCKCHIP_H
>  
> +#include <linux/clk.h>
>  #include <linux/kernel.h>
>  #include <linux/pci.h>
>  #include <linux/pci-ecam.h>
> @@ -299,10 +300,8 @@ struct rockchip_pcie {
>  	struct	reset_control *pm_rst;
>  	struct	reset_control *aclk_rst;
>  	struct	reset_control *pclk_rst;
> -	struct	clk *aclk_pcie;
> -	struct	clk *aclk_perf_pcie;
> -	struct	clk *hclk_pcie;
> -	struct	clk *clk_pcie_pm;
> +	struct  clk_bulk_data *clks;
> +	int	num_clks;
>  	struct	regulator *vpcie12v; /* 12V power supply */
>  	struct	regulator *vpcie3v3; /* 3.3V power supply */
>  	struct	regulator *vpcie1v8; /* 1.8V power supply */
> -- 
> 2.44.0
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> Refactor the reset control handling in the Rockchip PCIe driver,
> introducing a more robust and efficient method for assert and
> deassert reset controller using reset_control_bulk*() API. Using the
> reset_control_bulk APIs, the reset handling for the core clocks reset
> unit becomes much simpler.
> 

Same comments as previous patch.

> Spilt the reset controller in two groups as pre the RK3399 TRM.

*per

Also please state the TRM name and section for reference.

> After power up, the software driver should de-assert the reset of PCIe PHY,
> then wait the PLL locked by polling the status, if PLL
> has locked, then can de-assert the reset simultaneously
> driver need to De-assert the reset pins simultionaly.
> 
>   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> 
> - replace devm_reset_control_get_exclusive() with
> 	devm_reset_control_bulk_get_exclusive().
> - replace reset_control_assert with
> 	reset_control_bulk_assert().
> - replace reset_control_deassert with
> 	reset_control_bulk_deassert().
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> v7: replace devm_reset_control_bulk_get_optional_exclusive()
>         with devm_reset_control_bulk_get_exclusive()
>     update the functional changes.
> V6: Add reason for the split of the RESET pins.
> v5: Fix the De-assert reset core as per the TRM
>     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
>     simultaneously.
> v4: use dev_err_probe in error path.
> v3: Fix typo in commit message, dropped reported by.
> v2: Fix compilation error reported by Intel test robot
>     fixed checkpatch warning.
> ---
>  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
>  drivers/pci/controller/pcie-rockchip.h |  26 +++--
>  2 files changed, 49 insertions(+), 128 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index 2777ef0cb599..9a118e2b8cbd 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)

[...]

> +	err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
> +					rockchip->pm_rsts);
> +	if (err)
> +		return dev_err_probe(dev, err, "reset bulk assert pm reset\n");

'Couldn't assert PM resets'

>  
>  	for (i = 0; i < MAX_LANE_NUM; i++) {
>  		err = phy_init(rockchip->phys[i]);
> @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  		}
>  	}
>  
> -	err = reset_control_assert(rockchip->core_rst);
> -	if (err) {
> -		dev_err(dev, "assert core_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> -
> -	err = reset_control_assert(rockchip->mgmt_rst);
> -	if (err) {
> -		dev_err(dev, "assert mgmt_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> -
> -	err = reset_control_assert(rockchip->mgmt_sticky_rst);
> -	if (err) {
> -		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> -
> -	err = reset_control_assert(rockchip->pipe_rst);
> -	if (err) {
> -		dev_err(dev, "assert pipe_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> +	err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
> +					rockchip->core_rsts);
> +	if (err)
> +		return dev_err_probe(dev, err, "reset bulk assert core reset\n");

'Couldn't assert Core resets'

>  
>  	udelay(10);
>  
> -	err = reset_control_deassert(rockchip->pm_rst);
> -	if (err) {
> -		dev_err(dev, "deassert pm_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> -
> -	err = reset_control_deassert(rockchip->aclk_rst);
> +	err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,
> +					  rockchip->pm_rsts);
>  	if (err) {
> -		dev_err(dev, "deassert aclk_rst err %d\n", err);
> -		goto err_exit_phy;
> -	}
> -
> -	err = reset_control_deassert(rockchip->pclk_rst);
> -	if (err) {
> -		dev_err(dev, "deassert pclk_rst err %d\n", err);
> +		dev_err(dev, "reset bulk deassert pm err %d\n", err);

'Couldn't deassert PM resets'

>  		goto err_exit_phy;
>  	}
>  
> @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  	 * Please don't reorder the deassert sequence of the following
>  	 * four reset pins.

I don't think my earlier comment on this addressed. Why are you changing the
reset order? Why can't you have the resets in below (older) order?

static const char * const rockchip_pci_core_rsts[] = {
	mgmt-sticky",
	"core",
	"mgmt",
	"pipe",
};

Also, this comment should be removed now.

>  	 */
> -	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
> -	if (err) {
> -		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
> -		goto err_power_off_phy;
> -	}
> -
> -	err = reset_control_deassert(rockchip->core_rst);
> +	err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
> +					  rockchip->core_rsts);
>  	if (err) {
> -		dev_err(dev, "deassert core_rst err %d\n", err);
> -		goto err_power_off_phy;
> -	}
> -
> -	err = reset_control_deassert(rockchip->mgmt_rst);
> -	if (err) {
> -		dev_err(dev, "deassert mgmt_rst err %d\n", err);
> -		goto err_power_off_phy;
> -	}
> -
> -	err = reset_control_deassert(rockchip->pipe_rst);
> -	if (err) {
> -		dev_err(dev, "deassert pipe_rst err %d\n", err);
> +		dev_err(dev, "reset bulk deassert core err %d\n", err);

'Couldn't deassert Core resets'

- Mani

-- 
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Re: [PATCH v7 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 10:36:05AM +0530, Anand Moon wrote:
> Refactor the rockchip_pcie_disable_clocks function to accept a
> struct rockchip_pcie pointer instead of a void pointer. This change
> improves type safety and code readability by explicitly specifying
> the expected data type.
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> v7: None
> v6: Fix the subject, add the missing () in the function name.

Did you remove it in v7? Please don't do that, it just increases the burden on
reviewers.

- Mani

> v5: Fix the commit message and add r-b Manivannan.
> v4: None
> v3: None
> v2: No
> ---
>  drivers/pci/controller/pcie-rockchip.c | 3 +--
>  drivers/pci/controller/pcie-rockchip.h | 2 +-
>  2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index 9a118e2b8cbd..c3147111f1a7 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -269,9 +269,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
>  }
>  EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
>  
> -void rockchip_pcie_disable_clocks(void *data)
> +void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip)
>  {
> -	struct rockchip_pcie *rockchip = data;
>  
>  	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
>  }
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index 2761699f670b..7f0f938e9195 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -347,7 +347,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
>  int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
>  void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
>  int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
> -void rockchip_pcie_disable_clocks(void *data);
> +void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip);
>  void rockchip_pcie_cfg_configuration_accesses(
>  		struct rockchip_pcie *rockchip, u32 type);
>  
> -- 
> 2.44.0
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function

[Anand Moon]

Hi Manivannan,

Thanks for your review comments.

On Sat, 12 Oct 2024 at 11:38, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 10:36:03AM +0530, Anand Moon wrote:
> > Refactor the clock handling in the Rockchip PCIe driver,
> > introducing a more robust and efficient method for enabling and
> > disabling clocks using clk_bulk*() API. Using the clk_bulk APIs,
>
> I think I mentioned earlier to use impreative tone in commit messages.
>
I missed your point.
> > the clock handling for the core clocks becomes much simpler.
Will improve this. my focus is just I don't break the functionally.
> >
>
> Could you please elaborate how? i.e., devm_clk_bulk_get_all() allows the driver
> to get all clocks defined in the DT thereby removing the hardcoded clock names
> in the driver.
>
Ok,  I will elaborate on this in the next version.

> > - Replace devm_clk_get() with devm_clk_bulk_get_all().
> > - Replace clk_prepare_enable() with clk_bulk_prepare_enable().
> > - Replace clk_disable_unprepare() with clk_bulk_disable_unprepare().
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>
> With above changes,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> - Mani

I will try to improve the next version.

Thanks



-Anand

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Anand Moon]

Hi Manivannan,

Thanks for your review comments.

On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> > Refactor the reset control handling in the Rockchip PCIe driver,
> > introducing a more robust and efficient method for assert and
> > deassert reset controller using reset_control_bulk*() API. Using the
> > reset_control_bulk APIs, the reset handling for the core clocks reset
> > unit becomes much simpler.
> >
>
> Same comments as previous patch.
>
I will explain more about this.
> > Spilt the reset controller in two groups as pre the RK3399 TRM.
>
> *per
>
> Also please state the TRM name and section for reference.
>
Yes
> > After power up, the software driver should de-assert the reset of PCIe PHY,
> > then wait the PLL locked by polling the status, if PLL
> > has locked, then can de-assert the reset simultaneously
> > driver need to De-assert the reset pins simultionaly.
> >
> >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> >
> > - replace devm_reset_control_get_exclusive() with
> >       devm_reset_control_bulk_get_exclusive().
> > - replace reset_control_assert with
> >       reset_control_bulk_assert().
> > - replace reset_control_deassert with
> >       reset_control_bulk_deassert().
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > v7: replace devm_reset_control_bulk_get_optional_exclusive()
> >         with devm_reset_control_bulk_get_exclusive()
> >     update the functional changes.
> > V6: Add reason for the split of the RESET pins.
> > v5: Fix the De-assert reset core as per the TRM
> >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> >     simultaneously.
> > v4: use dev_err_probe in error path.
> > v3: Fix typo in commit message, dropped reported by.
> > v2: Fix compilation error reported by Intel test robot
> >     fixed checkpatch warning.
> > ---
> >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> >  2 files changed, 49 insertions(+), 128 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > index 2777ef0cb599..9a118e2b8cbd 100644
> > --- a/drivers/pci/controller/pcie-rockchip.c
> > +++ b/drivers/pci/controller/pcie-rockchip.c
> > @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>
> [...]
>
> > +     err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
> > +                                     rockchip->pm_rsts);
> > +     if (err)
> > +             return dev_err_probe(dev, err, "reset bulk assert pm reset\n");
>
> 'Couldn't assert PM resets'
>
> >
> >       for (i = 0; i < MAX_LANE_NUM; i++) {
> >               err = phy_init(rockchip->phys[i]);
> > @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> >               }
> >       }
> >
> > -     err = reset_control_assert(rockchip->core_rst);
> > -     if (err) {
> > -             dev_err(dev, "assert core_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > -
> > -     err = reset_control_assert(rockchip->mgmt_rst);
> > -     if (err) {
> > -             dev_err(dev, "assert mgmt_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > -
> > -     err = reset_control_assert(rockchip->mgmt_sticky_rst);
> > -     if (err) {
> > -             dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > -
> > -     err = reset_control_assert(rockchip->pipe_rst);
> > -     if (err) {
> > -             dev_err(dev, "assert pipe_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > +     err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
> > +                                     rockchip->core_rsts);
> > +     if (err)
> > +             return dev_err_probe(dev, err, "reset bulk assert core reset\n");
>
> 'Couldn't assert Core resets'
>
> >
> >       udelay(10);
> >
> > -     err = reset_control_deassert(rockchip->pm_rst);
> > -     if (err) {
> > -             dev_err(dev, "deassert pm_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > -
> > -     err = reset_control_deassert(rockchip->aclk_rst);
> > +     err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,
> > +                                       rockchip->pm_rsts);
> >       if (err) {
> > -             dev_err(dev, "deassert aclk_rst err %d\n", err);
> > -             goto err_exit_phy;
> > -     }
> > -
> > -     err = reset_control_deassert(rockchip->pclk_rst);
> > -     if (err) {
> > -             dev_err(dev, "deassert pclk_rst err %d\n", err);
> > +             dev_err(dev, "reset bulk deassert pm err %d\n", err);
>
> 'Couldn't deassert PM resets'
>
> >               goto err_exit_phy;
> >       }
> >
> > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> >        * Please don't reorder the deassert sequence of the following
> >        * four reset pins.
>
> I don't think my earlier comment on this addressed. Why are you changing the
> reset order? Why can't you have the resets in below (older) order?
>
> static const char * const rockchip_pci_core_rsts[] = {
>         mgmt-sticky",
>         "core",
>         "mgmt",
>         "pipe",
> };
 I will add a comment on this above.
>
> Also, this comment should be removed now.
>
> >        */
> > -     err = reset_control_deassert(rockchip->mgmt_sticky_rst);
> > -     if (err) {
> > -             dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
> > -             goto err_power_off_phy;
> > -     }
> > -
> > -     err = reset_control_deassert(rockchip->core_rst);
> > +     err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
> > +                                       rockchip->core_rsts);
> >       if (err) {
> > -             dev_err(dev, "deassert core_rst err %d\n", err);
> > -             goto err_power_off_phy;
> > -     }
> > -
> > -     err = reset_control_deassert(rockchip->mgmt_rst);
> > -     if (err) {
> > -             dev_err(dev, "deassert mgmt_rst err %d\n", err);
> > -             goto err_power_off_phy;
> > -     }
> > -
> > -     err = reset_control_deassert(rockchip->pipe_rst);
> > -     if (err) {
> > -             dev_err(dev, "deassert pipe_rst err %d\n", err);
> > +             dev_err(dev, "reset bulk deassert core err %d\n", err);
>
> 'Couldn't deassert Core resets'
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

Ok,I will try to improve this in the next version.

Thanks

-Anand

Re: [PATCH v7 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature

[Anand Moon]

Hi Manivannan,

Thanks for your review comments.

On Sat, 12 Oct 2024 at 11:50, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 10:36:05AM +0530, Anand Moon wrote:
> > Refactor the rockchip_pcie_disable_clocks function to accept a
> > struct rockchip_pcie pointer instead of a void pointer. This change
> > improves type safety and code readability by explicitly specifying
> > the expected data type.
> >
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > v7: None
> > v6: Fix the subject, add the missing () in the function name.
>
> Did you remove it in v7? Please don't do that, it just increases the burden on
> reviewers.
>
> - Mani
Earlier, it was reported that function () should be used in the function name.

Thanks

-Anand

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote:
> Hi Manivannan,
> 
> Thanks for your review comments.
> 
> On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> > > Refactor the reset control handling in the Rockchip PCIe driver,
> > > introducing a more robust and efficient method for assert and
> > > deassert reset controller using reset_control_bulk*() API. Using the
> > > reset_control_bulk APIs, the reset handling for the core clocks reset
> > > unit becomes much simpler.
> > >
> >
> > Same comments as previous patch.
> >
> I will explain more about this.
> > > Spilt the reset controller in two groups as pre the RK3399 TRM.
> >
> > *per
> >
> > Also please state the TRM name and section for reference.
> >
> Yes
> > > After power up, the software driver should de-assert the reset of PCIe PHY,
> > > then wait the PLL locked by polling the status, if PLL
> > > has locked, then can de-assert the reset simultaneously
> > > driver need to De-assert the reset pins simultionaly.
> > >
> > >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> > >
> > > - replace devm_reset_control_get_exclusive() with
> > >       devm_reset_control_bulk_get_exclusive().
> > > - replace reset_control_assert with
> > >       reset_control_bulk_assert().
> > > - replace reset_control_deassert with
> > >       reset_control_bulk_deassert().
> > >
> > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > ---
> > > v7: replace devm_reset_control_bulk_get_optional_exclusive()
> > >         with devm_reset_control_bulk_get_exclusive()
> > >     update the functional changes.
> > > V6: Add reason for the split of the RESET pins.
> > > v5: Fix the De-assert reset core as per the TRM
> > >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> > >     simultaneously.
> > > v4: use dev_err_probe in error path.
> > > v3: Fix typo in commit message, dropped reported by.
> > > v2: Fix compilation error reported by Intel test robot
> > >     fixed checkpatch warning.
> > > ---
> > >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> > >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> > >  2 files changed, 49 insertions(+), 128 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > > index 2777ef0cb599..9a118e2b8cbd 100644
> > > --- a/drivers/pci/controller/pcie-rockchip.c
> > > +++ b/drivers/pci/controller/pcie-rockchip.c

[...]

> > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> > >        * Please don't reorder the deassert sequence of the following
> > >        * four reset pins.
> >
> > I don't think my earlier comment on this addressed. Why are you changing the
> > reset order? Why can't you have the resets in below (older) order?
> >
> > static const char * const rockchip_pci_core_rsts[] = {
> >         mgmt-sticky",
> >         "core",
> >         "mgmt",
> >         "pipe",
> > };
>  I will add a comment on this above.

Sorry, I don't get your response. My suggestion was to keep the resets sorted as
the original order (also indicated by my above snippet).

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 12:55:38PM +0530, Anand Moon wrote:
> Hi Manivannan,
> 
> Thanks for your review comments.
> 
> On Sat, 12 Oct 2024 at 11:50, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Sat, Oct 12, 2024 at 10:36:05AM +0530, Anand Moon wrote:
> > > Refactor the rockchip_pcie_disable_clocks function to accept a
> > > struct rockchip_pcie pointer instead of a void pointer. This change
> > > improves type safety and code readability by explicitly specifying
> > > the expected data type.
> > >
> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > ---
> > > v7: None
> > > v6: Fix the subject, add the missing () in the function name.
> >
> > Did you remove it in v7? Please don't do that, it just increases the burden on
> > reviewers.
> >
> > - Mani
> Earlier, it was reported that function () should be used in the function name.

Hmm. Why can't you do the same for the description also?

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Anand Moon]

Hi Manivannan,

On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote:
> > Hi Manivannan,
> >
> > Thanks for your review comments.
> >
> > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam
> > <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> > > > Refactor the reset control handling in the Rockchip PCIe driver,
> > > > introducing a more robust and efficient method for assert and
> > > > deassert reset controller using reset_control_bulk*() API. Using the
> > > > reset_control_bulk APIs, the reset handling for the core clocks reset
> > > > unit becomes much simpler.
> > > >
> > >
> > > Same comments as previous patch.
> > >
> > I will explain more about this.
> > > > Spilt the reset controller in two groups as pre the RK3399 TRM.
> > >
> > > *per
> > >
> > > Also please state the TRM name and section for reference.
> > >
> > Yes
> > > > After power up, the software driver should de-assert the reset of PCIe PHY,
> > > > then wait the PLL locked by polling the status, if PLL
> > > > has locked, then can de-assert the reset simultaneously
> > > > driver need to De-assert the reset pins simultionaly.
> > > >
> > > >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> > > >
> > > > - replace devm_reset_control_get_exclusive() with
> > > >       devm_reset_control_bulk_get_exclusive().
> > > > - replace reset_control_assert with
> > > >       reset_control_bulk_assert().
> > > > - replace reset_control_deassert with
> > > >       reset_control_bulk_deassert().
> > > >
> > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > ---
> > > > v7: replace devm_reset_control_bulk_get_optional_exclusive()
> > > >         with devm_reset_control_bulk_get_exclusive()
> > > >     update the functional changes.
> > > > V6: Add reason for the split of the RESET pins.
> > > > v5: Fix the De-assert reset core as per the TRM
> > > >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> > > >     simultaneously.
> > > > v4: use dev_err_probe in error path.
> > > > v3: Fix typo in commit message, dropped reported by.
> > > > v2: Fix compilation error reported by Intel test robot
> > > >     fixed checkpatch warning.
> > > > ---
> > > >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> > > >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> > > >  2 files changed, 49 insertions(+), 128 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > > > index 2777ef0cb599..9a118e2b8cbd 100644
> > > > --- a/drivers/pci/controller/pcie-rockchip.c
> > > > +++ b/drivers/pci/controller/pcie-rockchip.c
>
> [...]
>
> > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> > > >        * Please don't reorder the deassert sequence of the following
> > > >        * four reset pins.
> > >
> > > I don't think my earlier comment on this addressed. Why are you changing the
> > > reset order? Why can't you have the resets in below (older) order?
> > >
> > > static const char * const rockchip_pci_core_rsts[] = {
> > >         mgmt-sticky",
> > >         "core",
> > >         "mgmt",
> > >         "pipe",
> > > };
> >  I will add a comment on this above.

I get your point, I missed your point.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275

Actually I had these changes, but it got missed out in rebase.

>
> Sorry, I don't get your response. My suggestion was to keep the resets sorted as
> the original order (also indicated by my above snippet).

I will go through all the suggestions and modify them accordingly.

As per the RK3399 TRM
[2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf

17.5.2.2 Reset Application
17.5.2.2.2 System Reset (describe all the core reset feature)
(name as per the dts mapping)
RESET_N: - core
MGMT_RESET_N:- mgmt
MGMT_STICKY_RESET_N:- mgmt-sticky
PIPE_RESET_N: - pipe
AXI_RESET_N - aclk
APB_RESET_N: pclk
PM_RESET_N: - pm
PCIE_PHY_RESET_N: - phy reset (used in the phy driver).

This is the reason for the split of the clk and core reset.

Further down in
17.5.8 PCIe Operation
17.5.8.1 PCIe Initialization Sequence
17.5.8.1.1 PCIe as Root Complex

6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
simultaneously

Should I follow this order ? or the above order.
static const char * const rockchip_pci_core_rsts[] = {
        "pipe",
        "mgmt-sticky",
         "mgmt",
         "core",
};

>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

Thanks
-Anand

Re: [PATCH v7 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature

[Anand Moon]

Hi Manivannan,

On Sat, 12 Oct 2024 at 13:32, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 12:55:38PM +0530, Anand Moon wrote:
> > Hi Manivannan,
> >
> > Thanks for your review comments.
> >
> > On Sat, 12 Oct 2024 at 11:50, Manivannan Sadhasivam
> > <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > On Sat, Oct 12, 2024 at 10:36:05AM +0530, Anand Moon wrote:
> > > > Refactor the rockchip_pcie_disable_clocks function to accept a
> > > > struct rockchip_pcie pointer instead of a void pointer. This change
> > > > improves type safety and code readability by explicitly specifying
> > > > the expected data type.
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > ---
> > > > v7: None
> > > > v6: Fix the subject, add the missing () in the function name.
> > >
> > > Did you remove it in v7? Please don't do that, it just increases the burden on
> > > reviewers.
> > >
> > > - Mani
> > Earlier, it was reported that function () should be used in the function name.
>
> Hmm. Why can't you do the same for the description also?
>
Ok, I missed this point.
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

Thanks

-Anand

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Manivannan Sadhasivam]

On Sat, Oct 12, 2024 at 03:34:25PM +0530, Anand Moon wrote:
> Hi Manivannan,
> 
> On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote:
> > > Hi Manivannan,
> > >
> > > Thanks for your review comments.
> > >
> > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam
> > > <manivannan.sadhasivam@linaro.org> wrote:
> > > >
> > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> > > > > Refactor the reset control handling in the Rockchip PCIe driver,
> > > > > introducing a more robust and efficient method for assert and
> > > > > deassert reset controller using reset_control_bulk*() API. Using the
> > > > > reset_control_bulk APIs, the reset handling for the core clocks reset
> > > > > unit becomes much simpler.
> > > > >
> > > >
> > > > Same comments as previous patch.
> > > >
> > > I will explain more about this.
> > > > > Spilt the reset controller in two groups as pre the RK3399 TRM.
> > > >
> > > > *per
> > > >
> > > > Also please state the TRM name and section for reference.
> > > >
> > > Yes
> > > > > After power up, the software driver should de-assert the reset of PCIe PHY,
> > > > > then wait the PLL locked by polling the status, if PLL
> > > > > has locked, then can de-assert the reset simultaneously
> > > > > driver need to De-assert the reset pins simultionaly.
> > > > >
> > > > >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> > > > >
> > > > > - replace devm_reset_control_get_exclusive() with
> > > > >       devm_reset_control_bulk_get_exclusive().
> > > > > - replace reset_control_assert with
> > > > >       reset_control_bulk_assert().
> > > > > - replace reset_control_deassert with
> > > > >       reset_control_bulk_deassert().
> > > > >
> > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > > ---
> > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive()
> > > > >         with devm_reset_control_bulk_get_exclusive()
> > > > >     update the functional changes.
> > > > > V6: Add reason for the split of the RESET pins.
> > > > > v5: Fix the De-assert reset core as per the TRM
> > > > >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> > > > >     simultaneously.
> > > > > v4: use dev_err_probe in error path.
> > > > > v3: Fix typo in commit message, dropped reported by.
> > > > > v2: Fix compilation error reported by Intel test robot
> > > > >     fixed checkpatch warning.
> > > > > ---
> > > > >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> > > > >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> > > > >  2 files changed, 49 insertions(+), 128 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > > > > index 2777ef0cb599..9a118e2b8cbd 100644
> > > > > --- a/drivers/pci/controller/pcie-rockchip.c
> > > > > +++ b/drivers/pci/controller/pcie-rockchip.c
> >
> > [...]
> >
> > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> > > > >        * Please don't reorder the deassert sequence of the following
> > > > >        * four reset pins.
> > > >
> > > > I don't think my earlier comment on this addressed. Why are you changing the
> > > > reset order? Why can't you have the resets in below (older) order?
> > > >
> > > > static const char * const rockchip_pci_core_rsts[] = {
> > > >         mgmt-sticky",
> > > >         "core",
> > > >         "mgmt",
> > > >         "pipe",
> > > > };
> > >  I will add a comment on this above.
> 
> I get your point, I missed your point.
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275
> 
> Actually I had these changes, but it got missed out in rebase.
> 
> >
> > Sorry, I don't get your response. My suggestion was to keep the resets sorted as
> > the original order (also indicated by my above snippet).
> 
> I will go through all the suggestions and modify them accordingly.
> 
> As per the RK3399 TRM
> [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
> 
> 17.5.2.2 Reset Application
> 17.5.2.2.2 System Reset (describe all the core reset feature)
> (name as per the dts mapping)
> RESET_N: - core
> MGMT_RESET_N:- mgmt
> MGMT_STICKY_RESET_N:- mgmt-sticky
> PIPE_RESET_N: - pipe
> AXI_RESET_N - aclk
> APB_RESET_N: pclk
> PM_RESET_N: - pm
> PCIE_PHY_RESET_N: - phy reset (used in the phy driver).
> 
> This is the reason for the split of the clk and core reset.
> 
> Further down in
> 17.5.8 PCIe Operation
> 17.5.8.1 PCIe Initialization Sequence
> 17.5.8.1.1 PCIe as Root Complex
> 
> 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> simultaneously
> 
> Should I follow this order ? or the above order.
> static const char * const rockchip_pci_core_rsts[] = {
>         "pipe",
>         "mgmt-sticky",
>          "mgmt",
>          "core",
> };

Ok, thanks for clarifying. I was worried about the comment in the driver that
warns against changing the order. But TRM rececommends a different order :/

But since no one ever reported any issue, let's go with the existing order. If
you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who
knows the hardware better.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function

[Anand Moon]

Hi Manivannan,

On Sat, 12 Oct 2024 at 17:35, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Sat, Oct 12, 2024 at 03:34:25PM +0530, Anand Moon wrote:
> > Hi Manivannan,
> >
> > On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam
> > <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote:
> > > > Hi Manivannan,
> > > >
> > > > Thanks for your review comments.
> > > >
> > > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam
> > > > <manivannan.sadhasivam@linaro.org> wrote:
> > > > >
> > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote:
> > > > > > Refactor the reset control handling in the Rockchip PCIe driver,
> > > > > > introducing a more robust and efficient method for assert and
> > > > > > deassert reset controller using reset_control_bulk*() API. Using the
> > > > > > reset_control_bulk APIs, the reset handling for the core clocks reset
> > > > > > unit becomes much simpler.
> > > > > >
> > > > >
> > > > > Same comments as previous patch.
> > > > >
> > > > I will explain more about this.
> > > > > > Spilt the reset controller in two groups as pre the RK3399 TRM.
> > > > >
> > > > > *per
> > > > >
> > > > > Also please state the TRM name and section for reference.
> > > > >
> > > > Yes
> > > > > > After power up, the software driver should de-assert the reset of PCIe PHY,
> > > > > > then wait the PLL locked by polling the status, if PLL
> > > > > > has locked, then can de-assert the reset simultaneously
> > > > > > driver need to De-assert the reset pins simultionaly.
> > > > > >
> > > > > >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> > > > > >
> > > > > > - replace devm_reset_control_get_exclusive() with
> > > > > >       devm_reset_control_bulk_get_exclusive().
> > > > > > - replace reset_control_assert with
> > > > > >       reset_control_bulk_assert().
> > > > > > - replace reset_control_deassert with
> > > > > >       reset_control_bulk_deassert().
> > > > > >
> > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > > > ---
> > > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive()
> > > > > >         with devm_reset_control_bulk_get_exclusive()
> > > > > >     update the functional changes.
> > > > > > V6: Add reason for the split of the RESET pins.
> > > > > > v5: Fix the De-assert reset core as per the TRM
> > > > > >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> > > > > >     simultaneously.
> > > > > > v4: use dev_err_probe in error path.
> > > > > > v3: Fix typo in commit message, dropped reported by.
> > > > > > v2: Fix compilation error reported by Intel test robot
> > > > > >     fixed checkpatch warning.
> > > > > > ---
> > > > > >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> > > > > >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> > > > > >  2 files changed, 49 insertions(+), 128 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > > > > > index 2777ef0cb599..9a118e2b8cbd 100644
> > > > > > --- a/drivers/pci/controller/pcie-rockchip.c
> > > > > > +++ b/drivers/pci/controller/pcie-rockchip.c
> > >
> > > [...]
> > >
> > > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> > > > > >        * Please don't reorder the deassert sequence of the following
> > > > > >        * four reset pins.
> > > > >
> > > > > I don't think my earlier comment on this addressed. Why are you changing the
> > > > > reset order? Why can't you have the resets in below (older) order?
> > > > >
> > > > > static const char * const rockchip_pci_core_rsts[] = {
> > > > >         mgmt-sticky",
> > > > >         "core",
> > > > >         "mgmt",
> > > > >         "pipe",
> > > > > };
> > > >  I will add a comment on this above.
> >
> > I get your point, I missed your point.
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275
> >
> > Actually I had these changes, but it got missed out in rebase.
> >
> > >
> > > Sorry, I don't get your response. My suggestion was to keep the resets sorted as
> > > the original order (also indicated by my above snippet).
> >
> > I will go through all the suggestions and modify them accordingly.
> >
> > As per the RK3399 TRM
> > [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
> >
> > 17.5.2.2 Reset Application
> > 17.5.2.2.2 System Reset (describe all the core reset feature)
> > (name as per the dts mapping)
> > RESET_N: - core
> > MGMT_RESET_N:- mgmt
> > MGMT_STICKY_RESET_N:- mgmt-sticky
> > PIPE_RESET_N: - pipe
> > AXI_RESET_N - aclk
> > APB_RESET_N: pclk
> > PM_RESET_N: - pm
> > PCIE_PHY_RESET_N: - phy reset (used in the phy driver).
> >
> > This is the reason for the split of the clk and core reset.
> >
> > Further down in
> > 17.5.8 PCIe Operation
> > 17.5.8.1 PCIe Initialization Sequence
> > 17.5.8.1.1 PCIe as Root Complex
> >
> > 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> > simultaneously
> >
> > Should I follow this order ? or the above order.
> > static const char * const rockchip_pci_core_rsts[] = {
> >         "pipe",
> >         "mgmt-sticky",
> >          "mgmt",
> >          "core",
> > };
>
> Ok, thanks for clarifying. I was worried about the comment in the driver that
> warns against changing the order. But TRM rececommends a different order :/
>
> But since no one ever reported any issue, let's go with the existing order. If
> you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who
> knows the hardware better.
>
I will follow the existing code version,
I was confused with the name and description earlier.
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

Thanks
-Anand