From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEB59CF2564 for ; Sat, 12 Oct 2024 12:07:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=d31fMEIkZBWfHDg7MkYDOFVjb8TdCN2jGRRDuyk+HcY=; b=gVnZp+pb6VS/Uts0u/L/ft1LWy zd2CWD+1SFzYaPmii89PfzPtpfTmQYt41auzYdV0G3d6XN7IDKRBLUczEFpYF115h7ol88CM5zwjr haYYxFNkj/gsxP8lP3FyYjks9XY6sZXe1+ZcLQQKr/yZOdcy9rYswvaA7dt/n+QZHXyVbobuCsMwe WU/j08Bf25Gva1qIG5JddqtRvgXMAzFPdYhn+xvkmOLCIobwmGdGewzSuZ5zHGv4c94NnKopS2uM6 faYjRMWotxDw2nHcXBWxhj1XNrc9V9EW2kRTg8CURXMWZ/LZkRARKdglDIRSzm5KIkSxB/0HQ6EZw 0bmACE4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1szato-00000001AcP-2OD8; Sat, 12 Oct 2024 12:07:08 +0000 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1szasQ-00000001AT5-24XR for linux-arm-kernel@lists.infradead.org; Sat, 12 Oct 2024 12:05:43 +0000 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-71e3d45bbb5so941475b3a.0 for ; Sat, 12 Oct 2024 05:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728734741; x=1729339541; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=d31fMEIkZBWfHDg7MkYDOFVjb8TdCN2jGRRDuyk+HcY=; b=htcRo2AmjXIkhJa6y1MUJtIhLylst1jzdMPwcLR5XwM2ixZsqvXmga9Piiwl39ATiw Bt6IPM7Kw93fjeCQJoJlNJF2khAiyfi/7k3ZqJwlVi3jG3QreSv3Jt7R1yQ9Kp+DHHoy 5oqkComll32CaKyeWXNwsMI2O7TPA96BMB41r8eyWpW+IMu8JtiH1PGVRvrQtR0f8RCy NNZqW0JhHh8IXyb9Vp2QHieC8U1vgzc+8mXZ/MgAKMGagKzqrf7OyTAxBGGZS2gS1KU5 ZuDzhJJUVc3DAV0OabGF93IMg5TShf6z5kkKfHI3l2qijsNQmsjbG4H2g3+vDZSMgPVp DmEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728734741; x=1729339541; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=d31fMEIkZBWfHDg7MkYDOFVjb8TdCN2jGRRDuyk+HcY=; b=nhbRurEgunx8LV+Bl3YonLcxoof+fr60t5VvQyIMFsL3LK7y1glTJYANr2GTUBNKTC 2yeqAlQ9cgWVyOugeojSYLFMOEkUqHlLJiu0rDFoB500WyVPJthakkP5XeVMkNwEZxd6 h/3vTPnE4C07z5rbQ6C+HNHAuUr/jjDcTXNXkb4Iies1ix6R3AB81S2p8iBJ/HQ433p6 +A9PaIv0RfeTVpa/99x29W0uBecX2KMST6R9eZqwV8TN07EI7L1NrO89Klu5dWorRj1E YT0AYs+JZUZ/kac3ftZ+vp9cDOAYjcQpEfSRL4xbm2UaYWU0M/LhqV77ywsUWsTClCCS QDjw== X-Forwarded-Encrypted: i=1; AJvYcCX/UPPS0K7VIDDmGxZskxYR+CVin8SShIl/Lvgx7WmmInkjp2k1BJvZHzuExI/+J9Qr1ZeMVM7tn8rXoBDgysSD@lists.infradead.org X-Gm-Message-State: AOJu0YwOdg3lOe2Vzv0lE66XlXHUPKhDtS56AWS19SMJx2yRXyvAzgjf 5KEIiLYrsvzRm9ActAGfRMxKQyERD8dacga93PWyvTzenq4HJ47t9wauHzWZ1Q== X-Google-Smtp-Source: AGHT+IFSsBMQH+PyGhmqzrLQ62VMYY9J5q1rZuOjYArGKZZ0lBK45Y5rDnqcj6s9R/T0RqZCAWlqBw== X-Received: by 2002:a05:6a00:811:b0:71e:209:513c with SMTP id d2e1a72fcca58-71e380a36c9mr10010363b3a.17.1728734741456; Sat, 12 Oct 2024 05:05:41 -0700 (PDT) Received: from thinkpad ([220.158.156.122]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2aaba17dsm4006379b3a.155.2024.10.12.05.05.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Oct 2024 05:05:41 -0700 (PDT) Date: Sat, 12 Oct 2024 17:35:36 +0530 From: Manivannan Sadhasivam To: Anand Moon Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , "open list:PCIE DRIVER FOR ROCKCHIP" , "open list:PCIE DRIVER FOR ROCKCHIP" , "moderated list:ARM/Rockchip SoC support" , open list Subject: Re: [PATCH v7 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Message-ID: <20241012120536.l7tp32ofvf6okijy@thinkpad> References: <20241012050611.1908-1-linux.amoon@gmail.com> <20241012050611.1908-3-linux.amoon@gmail.com> <20241012061834.ksbtcaw3c7iacnye@thinkpad> <20241012080019.cdgq63rwj6oi4bg7@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241012_050542_567482_400E7893 X-CRM114-Status: GOOD ( 36.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Oct 12, 2024 at 03:34:25PM +0530, Anand Moon wrote: > Hi Manivannan, > > On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam > wrote: > > > > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote: > > > Hi Manivannan, > > > > > > Thanks for your review comments. > > > > > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam > > > wrote: > > > > > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > > > > Refactor the reset control handling in the Rockchip PCIe driver, > > > > > introducing a more robust and efficient method for assert and > > > > > deassert reset controller using reset_control_bulk*() API. Using the > > > > > reset_control_bulk APIs, the reset handling for the core clocks reset > > > > > unit becomes much simpler. > > > > > > > > > > > > > Same comments as previous patch. > > > > > > > I will explain more about this. > > > > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > > > > > > > *per > > > > > > > > Also please state the TRM name and section for reference. > > > > > > > Yes > > > > > After power up, the software driver should de-assert the reset of PCIe PHY, > > > > > then wait the PLL locked by polling the status, if PLL > > > > > has locked, then can de-assert the reset simultaneously > > > > > driver need to De-assert the reset pins simultionaly. > > > > > > > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > > > > > > > - replace devm_reset_control_get_exclusive() with > > > > > devm_reset_control_bulk_get_exclusive(). > > > > > - replace reset_control_assert with > > > > > reset_control_bulk_assert(). > > > > > - replace reset_control_deassert with > > > > > reset_control_bulk_deassert(). > > > > > > > > > > Signed-off-by: Anand Moon > > > > > --- > > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > > > > with devm_reset_control_bulk_get_exclusive() > > > > > update the functional changes. > > > > > V6: Add reason for the split of the RESET pins. > > > > > v5: Fix the De-assert reset core as per the TRM > > > > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > > > > simultaneously. > > > > > v4: use dev_err_probe in error path. > > > > > v3: Fix typo in commit message, dropped reported by. > > > > > v2: Fix compilation error reported by Intel test robot > > > > > fixed checkpatch warning. > > > > > --- > > > > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > > > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > > > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > > > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > > > > index 2777ef0cb599..9a118e2b8cbd 100644 > > > > > --- a/drivers/pci/controller/pcie-rockchip.c > > > > > +++ b/drivers/pci/controller/pcie-rockchip.c > > > > [...] > > > > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > > > > * Please don't reorder the deassert sequence of the following > > > > > * four reset pins. > > > > > > > > I don't think my earlier comment on this addressed. Why are you changing the > > > > reset order? Why can't you have the resets in below (older) order? > > > > > > > > static const char * const rockchip_pci_core_rsts[] = { > > > > mgmt-sticky", > > > > "core", > > > > "mgmt", > > > > "pipe", > > > > }; > > > I will add a comment on this above. > > I get your point, I missed your point. > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275 > > Actually I had these changes, but it got missed out in rebase. > > > > > Sorry, I don't get your response. My suggestion was to keep the resets sorted as > > the original order (also indicated by my above snippet). > > I will go through all the suggestions and modify them accordingly. > > As per the RK3399 TRM > [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf > > 17.5.2.2 Reset Application > 17.5.2.2.2 System Reset (describe all the core reset feature) > (name as per the dts mapping) > RESET_N: - core > MGMT_RESET_N:- mgmt > MGMT_STICKY_RESET_N:- mgmt-sticky > PIPE_RESET_N: - pipe > AXI_RESET_N - aclk > APB_RESET_N: pclk > PM_RESET_N: - pm > PCIE_PHY_RESET_N: - phy reset (used in the phy driver). > > This is the reason for the split of the clk and core reset. > > Further down in > 17.5.8 PCIe Operation > 17.5.8.1 PCIe Initialization Sequence > 17.5.8.1.1 PCIe as Root Complex > > 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > simultaneously > > Should I follow this order ? or the above order. > static const char * const rockchip_pci_core_rsts[] = { > "pipe", > "mgmt-sticky", > "mgmt", > "core", > }; Ok, thanks for clarifying. I was worried about the comment in the driver that warns against changing the order. But TRM rececommends a different order :/ But since no one ever reported any issue, let's go with the existing order. If you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who knows the hardware better. - Mani -- மணிவண்ணன் சதாசிவம்