From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65A80D17129 for ; Mon, 21 Oct 2024 19:05:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1EVE840fPkz9MNxpBQgWZMM694YQmMf0npLzK+4eDqQ=; b=jC8AXkpNXNv6V+tOjaDq5/OzVQ +TBS/+eqcm/DxOSyixzSh4Oh3TTFafSydR/ZJvDBsvDIvAh2ltVmzg9TghgZJ9J7xgo0Fk4BLGNu8 CI16FM1UATm7lAcosO3ITX9SPfnvuYs2zJKHBqno7S1FLDJW01E4x0VciZ/aW0HDOkG5LZndbyhU6 uh4+3o7EKHckZ4vJ9KU57VOamt90akjw3JXI315Z0M418RNp9Rlm9oZlRVVgM4Fs3q1jJgNkTbShv CskOedVGG06a1BaNFiI+SepK+pzFKHSxERlUf9sdNs2mWCWf0YtPlAmZ/MIV+IX36Onv1Fvb/uM4s nT0InMnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t2xik-00000008OQM-0iBK; Mon, 21 Oct 2024 19:05:38 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t2xgm-00000008O4C-2wUO; Mon, 21 Oct 2024 19:03:38 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 77D875C59A2; Mon, 21 Oct 2024 19:03:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 794AEC4CEC3; Mon, 21 Oct 2024 19:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729537415; bh=rBGnIU2ChSzNbvZ5Xe+O+3llHRdoMbcsKIPRGW3IyNw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=BAC5eGI2h/vU8QtDowYR5TEPWsNlzjzTbJNgFcJV+n7COFotJ1Q7xfI84gbctw3b9 xlqtgRvkP7flzhq9MEQkb0t4Xg556IzWC/tm1+4LRsZaB3rmqHET8h76REqdPUnAqT zJ7Zkwc72vXITR1iaOR5mlPEL9iT4HNXWjRxRVKO1DrkXdFjosjO8NCH80EERSeXsb G6A8xN/lidTdzW1c1Ne0v8G73APArjVXQ+zP+CoCr/ZOivQbyscczPstZww+ZtW+05 +DOAV5G1iqMOQA2ub6TOuQLcX2gZn5iqlDbrZ/zFeKDS97V8jMsSxK1I9alECXvV0x 5hJaIEecAgl7g== Date: Mon, 21 Oct 2024 14:03:34 -0500 From: Rob Herring To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH 1/1] RFC: dt bindings: Add property "brcm,gen3-eq-presets" Message-ID: <20241021190334.GA953710-robh@kernel.org> References: <20241018182247.41130-1-james.quinlan@broadcom.com> <20241018182247.41130-2-james.quinlan@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241018182247.41130-2-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241021_120336_805705_A8055758 X-CRM114-Status: GOOD ( 16.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 18, 2024 at 02:22:45PM -0400, Jim Quinlan wrote: > Support configuration of the GEN3 preset equalization settings, aka the > Lane Equalization Control Register(s) of the Secondary PCI Express > Extended Capability. These registers are of type HwInit/RsvdP and > typically set by FW. In our case they are set by our RC host bridge > driver using internal registers. > > Signed-off-by: Jim Quinlan > --- > .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > index 0925c520195a..f965ad57f32f 100644 > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > @@ -104,6 +104,18 @@ properties: > minItems: 1 > maxItems: 3 > > + brcm,gen3-eq-presets: > + description: | > + A u16 array giving the GEN3 equilization presets, one for each lane. > + These values are destined for the 16bit registers known as the > + Lane Equalization Control Register(s) of the Secondary PCI Express > + Extended Capability. In the array, lane 0 is first term, lane 1 next, > + etc. The contents of the entries reflect what is necessary for > + the current board and SoC, and the details of each preset are > + described in Section 7.27.4 of the PCI base spec, Revision 3.0. If these are defined by the PCIe spec, then why is it Broadcom specific property? > + > + $ref: /schemas/types.yaml#/definitions/uint16-array minItems: 1 maxItems: 16 Last I saw, you can only have up to 16 lanes. Rob