From: Raghavendra Rao Ananta <rananta@google.com>
To: Subhasish Ghosh <subhasish.ghosh@arm.com>,
Joey Gouly <joey.gouly@arm.com>,
Andrew Jones <andrew.jones@linux.dev>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Marc Zyngier <maz@kernel.org>,
Raghavendra Rao Anata <rananta@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [kvm-unit-tests PATCH 3/3] arm: fpu: Fix the input/output args for inline asm in fpu.c
Date: Tue, 22 Oct 2024 00:47:10 +0000 [thread overview]
Message-ID: <20241022004710.1888067-4-rananta@google.com> (raw)
In-Reply-To: <20241022004710.1888067-1-rananta@google.com>
The macros fpu_reg_{read,write} post-increment the '__val'
pointer register as a part of 'stp' and 'ldp' instructions.
As a result, mark it with "+r" for the compiler to treat it
as read-write operand.
On the contrary, sve_reg_read() never updates the value of the
pointer/register. Hence, mark this as "r" for the compiler to
treat it as read-only operand.
Without these adjustments, the compiler can potentially perform
optimizations over the registers holding the pointers that could
lead to data aborts.
Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore")
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
arm/fpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arm/fpu.c b/arm/fpu.c
index 587b6ea3..6b0411d3 100644
--- a/arm/fpu.c
+++ b/arm/fpu.c
@@ -54,7 +54,7 @@ static inline bool arch_collect_entropy(uint64_t *random)
"stp q26, q27, [%0], #32\n\t" \
"stp q28, q29, [%0], #32\n\t" \
"stp q30, q31, [%0], #32\n\t" \
- : "=r" (__val) \
+ : "+r" (__val) \
: \
: "v0", "v1", "v2", "v3", \
"v4", "v5", "v6", "v7", \
@@ -87,8 +87,8 @@ do { \
"ldp q26, q27, [%0], #32\n\t" \
"ldp q28, q29, [%0], #32\n\t" \
"ldp q30, q31, [%0], #32\n\t" \
+ : "+r" (__val) \
: \
- : "r" (__val) \
: "v0", "v1", "v2", "v3", \
"v4", "v5", "v6", "v7", \
"v8", "v9", "v10", "v11", \
@@ -138,8 +138,8 @@ do { \
"str z29, [%0, #29, MUL VL]\n" \
"str z30, [%0, #30, MUL VL]\n" \
"str z31, [%0, #31, MUL VL]\n" \
- : "=r" (__val) \
: \
+ : "r" (__val) \
: "z0", "z1", "z2", "z3", \
"z4", "z5", "z6", "z7", \
"z8", "z9", "z10", "z11", \
--
2.47.0.105.g07ac214952-goog
next prev parent reply other threads:[~2024-10-22 1:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-22 0:47 [kvm-unit-tests PATCH 0/3] Fix arm64 clang errors on fpu tests Raghavendra Rao Ananta
2024-10-22 0:47 ` [kvm-unit-tests PATCH 1/3] arm: Fix clang error in sve_vl() Raghavendra Rao Ananta
2024-10-22 0:47 ` [kvm-unit-tests PATCH 2/3] arm: fpu: Convert 'q' registers to 'v' to satisfy clang Raghavendra Rao Ananta
2024-10-22 0:47 ` Raghavendra Rao Ananta [this message]
2024-10-22 13:10 ` [kvm-unit-tests PATCH 0/3] Fix arm64 clang errors on fpu tests Andrew Jones
2024-10-22 20:45 ` Raghavendra Rao Ananta
[not found] ` <CAJHc60wraJEBTAj-MCTA4QC6cEikvxfMcFRX8Ook9EVYKQu_Tw@mail.gmail.com>
2024-10-23 8:03 ` Andrew Jones
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