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From: Andrew Jones To: Raghavendra Rao Ananta Cc: Subhasish Ghosh , Joey Gouly , Oliver Upton , Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [kvm-unit-tests PATCH 0/3] Fix arm64 clang errors on fpu tests Message-ID: <20241023-f6a2a8d9fdea565838175648@orel> References: <20241022004710.1888067-1-rananta@google.com> <20241022-2c60a0bcbb908435aa91d1ff@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241023_010336_096330_5DCD51D2 X-CRM114-Status: GOOD ( 16.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 22, 2024 at 01:31:24PM -0700, Raghavendra Rao Ananta wrote: > Hi Andrew, > > > > > With clang 18.1.8 (Fedora 18.1.8-1.fc40) I get a bunch of errors like > > these > > > > arm/fpu.c:281:3: error: instruction requires: fp-armv8 > > > > I used my cross-clang series[1] and configured with > > > > ./configure --arch=arm64 --cc=clang --cflags='--target=aarch64' > --cross-prefix=aarch64-linux-gnu- > > > > [1] > https://lore.kernel.org/all/20240911091406.134240-7-andrew.jones@linux.dev/ > > > > Thanks, > > drew > > I was able to reproduce the errors by pointing to a newer clang (20) and > applying your series. > I think we see the errors because llvm decided to disable loads and stores > on FP registers with "-mgeneral-regs-only" [1]. Explicitly adding > ".arch_extension fp" for the fp_reg_{read,write}() helped with the build: > > diff --git a/arm/fpu.c b/arm/fpu.c > index 6b0411d3..f44ed82a 100644 > --- a/arm/fpu.c > +++ b/arm/fpu.c > @@ -38,7 +38,8 @@ static inline bool arch_collect_entropy(uint64_t *random) > #define fpu_reg_read(val) \ > ({ \ > uint64_t *__val = (val); \ > - asm volatile("stp q0, q1, [%0], #32\n\t" \ > + asm volatile(".arch_extension fp\n" \ > + "stp q0, q1, [%0], #32\n\t" \ > "stp q2, q3, [%0], #32\n\t" \ > "stp q4, q5, [%0], #32\n\t" \ > "stp q6, q7, [%0], #32\n\t" \ > @@ -71,7 +72,8 @@ static inline bool arch_collect_entropy(uint64_t *random) > #define fpu_reg_write(val) \ > do { \ > uint64_t *__val = (val); \ > - asm volatile("ldp q0, q1, [%0], #32\n\t" \ > + asm volatile(".arch_extension fp\n" \ > + "ldp q0, q1, [%0], #32\n\t" \ > "ldp q2, q3, [%0], #32\n\t" \ > "ldp q4, q5, [%0], #32\n\t" \ > "ldp q6, q7, [%0], #32\n\t" \ > > If you are fine with this, I can push it as a separate patch in v2. The fix works for me too. Please post v2. Thanks, drew