[PATCH 00/13] sunxi: A100/A133 second stage support

[PATCH 00/13] sunxi: A100/A133 second stage support

[Cody Eksal]

Hello! This is my first submission, so please be gentle :)

Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
submitted a patch series for the A100 series of SoCs; [1] intended to add
support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
implemented DVFS support. Some patches from the first series landed, but
the rest were seemingly abandoned.

Although references to the A100 have been removed by Allwinner, it is
believed that the A133 and A133 Plus, which are still available, are simply
better binned variants of the A100; no other differences have been noted
thus far, and the drivers for the A100 work on the A133 without any
additional modifications. There has been a resurgence of interest in the
A133; patches to allow mainline U-Boot to run on these devices are
currently in progress.

I have rebased the patches that failed to land, applying the feedback
provided by maintainers at the time. Some DT binding patches were added, as
there were a few cases where compatibles were used without being
documented. Minor reworks were necessary to apply certain patches, as the
drivers they modified have matured over time.

Patches 1 and 2 add PMU and watchdog nodes to the device tree. This is
followed by patches 3-8, which implement support for the USB host and OTG
peripherals. Patches 9 and 10 add MMC nodes, rounding out what originally
made up the first patch series; support for these already exists from
earlier patches. Patches 11-13 finish the job of the second original
series and this series, implementing OPP and enabling DVFS on these SoCs.

This series is also available on GitHub [3].

A sincere thanks to Andre for encouraging me to submit these patches,
Parthiban for testing this tree on his board, and to the linux-sunxi
community and its resources for pointing me to these abandoned series in
the first place [4].

[1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=380887&archive=both&state=*
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=396055&archive=both&state=*
[3] https://github.com/BrokenR3C0RD/linux-a100/compare/c2ee9f59..allwinner-a100
[4] https://linux-sunxi.org/Linux_mainlining_effort#Work_In_Progress

Cody Eksal (4):
  dt-bindings: phy: sun50i-a64: add a100 compatible
  dt-bindings: usb: Add A100 compatible string
  dt-bindings: usb: sunxi-musb: Add A100 compatible string
  dt-bindings: opp: h6: Add A100 operating points

Shuosheng Huang (2):
  cpufreq: sun50i: add a100 cpufreq support
  arm64: dts: allwinner: a100: Add CPU Operating Performance Points
    table

Yangtao Li (7):
  arm64: dts: allwinner: A100: Add PMU mode
  arm64: dts: allwinner: a100: add watchdog node
  phy: sun4i-usb: add support for A100 USB PHY
  arm64: dts: allwinner: a100: add usb related nodes
  arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
  arm64: allwinner: a100: Add MMC related nodes
  arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

 .../allwinner,sun50i-h6-operating-points.yaml |   1 +
 .../phy/allwinner,sun50i-a64-usb-phy.yaml     |   1 +
 .../usb/allwinner,sun4i-a10-musb.yaml         |   1 +
 .../devicetree/bindings/usb/generic-ehci.yaml |   1 +
 .../devicetree/bindings/usb/generic-ohci.yaml |   1 +
 .../allwinner/sun50i-a100-allwinner-perf1.dts |  59 ++++++
 .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    |  90 ++++++++
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 193 +++++++++++++++++-
 drivers/cpufreq/sun50i-cpufreq-nvmem.c        |  28 +++
 drivers/phy/allwinner/phy-sun4i-usb.c         |  11 +
 10 files changed, 383 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi


base-commit: c2ee9f594da826bea183ed14f2cc029c719bf4da
-- 
2.47.0

[PATCH 01/13] arm64: dts: allwinner: A100: Add PMU mode

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index a3dccf193765..1eca7c220ede 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.47.0

[PATCH 02/13] arm64: dts: allwinner: a100: add watchdog node

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Declare A100's watchdog in the device-tree.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 1eca7c220ede..adb11b26045f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -144,6 +144,14 @@ ths_calibration: calib@14 {
 			};
 		};
 
+		watchdog@30090a0 {
+			compatible = "allwinner,sun50i-a100-wdt",
+				     "allwinner,sun6i-a31-wdt";
+			reg = <0x030090a0 0x20>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo24M>;
+		};
+
 		pio: pinctrl@300b000 {
 			compatible = "allwinner,sun50i-a100-pinctrl";
 			reg = <0x0300b000 0x400>;
-- 
2.47.0

[PATCH 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Cody Eksal]

The USB PHY found in the A100 is similar to that found in the A64,
although it requires some quirks to be enabled. Add a compatible for the
A100's variant.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
index f557feca9763..b91e6c83722c 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
@@ -18,6 +18,7 @@ properties:
     enum:
       - allwinner,sun20i-d1-usb-phy
       - allwinner,sun50i-a64-usb-phy
+      - allwinner,sun50i-a100-usb-phy
 
   reg:
     items:
-- 
2.47.0

[PATCH 04/13] dt-bindings: usb: Add A100 compatible string

[Cody Eksal]

The Allwinner A100 contains two fully OHCI/EHCI compatible USB host
controllers. Add their compatible strings to the list of
generic OHCI/EHCI controllers.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
 Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 2ed178f16a78..e00e98dd04af 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -30,6 +30,7 @@ properties:
               - allwinner,sun4i-a10-ehci
               - allwinner,sun50i-a64-ehci
               - allwinner,sun50i-h6-ehci
+              - allwinner,sun50i-a100-ehci
               - allwinner,sun50i-h616-ehci
               - allwinner,sun5i-a13-ehci
               - allwinner,sun6i-a31-ehci
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index b9576015736b..6ce81979781b 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -17,6 +17,7 @@ properties:
               - allwinner,sun4i-a10-ohci
               - allwinner,sun50i-a64-ohci
               - allwinner,sun50i-h6-ohci
+              - allwinner,sun50i-a100-ohci
               - allwinner,sun50i-h616-ohci
               - allwinner,sun5i-a13-ohci
               - allwinner,sun6i-a31-ohci
-- 
2.47.0

[PATCH 05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string

[Cody Eksal]

The A100 MUSB peripheral has 10 endpoints, and thus is compatible with
the A33 version.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index f972ce976e86..d4993336a29b 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -24,6 +24,7 @@ properties:
               - allwinner,sun8i-a83t-musb
               - allwinner,sun20i-d1-musb
               - allwinner,sun50i-h6-musb
+              - allwinner,sun50i-a100-musb
           - const: allwinner,sun8i-a33-musb
       - items:
           - const: allwinner,sun50i-h616-musb
-- 
2.47.0

[PATCH 06/13] phy: sun4i-usb: add support for A100 USB PHY

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Add support for a100's usb phy, which with 2 PHYs.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
[masterr3c0rd@epochal.quest: modified to use quirk flags]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index b0f19e950601..a3942b2ee90b 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1006,6 +1006,16 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun50i_a100_cfg = {
+	.num_phys = 2,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+	.phy0_dual_route = true,
+	.siddq_in_base = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
 	.phyctl_offset = REG_PHYCTL_A33,
@@ -1040,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
+	{ .compatible = "allwinner,sun50i-a100-usb-phy", .data = &sun50i_a100_cfg },
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
 	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
-- 
2.47.0

[PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
PHY device, let's add nodes on dts.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
[masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index adb11b26045f..0aee1b578661 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		usbphy: phy@5100400 {
+			#phy-cells = <1>;
+			compatible = "allwinner,sun50i-a100-usb-phy";
+			reg = <0x05100400 0x14>,
+			      <0x05101800 0x4>,
+			      <0x05200800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu1";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY1>;
+			clock-names = "usb0_phy",
+				      "usb1_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>;
+			reset-names = "usb0_reset",
+				      "usb1_reset";
+			status = "disabled";
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-a100-ehci",
+				     "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-a100-ohci",
+				     "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		usb_otg: usb@5100000 {
+			compatible = "allwinner,sun50i-a100-musb",
+				     "allwinner,sun8i-a33-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			dr_mode = "otg";
+			status = "disabled";
+		};
+
+		ehci1: usb@5200000 {
+			compatible = "allwinner,sun50i-a100-ehci",
+				     "generic-ehci";
+			reg = <0x05200000 0x100>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_BUS_EHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>,
+				 <&ccu RST_BUS_EHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@5200400 {
+			compatible = "allwinner,sun50i-a100-ohci",
+				     "generic-ohci";
+			reg = <0x05200400 0x100>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-a100-r-ccu";
 			reg = <0x07010000 0x300>;
-- 
2.47.0

[PATCH 08/13] arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Add USB support on A100 perf1 board, which include two USB2.0 port.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../allwinner/sun50i-a100-allwinner-perf1.dts | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index f5c5c1464482..c6d8264b91b7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -7,6 +7,8 @@
 
 #include "sun50i-a100.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 /{
 	model = "Allwinner A100 Perf1";
 	compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
@@ -18,6 +20,35 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+		enable-active-high;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
 };
 
 &pio {
@@ -178,3 +209,10 @@ &uart0 {
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
-- 
2.47.0

[PATCH 09/13] arm64: allwinner: a100: Add MMC related nodes

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

The A100 has 3 MMC controllers, one of them being especially targeted to
eMMC. Let's add nodes on dts.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 0aee1b578661..6dca766ea222 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -169,12 +169,83 @@ pio: pinctrl@300b000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3",
+				       "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3",
+				       "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc2_pins: mmc2-pins {
+				pins = "PC0", "PC1", "PC5", "PC6",
+				       "PC8", "PC9", "PC10", "PC11",
+				       "PC13", "PC14", "PC15", "PC16";
+				function = "mmc2";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB9", "PB10";
 				function = "uart0";
 			};
 		};
 
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04020000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04021000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc1_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun50i-a100-emmc";
+			reg = <0x04022000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@5000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x05000000 0x400>;
-- 
2.47.0

[PATCH 10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../allwinner/sun50i-a100-allwinner-perf1.dts    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index c6d8264b91b7..29e9d24da8b6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -39,6 +39,22 @@ &ehci1 {
 	status = "okay";
 };
 
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_aldo1>;
+	cap-mmc-hw-reset;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
+
 &ohci0 {
 	status = "okay";
 };
-- 
2.47.0

[PATCH 11/13] dt-bindings: opp: h6: Add A100 operating points

[Cody Eksal]

The A100, similar to the H6 and H616, use an NVMEM value to determine
speed binnings. The method used is similar to that of the H6. However,
the information is stored at a slightly different bit offset.

Add a new compatible for the A100.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
index ec5e424bb3c8..603c6c88d080 100644
--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
@@ -23,6 +23,7 @@ properties:
   compatible:
     enum:
       - allwinner,sun50i-h6-operating-points
+      - allwinner,sun50i-a100-operating-points
       - allwinner,sun50i-h616-operating-points
 
   nvmem-cells:
-- 
2.47.0

[PATCH 12/13] cpufreq: sun50i: add a100 cpufreq support

[Cody Eksal]

From: Shuosheng Huang <huangshuosheng@allwinnertech.com>

Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
let us use efuse_xlate to extract the differentiated part.

Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: add A100 to opp_match_list]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 drivers/cpufreq/sun50i-cpufreq-nvmem.c | 28 ++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 293921acec93..3a29c026d364 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -22,6 +22,9 @@
 #define NVMEM_MASK	0x7
 #define NVMEM_SHIFT	5
 
+#define SUN50I_A100_NVMEM_MASK	0xf
+#define SUN50I_A100_NVMEM_SHIFT	12
+
 static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
 
 struct sunxi_cpufreq_data {
@@ -45,6 +48,23 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
 		return 0;
 }
 
+static u32 sun50i_a100_efuse_xlate(u32 speedbin)
+{
+	u32 efuse_value;
+
+	efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
+		      SUN50I_A100_NVMEM_MASK;
+
+	switch (efuse_value) {
+	case 0b100:
+		return 2;
+	case 0b010:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
 static int get_soc_id_revision(void)
 {
 #ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
@@ -108,6 +128,10 @@ static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
 	.efuse_xlate = sun50i_h6_efuse_xlate,
 };
 
+static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
+	.efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
 static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
 	.efuse_xlate = sun50i_h616_efuse_xlate,
 };
@@ -116,6 +140,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
 	{ .compatible = "allwinner,sun50i-h6-operating-points",
 	  .data = &sun50i_h6_cpufreq_data,
 	},
+	{ .compatible = "allwinner,sun50i-a100-operating-points",
+	  .data = &sun50i_a100_cpufreq_data,
+	},
 	{ .compatible = "allwinner,sun50i-h616-operating-points",
 	  .data = &sun50i_h616_cpufreq_data,
 	},
@@ -291,6 +318,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
 
 static const struct of_device_id sun50i_cpufreq_match_list[] = {
 	{ .compatible = "allwinner,sun50i-h6" },
+	{ .compatible = "allwinner,sun50i-a100" },
 	{ .compatible = "allwinner,sun50i-h616" },
 	{ .compatible = "allwinner,sun50i-h618" },
 	{ .compatible = "allwinner,sun50i-h700" },
-- 
2.47.0

[PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table

[Cody Eksal]

From: Shuosheng Huang <huangshuosheng@allwinnertech.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.

Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../allwinner/sun50i-a100-allwinner-perf1.dts |  5 ++
 .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    | 90 +++++++++++++++++++
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi |  8 ++
 3 files changed, 103 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index 29e9d24da8b6..99b1b2f7b92a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "sun50i-a100.dtsi"
+#include "sun50i-a100-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -67,6 +68,10 @@ &usb_otg {
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &pio {
 	vcc-pb-supply = <&reg_dcdc1>;
 	vcc-pc-supply = <&reg_eldo1>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
new file mode 100644
index 000000000000..eeb8d20f3fb4
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
+
+/ {
+	cpu_opp_table: cpu-opp-table {
+		compatible = "allwinner,sun50i-a100-operating-points";
+		nvmem-cells = <&cpu_speed_grade>;
+		opp-shared;
+
+		opp@408000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <408000000>;
+
+			opp-microvolt-speed0 = <900000 900000 1200000>;
+			opp-microvolt-speed1 = <900000 900000 1200000>;
+			opp-microvolt-speed2 = <900000 900000 1200000>;
+		};
+
+		opp@600000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <600000000>;
+
+			opp-microvolt-speed0 = <900000 900000 1200000>;
+			opp-microvolt-speed1 = <900000 900000 1200000>;
+			opp-microvolt-speed2 = <900000 900000 1200000>;
+		};
+
+		opp@816000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <816000000>;
+
+			opp-microvolt-speed0 = <940000 940000 1200000>;
+			opp-microvolt-speed1 = <900000 900000 1200000>;
+			opp-microvolt-speed2 = <900000 900000 1200000>;
+		};
+
+		opp@1080000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1080000000>;
+
+			opp-microvolt-speed0 = <1020000 1020000 1200000>;
+			opp-microvolt-speed1 = <980000 980000 1200000>;
+			opp-microvolt-speed2 = <950000 950000 1200000>;
+		};
+
+		opp@1200000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1200000000>;
+
+			opp-microvolt-speed0 = <1100000 1100000 1200000>;
+			opp-microvolt-speed1 = <1020000 1020000 1200000>;
+			opp-microvolt-speed2 = <1000000 1000000 1200000>;
+		};
+
+		opp@1320000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1320000000>;
+
+			opp-microvolt-speed0 = <1160000 1160000 1200000>;
+			opp-microvolt-speed1 = <1060000 1060000 1200000>;
+			opp-microvolt-speed2 = <1030000 1030000 1200000>;
+		};
+
+		opp@1464000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1464000000>;
+
+			opp-microvolt-speed0 = <1180000 1180000 1200000>;
+			opp-microvolt-speed1 = <1180000 1180000 1200000>;
+			opp-microvolt-speed2 = <1130000 1130000 1200000>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 6dca766ea222..747a0292ef98 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -23,6 +23,7 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			reg = <0x0>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu1: cpu@1 {
@@ -30,6 +31,7 @@ cpu1: cpu@1 {
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu2: cpu@2 {
@@ -37,6 +39,7 @@ cpu2: cpu@2 {
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu3: cpu@3 {
@@ -44,6 +47,7 @@ cpu3: cpu@3 {
 			device_type = "cpu";
 			reg = <0x3>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 	};
 
@@ -142,6 +146,10 @@ efuse@3006000 {
 			ths_calibration: calib@14 {
 				reg = <0x14 8>;
 			};
+
+			cpu_speed_grade: cpu-speed-grade@1c {
+				reg = <0x1c 0x2>;
+			};
 		};
 
 		watchdog@30090a0 {
-- 
2.47.0

Re: [PATCH 06/13] phy: sun4i-usb: add support for A100 USB PHY

[Andre Przywara]

On Thu, 24 Oct 2024 14:05:24 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

Hi,

> From: Yangtao Li <frank@allwinnertech.com>
> 
> Add support for a100's usb phy, which with 2 PHYs.
> 
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> [masterr3c0rd@epochal.quest: modified to use quirk flags]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
> index b0f19e950601..a3942b2ee90b 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -1006,6 +1006,16 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
>  	.phy0_dual_route = true,
>  };
>  
> +static const struct sun4i_usb_phy_cfg sun50i_a100_cfg = {
> +	.num_phys = 2,
> +	.disc_thresh = 3,

This member is never used when .siddq_in_base is true (and yes, this is
wrong for the H616 too), ...

> +	.phyctl_offset = REG_PHYCTL_A33,
> +	.dedicated_clocks = true,
> +	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
> +	.phy0_dual_route = true,
> +	.siddq_in_base = true,

... which makes this whole description identical to the D1 version.
So at the very least we wouldn't this new a100_cfg, but instead just
point to the existing d1_cfg.

> +};
> +
>  static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
>  	.num_phys = 4,
>  	.phyctl_offset = REG_PHYCTL_A33,
> @@ -1040,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
>  	{ .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
>  	{ .compatible = "allwinner,sun50i-a64-usb-phy",
>  	  .data = &sun50i_a64_cfg},
> +	{ .compatible = "allwinner,sun50i-a100-usb-phy", .data = &sun50i_a100_cfg },

And this also brings up the question whether we need a new compatible
string. As it stands now, we could also use:
	compatible = "allwinner,sun50i-a100-usb-phy",
		     "allwinner,sun20i-d1-usb-phy";

and wouldn't need any driver changes at all. Which would have the neat
side effect to make USB work already with v5.18 kernels.

The only downside is the somewhat weird ordering of the compatible
strings, with the much newer chip as the fallback.

What do other people think here?

Cheers,
Andre


>  	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
>  	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
>  	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",

Re: [PATCH 04/13] dt-bindings: usb: Add A100 compatible string

[Andre Przywara]

On Thu, 24 Oct 2024 18:05:22 +0100
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> The Allwinner A100 contains two fully OHCI/EHCI compatible USB host
> controllers. Add their compatible strings to the list of
> generic OHCI/EHCI controllers.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
>  Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> index 2ed178f16a78..e00e98dd04af 100644
> --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> @@ -30,6 +30,7 @@ properties:
>                - allwinner,sun4i-a10-ehci
>                - allwinner,sun50i-a64-ehci
>                - allwinner,sun50i-h6-ehci
> +              - allwinner,sun50i-a100-ehci
>                - allwinner,sun50i-h616-ehci
>                - allwinner,sun5i-a13-ehci
>                - allwinner,sun6i-a31-ehci
> diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> index b9576015736b..6ce81979781b 100644
> --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> @@ -17,6 +17,7 @@ properties:
>                - allwinner,sun4i-a10-ohci
>                - allwinner,sun50i-a64-ohci
>                - allwinner,sun50i-h6-ohci
> +              - allwinner,sun50i-a100-ohci
>                - allwinner,sun50i-h616-ohci
>                - allwinner,sun5i-a13-ohci
>                - allwinner,sun6i-a31-ohci

Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table

[Andre Przywara]

On Thu, 24 Oct 2024 14:05:31 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> 
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
> 
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../allwinner/sun50i-a100-allwinner-perf1.dts |  5 ++
>  .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    | 90 +++++++++++++++++++
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi |  8 ++
>  3 files changed, 103 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index 29e9d24da8b6..99b1b2f7b92a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -6,6 +6,7 @@
>  /dts-v1/;
>  
>  #include "sun50i-a100.dtsi"
> +#include "sun50i-a100-cpu-opp.dtsi"
>  
>  #include <dt-bindings/gpio/gpio.h>
>  
> @@ -67,6 +68,10 @@ &usb_otg {
>  	status = "okay";
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&reg_dcdc2>;
> +};
> +
>  &pio {
>  	vcc-pb-supply = <&reg_dcdc1>;
>  	vcc-pc-supply = <&reg_eldo1>;
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> new file mode 100644
> index 000000000000..eeb8d20f3fb4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
> +
> +/ {
> +	cpu_opp_table: cpu-opp-table {
> +		compatible = "allwinner,sun50i-a100-operating-points";
> +		nvmem-cells = <&cpu_speed_grade>;
> +		opp-shared;
> +
> +		opp@408000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <408000000>;
> +
> +			opp-microvolt-speed0 = <900000 900000 1200000>;
> +			opp-microvolt-speed1 = <900000 900000 1200000>;
> +			opp-microvolt-speed2 = <900000 900000 1200000>;

Is there actually an advantage when using the three cells version?
I wonder if we should go with just the target voltage (the first cell
here), as done for the H616.

Apart from that it looks fine to me.

Cheers,
Andre.

> +		};
> +
> +		opp@600000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <600000000>;
> +
> +			opp-microvolt-speed0 = <900000 900000 1200000>;
> +			opp-microvolt-speed1 = <900000 900000 1200000>;
> +			opp-microvolt-speed2 = <900000 900000 1200000>;
> +		};
> +
> +		opp@816000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <816000000>;
> +
> +			opp-microvolt-speed0 = <940000 940000 1200000>;
> +			opp-microvolt-speed1 = <900000 900000 1200000>;
> +			opp-microvolt-speed2 = <900000 900000 1200000>;
> +		};
> +
> +		opp@1080000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <1080000000>;
> +
> +			opp-microvolt-speed0 = <1020000 1020000 1200000>;
> +			opp-microvolt-speed1 = <980000 980000 1200000>;
> +			opp-microvolt-speed2 = <950000 950000 1200000>;
> +		};
> +
> +		opp@1200000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <1200000000>;
> +
> +			opp-microvolt-speed0 = <1100000 1100000 1200000>;
> +			opp-microvolt-speed1 = <1020000 1020000 1200000>;
> +			opp-microvolt-speed2 = <1000000 1000000 1200000>;
> +		};
> +
> +		opp@1320000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <1320000000>;
> +
> +			opp-microvolt-speed0 = <1160000 1160000 1200000>;
> +			opp-microvolt-speed1 = <1060000 1060000 1200000>;
> +			opp-microvolt-speed2 = <1030000 1030000 1200000>;
> +		};
> +
> +		opp@1464000000 {
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			opp-hz = /bits/ 64 <1464000000>;
> +
> +			opp-microvolt-speed0 = <1180000 1180000 1200000>;
> +			opp-microvolt-speed1 = <1180000 1180000 1200000>;
> +			opp-microvolt-speed2 = <1130000 1130000 1200000>;
> +		};
> +	};
> +};
> +
> +&cpu0 {
> +	operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu1 {
> +	operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu2 {
> +	operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu3 {
> +	operating-points-v2 = <&cpu_opp_table>;
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 6dca766ea222..747a0292ef98 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
>  			device_type = "cpu";
>  			reg = <0x0>;
>  			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
>  			device_type = "cpu";
>  			reg = <0x1>;
>  			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
>  		};
>  
>  		cpu2: cpu@2 {
> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
>  			device_type = "cpu";
>  			reg = <0x2>;
>  			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
>  		};
>  
>  		cpu3: cpu@3 {
> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
>  			device_type = "cpu";
>  			reg = <0x3>;
>  			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
>  		};
>  	};
>  
> @@ -142,6 +146,10 @@ efuse@3006000 {
>  			ths_calibration: calib@14 {
>  				reg = <0x14 8>;
>  			};
> +
> +			cpu_speed_grade: cpu-speed-grade@1c {
> +				reg = <0x1c 0x2>;
> +			};
>  		};
>  
>  		watchdog@30090a0 {

Re: [PATCH 00/13] sunxi: A100/A133 second stage support

[Rob Herring (Arm)]

On Thu, 24 Oct 2024 14:05:18 -0300, Cody Eksal wrote:
> Hello! This is my first submission, so please be gentle :)
> 
> Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
> submitted a patch series for the A100 series of SoCs; [1] intended to add
> support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
> implemented DVFS support. Some patches from the first series landed, but
> the rest were seemingly abandoned.
> 
> Although references to the A100 have been removed by Allwinner, it is
> believed that the A133 and A133 Plus, which are still available, are simply
> better binned variants of the A100; no other differences have been noted
> thus far, and the drivers for the A100 work on the A133 without any
> additional modifications. There has been a resurgence of interest in the
> A133; patches to allow mainline U-Boot to run on these devices are
> currently in progress.
> 
> I have rebased the patches that failed to land, applying the feedback
> provided by maintainers at the time. Some DT binding patches were added, as
> there were a few cases where compatibles were used without being
> documented. Minor reworks were necessary to apply certain patches, as the
> drivers they modified have matured over time.
> 
> Patches 1 and 2 add PMU and watchdog nodes to the device tree. This is
> followed by patches 3-8, which implement support for the USB host and OTG
> peripherals. Patches 9 and 10 add MMC nodes, rounding out what originally
> made up the first patch series; support for these already exists from
> earlier patches. Patches 11-13 finish the job of the second original
> series and this series, implementing OPP and enabling DVFS on these SoCs.
> 
> This series is also available on GitHub [3].
> 
> A sincere thanks to Andre for encouraging me to submit these patches,
> Parthiban for testing this tree on his board, and to the linux-sunxi
> community and its resources for pointing me to these abandoned series in
> the first place [4].
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=380887&archive=both&state=*
> [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=396055&archive=both&state=*
> [3] https://github.com/BrokenR3C0RD/linux-a100/compare/c2ee9f59..allwinner-a100
> [4] https://linux-sunxi.org/Linux_mainlining_effort#Work_In_Progress
> 
> Cody Eksal (4):
>   dt-bindings: phy: sun50i-a64: add a100 compatible
>   dt-bindings: usb: Add A100 compatible string
>   dt-bindings: usb: sunxi-musb: Add A100 compatible string
>   dt-bindings: opp: h6: Add A100 operating points
> 
> Shuosheng Huang (2):
>   cpufreq: sun50i: add a100 cpufreq support
>   arm64: dts: allwinner: a100: Add CPU Operating Performance Points
>     table
> 
> Yangtao Li (7):
>   arm64: dts: allwinner: A100: Add PMU mode
>   arm64: dts: allwinner: a100: add watchdog node
>   phy: sun4i-usb: add support for A100 USB PHY
>   arm64: dts: allwinner: a100: add usb related nodes
>   arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
>   arm64: allwinner: a100: Add MMC related nodes
>   arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
> 
>  .../allwinner,sun50i-h6-operating-points.yaml |   1 +
>  .../phy/allwinner,sun50i-a64-usb-phy.yaml     |   1 +
>  .../usb/allwinner,sun4i-a10-musb.yaml         |   1 +
>  .../devicetree/bindings/usb/generic-ehci.yaml |   1 +
>  .../devicetree/bindings/usb/generic-ohci.yaml |   1 +
>  .../allwinner/sun50i-a100-allwinner-perf1.dts |  59 ++++++
>  .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    |  90 ++++++++
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 193 +++++++++++++++++-
>  drivers/cpufreq/sun50i-cpufreq-nvmem.c        |  28 +++
>  drivers/phy/allwinner/phy-sun4i-usb.c         |  11 +
>  10 files changed, 383 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> 
> 
> base-commit: c2ee9f594da826bea183ed14f2cc029c719bf4da
> --
> 2.47.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y allwinner/sun50i-a100-allwinner-perf1.dtb' for 20241024170540.2721307-1-masterr3c0rd@epochal.quest:

arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dtb: cpu-opp-table: $nodename:0: 'cpu-opp-table' does not match '^opp-table(-[a-z0-9]+)?$'
	from schema $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dtb: cpu-opp-table: 'opp@1080000000', 'opp@1200000000', 'opp@1320000000', 'opp@1464000000', 'opp@408000000', 'opp@600000000', 'opp@816000000' do not match any of the regexes: '^opp-[0-9]+$', 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#

Re: [PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

[Andre Przywara]

On Thu, 24 Oct 2024 14:05:25 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

Hi,

> From: Yangtao Li <frank@allwinnertech.com>
> 
> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
> PHY device, let's add nodes on dts.
> 
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index adb11b26045f..0aee1b578661 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> +		usbphy: phy@5100400 {
> +			#phy-cells = <1>;

Please keep the compatible string first, and move #phy-cells to the end.

> +			compatible = "allwinner,sun50i-a100-usb-phy";
> +			reg = <0x05100400 0x14>,
> +			      <0x05101800 0x4>,
> +			      <0x05200800 0x4>;

We need at least 0x24 for the phy_ctrl and 0x14 for the PMUs. But I
wonder if we should use 0x100 for all of them, like for the D1, as there
are more registers. The fact that the Linux driver doesn't use more
shouldn't prevent the DT from describing them.

> +			reg-names = "phy_ctrl",
> +				    "pmu0",
> +				    "pmu1";
> +			clocks = <&ccu CLK_USB_PHY0>,
> +				 <&ccu CLK_USB_PHY1>;
> +			clock-names = "usb0_phy",
> +				      "usb1_phy";
> +			resets = <&ccu RST_USB_PHY0>,
> +				 <&ccu RST_USB_PHY1>;
> +			reset-names = "usb0_reset",
> +				      "usb1_reset";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb@5101000 {

The nodes are ordered by their MMIO base address, so please move them
around accordingly.

> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_BUS_EHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>,
> +				 <&ccu RST_BUS_EHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@5101400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		usb_otg: usb@5100000 {
> +			compatible = "allwinner,sun50i-a100-musb",
> +				     "allwinner,sun8i-a33-musb";
> +			reg = <0x05100000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			dr_mode = "otg";

dr_mode should be set in the board .dts, so please remove that line
from here.

For the records: I checked the MMIO base addresses, clock and reset
names and the IRQs against the manual: they all match.

Cheers,
Andre

> +			status = "disabled";
> +		};
> +
> +		ehci1: usb@5200000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05200000 0x100>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_BUS_EHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>,
> +				 <&ccu RST_BUS_EHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci1: usb@5200400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05200400 0x100>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
>  		r_ccu: clock@7010000 {
>  			compatible = "allwinner,sun50i-a100-r-ccu";
>  			reg = <0x07010000 0x300>;

Re: [PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

[Chen-Yu Tsai]

On Fri, Oct 25, 2024 at 1:09 AM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> From: Yangtao Li <frank@allwinnertech.com>
>
> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB

            ^^^ Please update this.

> PHY device, let's add nodes on dts.
>
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index adb11b26045f..0aee1b578661 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>                         #thermal-sensor-cells = <1>;
>                 };
>
> +               usbphy: phy@5100400 {
> +                       #phy-cells = <1>;
> +                       compatible = "allwinner,sun50i-a100-usb-phy";
> +                       reg = <0x05100400 0x14>,
> +                             <0x05101800 0x4>,
> +                             <0x05200800 0x4>;
> +                       reg-names = "phy_ctrl",
> +                                   "pmu0",
> +                                   "pmu1";
> +                       clocks = <&ccu CLK_USB_PHY0>,
> +                                <&ccu CLK_USB_PHY1>;
> +                       clock-names = "usb0_phy",
> +                                     "usb1_phy";
> +                       resets = <&ccu RST_USB_PHY0>,
> +                                <&ccu RST_USB_PHY1>;
> +                       reset-names = "usb0_reset",
> +                                     "usb1_reset";
> +                       status = "disabled";
> +               };
> +
> +               ehci0: usb@5101000 {
> +                       compatible = "allwinner,sun50i-a100-ehci",
> +                                    "generic-ehci";
> +                       reg = <0x05101000 0x100>;
> +                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_BUS_EHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>,
> +                                <&ccu RST_BUS_EHCI0>;
> +                       phys = <&usbphy 0>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
> +               ohci0: usb@5101400 {
> +                       compatible = "allwinner,sun50i-a100-ohci",
> +                                    "generic-ohci";
> +                       reg = <0x05101400 0x100>;
> +                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>;
> +                       phys = <&usbphy 0>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
> +               usb_otg: usb@5100000 {
> +                       compatible = "allwinner,sun50i-a100-musb",
> +                                    "allwinner,sun8i-a33-musb";
> +                       reg = <0x05100000 0x0400>;
> +                       clocks = <&ccu CLK_BUS_OTG>;
> +                       resets = <&ccu RST_BUS_OTG>;
> +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "mc";
> +                       phys = <&usbphy 0>;
> +                       phy-names = "usb";
> +                       extcon = <&usbphy 0>;
> +                       dr_mode = "otg";
> +                       status = "disabled";
> +               };
> +
> +               ehci1: usb@5200000 {
> +                       compatible = "allwinner,sun50i-a100-ehci",
> +                                    "generic-ehci";
> +                       reg = <0x05200000 0x100>;
> +                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI1>,
> +                                <&ccu CLK_BUS_EHCI1>,
> +                                <&ccu CLK_USB_OHCI1>;
> +                       resets = <&ccu RST_BUS_OHCI1>,
> +                                <&ccu RST_BUS_EHCI1>;
> +                       phys = <&usbphy 1>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
> +               ohci1: usb@5200400 {
> +                       compatible = "allwinner,sun50i-a100-ohci",
> +                                    "generic-ohci";
> +                       reg = <0x05200400 0x100>;
> +                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI1>,
> +                                <&ccu CLK_USB_OHCI1>;
> +                       resets = <&ccu RST_BUS_OHCI1>;
> +                       phys = <&usbphy 1>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
>                 r_ccu: clock@7010000 {
>                         compatible = "allwinner,sun50i-a100-r-ccu";
>                         reg = <0x07010000 0x300>;
> --
> 2.47.0
>
>

Re: [PATCH 05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 02:05:23PM -0300, Cody Eksal wrote:
> The A100 MUSB peripheral has 10 endpoints, and thus is compatible with
> the A33 version.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
> index f972ce976e86..d4993336a29b 100644
> --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
> +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
> @@ -24,6 +24,7 @@ properties:
>                - allwinner,sun8i-a83t-musb
>                - allwinner,sun20i-d1-musb
>                - allwinner,sun50i-h6-musb
> +              - allwinner,sun50i-a100-musb

List looked ordered, now doesn't.... are you sure you keep intented
ordering here?

Best regards,
Krzysztof

Re: [PATCH 11/13] dt-bindings: opp: h6: Add A100 operating points

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 02:05:29PM -0300, Cody Eksal wrote:
> The A100, similar to the H6 and H616, use an NVMEM value to determine
> speed binnings. The method used is similar to that of the H6. However,
> the information is stored at a slightly different bit offset.
> 
> Add a new compatible for the A100.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml       | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> index ec5e424bb3c8..603c6c88d080 100644
> --- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> @@ -23,6 +23,7 @@ properties:
>    compatible:
>      enum:
>        - allwinner,sun50i-h6-operating-points
> +      - allwinner,sun50i-a100-operating-points
>        - allwinner,sun50i-h616-operating-points

I have no clue why a100 is between h6 and h616. :/

Best regards,
Krzysztof

Re: [PATCH 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Rob Herring (Arm)]

On Thu, 24 Oct 2024 14:05:21 -0300, Cody Eksal wrote:
> The USB PHY found in the A100 is similar to that found in the A64,
> although it requires some quirks to be enabled. Add a compatible for the
> A100's variant.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml    | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 04/13] dt-bindings: usb: Add A100 compatible string

[Rob Herring (Arm)]

On Thu, 24 Oct 2024 14:05:22 -0300, Cody Eksal wrote:
> The Allwinner A100 contains two fully OHCI/EHCI compatible USB host
> controllers. Add their compatible strings to the list of
> generic OHCI/EHCI controllers.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
>  Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
>  2 files changed, 2 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 11/13] dt-bindings: opp: h6: Add A100 operating points

[Krzysztof Kozlowski]

On 27/10/2024 22:13, Cody Eksal wrote:
> On 2024/10/27 5:47 pm, Krzysztof Kozlowski wrote:
>> On Thu, Oct 24, 2024 at 02:05:29PM -0300, Cody Eksal wrote:
>>> diff --git 
>>> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml 
>>> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>> index ec5e424bb3c8..603c6c88d080 100644
>>> --- 
>>> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>> +++ 
>>> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>> @@ -23,6 +23,7 @@ properties:
>>>    compatible:
>>>      enum:
>>>        - allwinner,sun50i-h6-operating-points
>>> +      - allwinner,sun50i-a100-operating-points
>>>        - allwinner,sun50i-h616-operating-points
>>
>> I have no clue why a100 is between h6 and h616. :/
>  From my understanding, the A100 was released before the H616, but after 
> the H6. There are not many sources to rely on for this, but the H6 
> appears to have launched in 2017, the A100 in 2019, and the H616 in 
> 2020.
> 
> I assumed ordering was intended to be in chronological order; perhaps it 
> was intended to be in lexicographical order instead? If so, I can move 
> this entry above the H6.

Most, really most of the lists in the bindings are ordered
alphanumerically, because that's the only order all people will get and
all people can really verify. There are exceptions. If that's the one
here, then sure, keep chronological order.

Best regards,
Krzysztof

Re: [PATCH 04/13] dt-bindings: usb: Add A100 compatible string

[Rob Herring]

On Sun, Oct 27, 2024 at 04:12:29PM -0500, Rob Herring (Arm) wrote:
> 
> On Thu, 24 Oct 2024 14:05:22 -0300, Cody Eksal wrote:
> > The Allwinner A100 contains two fully OHCI/EHCI compatible USB host
> > controllers. Add their compatible strings to the list of
> > generic OHCI/EHCI controllers.
> > 
> > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > ---
> >  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
> >  Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> 
> Acked-by: Rob Herring (Arm) <robh@kernel.org>

Well, except that the compatibles should be alphabetical order.

Rob

Re: [PATCH 04/13] dt-bindings: usb: Add A100 compatible string

[Cody Eksal]

On 2024/10/27 6:22 pm, Rob Herring wrote:
> On Sun, Oct 27, 2024 at 04:12:29PM -0500, Rob Herring (Arm) wrote:
>> 
>> On Thu, 24 Oct 2024 14:05:22 -0300, Cody Eksal wrote:
>> > The Allwinner A100 contains two fully OHCI/EHCI compatible USB host
>> > controllers. Add their compatible strings to the list of
>> > generic OHCI/EHCI controllers.
>> >
>> > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> > ---
>> >  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
>> >  Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
>> >  2 files changed, 2 insertions(+)
>> >
>> 
>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> 
> Well, except that the compatibles should be alphabetical order.
Will be fixed in V2, thanks!
- Cody
> Rob

Re: [PATCH 05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string

[Cody Eksal]

On 2024/10/27 5:47 pm, Krzysztof Kozlowski wrote:
> On Thu, Oct 24, 2024 at 02:05:23PM -0300, Cody Eksal wrote:
>> diff --git 
>> a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml 
>> b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
>> index f972ce976e86..d4993336a29b 100644
>> --- 
>> a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
>> +++ 
>> b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
>> @@ -24,6 +24,7 @@ properties:
>>                - allwinner,sun8i-a83t-musb
>>                - allwinner,sun20i-d1-musb
>>                - allwinner,sun50i-h6-musb
>> +              - allwinner,sun50i-a100-musb
> 
> List looked ordered, now doesn't.... are you sure you keep intented
> ordering here?
I'll move this entry to fit the expected order for V2, thanks!

- Cody
> Best regards,
> Krzysztof

Re: [PATCH 06/13] phy: sun4i-usb: add support for A100 USB PHY

[Cody Eksal]

On 2024/10/24 4:22 pm, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:24 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c 
>> b/drivers/phy/allwinner/phy-sun4i-usb.c
>> index b0f19e950601..a3942b2ee90b 100644
>> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
>> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
>> @@ -1006,6 +1006,16 @@ static const struct sun4i_usb_phy_cfg 
>> sun50i_a64_cfg = {
>>  	.phy0_dual_route = true,
>>  };
>> 
>> +static const struct sun4i_usb_phy_cfg sun50i_a100_cfg = {
>> +	.num_phys = 2,
>> +	.disc_thresh = 3,
> 
> This member is never used when .siddq_in_base is true (and yes, this is
> wrong for the H616 too), ...
> 
>> +	.phyctl_offset = REG_PHYCTL_A33,
>> +	.dedicated_clocks = true,
>> +	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
>> +	.phy0_dual_route = true,
>> +	.siddq_in_base = true,
> 
> ... which makes this whole description identical to the D1 version.
> So at the very least we wouldn't this new a100_cfg, but instead just
> point to the existing d1_cfg.
I did test on my board and confirmed simply using a D1 compatible works.
> And this also brings up the question whether we need a new compatible
> string. As it stands now, we could also use:
> 	compatible = "allwinner,sun50i-a100-usb-phy",
> 		     "allwinner,sun20i-d1-usb-phy";
> 
> and wouldn't need any driver changes at all. Which would have the neat
> side effect to make USB work already with v5.18 kernels.
> 
> The only downside is the somewhat weird ordering of the compatible
> strings, with the much newer chip as the fallback.
I plan to drop this patch in V2, in favor of just adding the 
compatible/fallback. Although it's odd ordering, I would think fixing 
the DTS of other device trees to remedy this would probably not be worth 
the hassle.
Thanks for pointing this out!

- Cody
> What do other people think here?
> 
> Cheers,
> Andre

Re: [PATCH 11/13] dt-bindings: opp: h6: Add A100 operating points

[Cody Eksal]

On 2024/10/27 6:17 pm, Krzysztof Kozlowski wrote:
> On 27/10/2024 22:13, Cody Eksal wrote:
>> On 2024/10/27 5:47 pm, Krzysztof Kozlowski wrote:
>>> On Thu, Oct 24, 2024 at 02:05:29PM -0300, Cody Eksal wrote:
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>>> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>>> index ec5e424bb3c8..603c6c88d080 100644
>>>> ---
>>>> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>>> +++
>>>> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
>>>> @@ -23,6 +23,7 @@ properties:
>>>>    compatible:
>>>>      enum:
>>>>        - allwinner,sun50i-h6-operating-points
>>>> +      - allwinner,sun50i-a100-operating-points
>>>>        - allwinner,sun50i-h616-operating-points
>>> 
>>> I have no clue why a100 is between h6 and h616. :/
>>  From my understanding, the A100 was released before the H616, but 
>> after
>> the H6. There are not many sources to rely on for this, but the H6
>> appears to have launched in 2017, the A100 in 2019, and the H616 in
>> 2020.
>> 
>> I assumed ordering was intended to be in chronological order; perhaps 
>> it
>> was intended to be in lexicographical order instead? If so, I can move
>> this entry above the H6.
> 
> Most, really most of the lists in the bindings are ordered
> alphanumerically, because that's the only order all people will get and
> all people can really verify. There are exceptions. If that's the one
> here, then sure, keep chronological order.
After reviewing other files, it seems like alphanumeric ordering is 
normally used in the bindings for these peripherals. I'll update in V2.

Thank you!
- Cody
> Best regards,
> Krzysztof

Re: [PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

[Cody Eksal]

On 2024/10/25 9:44 pm, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:25 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> 
> Hi,
> 
>> From: Yangtao Li <frank@allwinnertech.com>
>> 
>> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
>> PHY device, let's add nodes on dts.
>> 
>> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 
>> +++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index adb11b26045f..0aee1b578661 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>>  			#thermal-sensor-cells = <1>;
>>  		};
>> 
>> +		usbphy: phy@5100400 {
>> +			#phy-cells = <1>;
> 
> Please keep the compatible string first, and move #phy-cells to the 
> end.
Will be done in V2
>> +			compatible = "allwinner,sun50i-a100-usb-phy";
>> +			reg = <0x05100400 0x14>,
>> +			      <0x05101800 0x4>,
>> +			      <0x05200800 0x4>;
> 
> We need at least 0x24 for the phy_ctrl and 0x14 for the PMUs. But I
> wonder if we should use 0x100 for all of them, like for the D1, as 
> there
> are more registers. The fact that the Linux driver doesn't use more
> shouldn't prevent the DT from describing them.
This as well.
>> +			reg-names = "phy_ctrl",
>> +				    "pmu0",
>> +				    "pmu1";
>> +			clocks = <&ccu CLK_USB_PHY0>,
>> +				 <&ccu CLK_USB_PHY1>;
>> +			clock-names = "usb0_phy",
>> +				      "usb1_phy";
>> +			resets = <&ccu RST_USB_PHY0>,
>> +				 <&ccu RST_USB_PHY1>;
>> +			reset-names = "usb0_reset",
>> +				      "usb1_reset";
>> +			status = "disabled";
>> +		};
>> +
>> +		ehci0: usb@5101000 {
> 
> The nodes are ordered by their MMIO base address, so please move them
> around accordingly.
I double checked; the only note that wasn't in order was MUSB, which 
fits above the USB PHY in the memory map. I've moved those up.
>> +			compatible = "allwinner,sun50i-a100-ehci",
>> +				     "generic-ehci";
>> +			reg = <0x05101000 0x100>;
>> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_OHCI0>,
>> +				 <&ccu CLK_BUS_EHCI0>,
>> +				 <&ccu CLK_USB_OHCI0>;
>> +			resets = <&ccu RST_BUS_OHCI0>,
>> +				 <&ccu RST_BUS_EHCI0>;
>> +			phys = <&usbphy 0>;
>> +			phy-names = "usb";
>> +			status = "disabled";
>> +		};
>> +
>> +		ohci0: usb@5101400 {
>> +			compatible = "allwinner,sun50i-a100-ohci",
>> +				     "generic-ohci";
>> +			reg = <0x05101400 0x100>;
>> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_OHCI0>,
>> +				 <&ccu CLK_USB_OHCI0>;
>> +			resets = <&ccu RST_BUS_OHCI0>;
>> +			phys = <&usbphy 0>;
>> +			phy-names = "usb";
>> +			status = "disabled";
>> +		};
>> +
>> +		usb_otg: usb@5100000 {
>> +			compatible = "allwinner,sun50i-a100-musb",
>> +				     "allwinner,sun8i-a33-musb";
>> +			reg = <0x05100000 0x0400>;
>> +			clocks = <&ccu CLK_BUS_OTG>;
>> +			resets = <&ccu RST_BUS_OTG>;
>> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "mc";
>> +			phys = <&usbphy 0>;
>> +			phy-names = "usb";
>> +			extcon = <&usbphy 0>;
>> +			dr_mode = "otg";
> 
> dr_mode should be set in the board .dts, so please remove that line
> from here.
Done, and updated the Perf1 DTS to reflect this
> For the records: I checked the MMIO base addresses, clock and reset
> names and the IRQs against the manual: they all match.
Thanks again!
- Cody
> Cheers,
> Andre
> 
>> +			status = "disabled";
>> +		};
>> +

Re: [PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

[Cody Eksal]

On 2024/10/25 10:29 pm, Chen-Yu Tsai wrote:
> On Fri, Oct 25, 2024 at 1:09 AM Cody Eksal <masterr3c0rd@epochal.quest> 
> wrote:
>> 
>> From: Yangtao Li <frank@allwinnertech.com>
>> 
>> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
> 
>             ^^^ Please update this.
I wasn't sure if I was supposed to update the commit messages; a few 
others have grammar errors as well. I'll fix those alongside this one in 
V2.

Thanks!
- Cody
>> PHY device, let's add nodes on dts.
>> 
>> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 
>> +++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index adb11b26045f..0aee1b578661 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi

Re: [PATCH 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Cody Eksal]

On 2024/10/27 6:11 pm, Rob Herring (Arm) wrote:
> On Thu, 24 Oct 2024 14:05:21 -0300, Cody Eksal wrote:
>> The USB PHY found in the A100 is similar to that found in the A64,
>> although it requires some quirks to be enabled. Add a compatible for 
>> the
>> A100's variant.
>> 
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>>  .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml    | 1 
>> +
>>  1 file changed, 1 insertion(+)
>> 
> 
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
A quick note that I'm updating this patch in V2 to allow for falling 
back to the D1 compatible.

Thanks!
- Cody

Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table

[Cody Eksal]

On 2024/10/25 9:27 am, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:31 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> 
>> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>> 
>> Add an Operating Performance Points table for the CPU cores to
>> enable Dynamic Voltage & Frequency Scaling on the A100.
>> 
>> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>>  .../allwinner/sun50i-a100-allwinner-perf1.dts |  5 ++
>>  .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    | 90 
>> +++++++++++++++++++
>>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi |  8 ++
>>  3 files changed, 103 insertions(+)
>>  create mode 100644 
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> 
>> diff --git 
>> a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts 
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> index 29e9d24da8b6..99b1b2f7b92a 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> @@ -6,6 +6,7 @@
>>  /dts-v1/;
>> 
>>  #include "sun50i-a100.dtsi"
>> +#include "sun50i-a100-cpu-opp.dtsi"
>> 
>>  #include <dt-bindings/gpio/gpio.h>
>> 
>> @@ -67,6 +68,10 @@ &usb_otg {
>>  	status = "okay";
>>  };
>> 
>> +&cpu0 {
>> +	cpu-supply = <&reg_dcdc2>;
>> +};
>> +
>>  &pio {
>>  	vcc-pb-supply = <&reg_dcdc1>;
>>  	vcc-pc-supply = <&reg_eldo1>;
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi 
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> new file mode 100644
>> index 000000000000..eeb8d20f3fb4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
>> +// Copyright (c) 2020 ShuoSheng Huang 
>> <huangshuosheng@allwinnertech.com>
>> +
>> +/ {
>> +	cpu_opp_table: cpu-opp-table {
>> +		compatible = "allwinner,sun50i-a100-operating-points";
>> +		nvmem-cells = <&cpu_speed_grade>;
>> +		opp-shared;
>> +
>> +		opp@408000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <408000000>;
>> +
>> +			opp-microvolt-speed0 = <900000 900000 1200000>;
>> +			opp-microvolt-speed1 = <900000 900000 1200000>;
>> +			opp-microvolt-speed2 = <900000 900000 1200000>;
> 
> Is there actually an advantage when using the three cells version?
> I wonder if we should go with just the target voltage (the first cell
> here), as done for the H616.
It probably makes sense to follow precedent; I've updated V2 to make 
these single-cell.
> Apart from that it looks fine to me.
I did get a comment from Rob's bot that picked up some issues with the 
namings of these nodes; I've updated that as well.

Thanks!
- Cody
> Cheers,
> Andre.
> 
>> +		};
>> +
>> +		opp@600000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <600000000>;
>> +
>> +			opp-microvolt-speed0 = <900000 900000 1200000>;
>> +			opp-microvolt-speed1 = <900000 900000 1200000>;
>> +			opp-microvolt-speed2 = <900000 900000 1200000>;
>> +		};
>> +
>> +		opp@816000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <816000000>;
>> +
>> +			opp-microvolt-speed0 = <940000 940000 1200000>;
>> +			opp-microvolt-speed1 = <900000 900000 1200000>;
>> +			opp-microvolt-speed2 = <900000 900000 1200000>;
>> +		};
>> +
>> +		opp@1080000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <1080000000>;
>> +
>> +			opp-microvolt-speed0 = <1020000 1020000 1200000>;
>> +			opp-microvolt-speed1 = <980000 980000 1200000>;
>> +			opp-microvolt-speed2 = <950000 950000 1200000>;
>> +		};
>> +
>> +		opp@1200000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <1200000000>;
>> +
>> +			opp-microvolt-speed0 = <1100000 1100000 1200000>;
>> +			opp-microvolt-speed1 = <1020000 1020000 1200000>;
>> +			opp-microvolt-speed2 = <1000000 1000000 1200000>;
>> +		};
>> +
>> +		opp@1320000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <1320000000>;
>> +
>> +			opp-microvolt-speed0 = <1160000 1160000 1200000>;
>> +			opp-microvolt-speed1 = <1060000 1060000 1200000>;
>> +			opp-microvolt-speed2 = <1030000 1030000 1200000>;
>> +		};
>> +
>> +		opp@1464000000 {
>> +			clock-latency-ns = <244144>; /* 8 32k periods */
>> +			opp-hz = /bits/ 64 <1464000000>;
>> +
>> +			opp-microvolt-speed0 = <1180000 1180000 1200000>;
>> +			opp-microvolt-speed1 = <1180000 1180000 1200000>;
>> +			opp-microvolt-speed2 = <1130000 1130000 1200000>;
>> +		};
>> +	};
>> +};
>> +
>> +&cpu0 {
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu1 {
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu2 {
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu3 {
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index 6dca766ea222..747a0292ef98 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
>>  			device_type = "cpu";
>>  			reg = <0x0>;
>>  			enable-method = "psci";
>> +			clocks = <&ccu CLK_CPUX>;
>>  		};
>> 
>>  		cpu1: cpu@1 {
>> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
>>  			device_type = "cpu";
>>  			reg = <0x1>;
>>  			enable-method = "psci";
>> +			clocks = <&ccu CLK_CPUX>;
>>  		};
>> 
>>  		cpu2: cpu@2 {
>> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
>>  			device_type = "cpu";
>>  			reg = <0x2>;
>>  			enable-method = "psci";
>> +			clocks = <&ccu CLK_CPUX>;
>>  		};
>> 
>>  		cpu3: cpu@3 {
>> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
>>  			device_type = "cpu";
>>  			reg = <0x3>;
>>  			enable-method = "psci";
>> +			clocks = <&ccu CLK_CPUX>;
>>  		};
>>  	};
>> 
>> @@ -142,6 +146,10 @@ efuse@3006000 {
>>  			ths_calibration: calib@14 {
>>  				reg = <0x14 8>;
>>  			};
>> +
>> +			cpu_speed_grade: cpu-speed-grade@1c {
>> +				reg = <0x1c 0x2>;
>> +			};
>>  		};
>> 
>>  		watchdog@30090a0 {