Re: [PATCH v7 3/7] PCI: dwc: ep: Add bus_addr_base for outbound window

Manivannan Sadhasivam
2024-11-15T18:25:02Z

On Tue, Oct 29, 2024 at 12:36:36PM -0400, Frank Li wrote:
> Endpoint
> ┌───────────────────────────────────────────────┐
> │ pcie-ep@5f010000 │
> │ ┌────────────────┐│
> │ │ Endpoint ││
> │ │ PCIe ││
> │ │ Controller ││
> │ bus@5f000000 │ ││
> │ ┌──────────┐ │ ││
> │ │ │ Outbound Transfer ││
> │┌─────┐ │ Bus ┼─────►│ ATU ──────────┬┬─────►
> ││ │ │ Fabric │Bus │ ││PCI Addr
> ││ CPU ├───►│ │Addr │ ││0xA000_0000
> ││ │CPU │ │0x8000_0000 ││
> │└─────┘Addr└──────────┘ │ ││
> │ 0x7000_0000 └────────────────┘│
> └───────────────────────────────────────────────┘
>
> Add 'bus_addr_base' to configure the outbound window address for CPU write.

This doesn't make a lot of sense to readers. Use something like,

"Use 'ranges' property in DT to configure the iATU outbound window address."

> The bus fabric generally passes the same address to the PCIe EP controller,
> but some bus fabrics convert the address before sending it to the PCIe EP
> controller.
>
> Above diagram, CPU write data to outbound windows address 0x7000_0000,
> Bus fabric convert it to 0x8000_0000. ATU should use bus address
> 0x8000_0000 as input address and convert to PCI address 0xA000_0000.

s/convert/map

>
> Previously, 'cpu_addr_fixup()' was used to handle address conversion. Now,
> the device tree provides this information, preferring a common method.
>
> bus@5f000000 {
> compatible = "simple-bus";
> ranges = <0x80000000 0x0 0x70000000 0x10000000>;
>
> pcie-ep@5f010000 {
> reg = <0x80000000 0x10000000>;
> reg-names ="addr_space";
> ...
> };
> ...
> };
>
> 'ranges' in bus@5f000000 descript how address convert from CPU address
> to bus address.
>
> Use `of_property_read_reg()` to obtain the bus address and set it to the
> ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup().
>
> Add 'using_dtbus_info' to indicate device tree reflect correctly bus
> address translation in case break compatibility.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

One comment below. With that addressed,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

> ---
> Change from v6 to v7
> - none
>
> Change from v5 to v6
> - update diagram
> - Add comments for of_property_read_reg()
> - Remove unrelated 0x5f00_0000 in commit message
>
> Change from v3 to v4
> - change bus_addr_base to u64 to fix 32bit build error
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202410230328.BTHareG1-lkp@intel.com/
>
> Change from v2 to v3
> - Add using_dtbus_info to control if use device tree bus ranges
> information.
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 21 ++++++++++++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 43ba5c6738df1..a5b40c32aadf5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -9,6 +9,7 @@
> #include <linux/align.h>
> #include <linux/bitfield.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
>
> #include "pcie-designware.h"
> @@ -294,7 +295,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>
> atu.func_no = func_no;
> atu.type = PCIE_ATU_TYPE_MEM;
> - atu.cpu_addr = addr;
> + atu.cpu_addr = addr - ep->phys_base + ep->bus_addr_base;
> atu.pci_addr = pci_addr;
> atu.size = size;
> ret = dw_pcie_ep_outbound_atu(ep, &atu);
> @@ -861,6 +862,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> struct device *dev = pci->dev;
> struct platform_device *pdev = to_platform_device(dev);
> struct device_node *np = dev->of_node;
> + int index;
>
> INIT_LIST_HEAD(&ep->func_list);
>
> @@ -873,6 +875,23 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return -EINVAL;
>
> ep->phys_base = res->start;
> + ep->bus_addr_base = ep->phys_base;
> +
> + if (pci->using_dtbus_info) {
> + index = of_property_match_string(np, "reg-names", "addr_space");
> + if (index < 0)
> + return -EINVAL;
> +
> + /*
> + * Retrieve the local bus address information, which is sent to
> + * the PCIe Endpoint (EP) controller. If the parent bus
> + * 'ranges' in the device tree provide the correct address
> + * conversion information, set 'using_dtbus_info' to true. This
> + * allows 'cpu_addr_fixup()' to be eliminated.
> + */

/*
* Get the untranslated bus address from devicetree to use it as
* the iATU CPU address in dw_pcie_ep_map_addr().
*/

- Mani

> + of_property_read_reg(np, index, &ep->bus_addr_base, NULL);
> + }
> +
> ep->addr_size = resource_size(res);
>
> if (ep->ops->pre_init)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index f8067393ad35a..f10b533b04f77 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -410,6 +410,7 @@ struct dw_pcie_ep {
> struct list_head func_list;
> const struct dw_pcie_ep_ops *ops;
> phys_addr_t phys_base;
> + u64 bus_addr_base;
> size_t addr_size;
> size_t page_size;
> u8 bar_to_atu[PCI_STD_NUM_BARS];
>
> --
> 2.34.1
>

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