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Sat, 02 Nov 2024 10:24:50 -0700 (PDT) Received: from thinkpad ([220.158.156.209]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee452979e4sm4093637a12.9.2024.11.02.10.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2024 10:24:49 -0700 (PDT) Date: Sat, 2 Nov 2024 22:54:42 +0530 From: Manivannan Sadhasivam To: AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, fshao@chromium.org Subject: Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting link width Message-ID: <20241102172442.5dpmca6yeb2gmpjt@thinkpad> References: <20240918081307.51264-1-angelogioacchino.delregno@collabora.com> <20240918081307.51264-3-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240918081307.51264-3-angelogioacchino.delregno@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241102_102452_699106_B9B65329 X-CRM114-Status: GOOD ( 25.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 18, 2024 at 10:13:07AM +0200, AngeloGioacchino Del Regno wrote: > Add support for restricting the port's link width by specifying > the num-lanes devicetree property in the PCIe node. > > The setting is done in the GEN_SETTINGS register (in the driver > named as PCIE_SETTING_REG), where each set bit in [11:8] activates > a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2). > > Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index 8d4b045633da..8dd2e5135b01 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -32,6 +32,7 @@ > #define PCIE_BASE_CFG_SPEED GENMASK(15, 8) > > #define PCIE_SETTING_REG 0x80 > +#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8) > #define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12) > #define PCIE_PCI_IDS_1 0x9c > #define PCI_CLASS(class) (class << 8) > @@ -168,6 +169,7 @@ struct mtk_msi_set { > * @clks: PCIe clocks > * @num_clks: PCIe clocks count for this port > * @max_link_speed: Maximum link speed (PCIe Gen) for this port > + * @num_lanes: Number of PCIe lanes for this port > * @irq: PCIe controller interrupt number > * @saved_irq_state: IRQ enable state saved at suspend time > * @irq_lock: lock protecting IRQ register access > @@ -189,6 +191,7 @@ struct mtk_gen3_pcie { > struct clk_bulk_data *clks; > int num_clks; > u8 max_link_speed; > + u8 num_lanes; > > int irq; > u32 saved_irq_state; > @@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) > val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT, > GENMASK(pcie->max_link_speed - 2, 0)); > } > + if (pcie->num_lanes) { > + val &= ~PCIE_SETTING_LINK_WIDTH; > + > + /* Zero means one lane, each bit activates x2/x4/x8/x16 */ > + if (pcie->num_lanes > 1) > + val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH, > + GENMASK(pcie->num_lanes >> 1, 0)); > + }; > writel_relaxed(val, pcie->base + PCIE_SETTING_REG); > > /* Set Link Control 2 (LNKCTL2) speed restriction, if any */ > @@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) > struct device *dev = pcie->dev; > struct platform_device *pdev = to_platform_device(dev); > struct resource *regs; > + u32 num_lanes; > > regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); > if (!regs) > @@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) > return pcie->num_clks; > } > > + ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); > + if (ret == 0) { > + if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2)) > + dev_warn(dev, "Invalid num-lanes, using controller defaults\n"); > + else > + pcie->num_lanes = num_lanes; > + } > + > return 0; > } > > -- > 2.46.0 > > -- மணிவண்ணன் சதாசிவம்