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From: "Michał Pecio" <michal.pecio@gmail.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org,
	Linus Walleij <linus.walleij@linaro.org>
Subject: Re: cacheflush completely broken, suspecting PAN+LPAE
Date: Tue, 12 Nov 2024 11:45:56 +0100	[thread overview]
Message-ID: <20241112114556.11abb7c2@foxbook> (raw)
In-Reply-To: <ZzMsMFNSHLOKEeEW@shell.armlinux.org.uk>

Hi,

On Tue, 12 Nov 2024 10:21:36 +0000, Russell King (Oracle) wrote:
> On Mon, Nov 11, 2024 at 11:38:17PM +0100, Michał Pecio wrote:
> > Hi,
> > So I guess it looks like there is a problem with this feature,
> > perhaps a missing "permit user accesss" somewhere?  
> 
> That's exactly the reason - user access needs to be enabled before
> calling flush_icache_user_range() so that the cache operation
> instructions don't fault. The patch below should fix this.

Thanks, I will test it later this day.

By the way, do you know why it wasn't broken without LPAE? It looks
like either those specific coprocessor operations somehow bypass the
protection, or maybe all of PAN is a big, expensive no-op...

> Please ensure that you copy me with ARM related bugs in future.

OK, will do.

Regards,
Michal


  reply	other threads:[~2024-11-12 11:46 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11 22:38 cacheflush completely broken, suspecting PAN+LPAE Michał Pecio
2024-11-12  1:15 ` Linus Walleij
2024-11-12  6:41   ` Arnd Bergmann
2024-11-12  9:46     ` Michał Pecio
2024-11-12  9:32   ` Michał Pecio
2024-11-12 10:16     ` Michał Pecio
2024-11-12 10:21 ` Russell King (Oracle)
2024-11-12 10:45   ` Michał Pecio [this message]
2024-11-12 13:58     ` Linus Walleij
2024-11-12 17:10   ` Michał Pecio

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