linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Suraj Gupta <suraj.gupta2@amd.com>
To: <andrew+netdev@lunn.ch>, <davem@davemloft.net>,
	<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<michal.simek@amd.com>, <sean.anderson@linux.dev>,
	<radhey.shyam.pandey@amd.com>, <horms@kernel.org>
Cc: <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <git@amd.com>,
	<harini.katakam@amd.com>
Subject: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC
Date: Mon, 18 Nov 2024 13:48:21 +0530	[thread overview]
Message-ID: <20241118081822.19383-2-suraj.gupta2@amd.com> (raw)
In-Reply-To: <20241118081822.19383-1-suraj.gupta2@amd.com>

AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
max-speed is made a required property, and it breaks DT ABI but driver
implementation ensures backward compatibility and assumes 1G when this
property is absent.
Modify existing bindings description for 2.5G MAC.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 .../bindings/net/xlnx,axi-ethernet.yaml       | 44 +++++++++++++++++--
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
index fb02e579463c..69e84e2e2b63 100644
--- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
 description: |
   Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
   provides connectivity to an external ethernet PHY supporting different
-  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
   segments of memory for buffering TX and RX, as well as the capability of
   offloading TX/RX checksum calculation off the processor.
 
+  AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
+
   Management configuration is done through the AXI interface, while payload is
   sent and received through means of an AXI DMA controller. This driver
   includes the DMA driver code, so this driver is incompatible with AXI DMA
@@ -62,6 +64,7 @@ properties:
       - rgmii
       - sgmii
       - 1000base-x
+      - 2500base-x
 
   xlnx,phy-type:
     description:
@@ -118,9 +121,9 @@ properties:
     type: object
 
   pcs-handle:
-    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
-      modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
-      and "phy-handle" should point to an external PHY if exists.
+    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
+      2500base-x modes, where "pcs-handle" should be used to point to the
+      PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
     maxItems: 1
 
   dmas:
@@ -137,12 +140,17 @@ properties:
     minItems: 2
     maxItems: 32
 
+  max-speed:
+    description:
+      Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
+
 required:
   - compatible
   - interrupts
   - reg
   - xlnx,rxmem
   - phy-handle
+  - max-speed
 
 allOf:
   - $ref: /schemas/net/ethernet-controller.yaml#
@@ -164,6 +172,7 @@ examples:
         xlnx,rxmem = <0x800>;
         xlnx,txcsum = <0x2>;
         phy-handle = <&phy0>;
+        max-speed = <1000>;
 
         mdio {
             #address-cells = <1>;
@@ -188,6 +197,7 @@ examples:
         xlnx,txcsum = <0x2>;
         phy-handle = <&phy1>;
         axistream-connected = <&dma>;
+        max-speed = <1000>;
 
         mdio {
             #address-cells = <1>;
@@ -198,3 +208,29 @@ examples:
             };
         };
     };
+
+# AXI 2.5G MAC
+  - |
+    axi_ethernet_eth2: ethernet@a4000000 {
+        compatible = "xlnx,axi-ethernet-1.00.a";
+        interrupts = <0>;
+        clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
+        clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
+        phy-mode = "2500base-x";
+        reg = <0x40000000 0x40000>;
+        xlnx,rxcsum = <0x2>;
+        xlnx,rxmem = <0x800>;
+        xlnx,txcsum = <0x2>;
+        phy-handle = <&phy1>;
+        axistream-connected = <&dma>;
+        max-speed = <2500>;
+
+        mdio {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            phy2: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                reg = <1>;
+            };
+        };
+    };
-- 
2.25.1



  reply	other threads:[~2024-11-18  8:20 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-18  8:18 [PATCH net-next 0/2] Add support for AXI 2.5G ethernet Suraj Gupta
2024-11-18  8:18 ` Suraj Gupta [this message]
2024-11-18 15:36   ` [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC Sean Anderson
2024-11-18 15:54   ` Maxime Chevallier
2024-11-18 15:57     ` Sean Anderson
2024-11-19  1:38       ` Andrew Lunn
2024-11-19  9:40         ` Gupta, Suraj
2024-11-19 13:38           ` Andrew Lunn
2024-11-19  7:42   ` Krzysztof Kozlowski
2024-11-18  8:18 ` [PATCH net-next 2/2] net: axienet: Add support " Suraj Gupta
2024-11-18 14:42   ` Pandey, Radhey Shyam
2024-11-18 15:56   ` Russell King (Oracle)
2024-11-18 16:00     ` Sean Anderson
2024-11-18 16:08       ` Russell King (Oracle)
2024-11-19 10:28         ` Gupta, Suraj
2024-11-19 13:18           ` Russell King (Oracle)
2024-11-19 15:12             ` Russell King (Oracle)
2024-11-19  1:35       ` Andrew Lunn
2024-11-19 15:26         ` Sean Anderson
2024-11-19 15:49           ` Russell King (Oracle)
2024-11-19 16:42             ` Sean Anderson
2025-02-20 11:30             ` Gupta, Suraj
2025-02-20 11:44               ` Russell King (Oracle)
2025-02-20 12:17                 ` Gupta, Suraj
2025-02-20 14:35                   ` Andrew Lunn

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20241118081822.19383-2-suraj.gupta2@amd.com \
    --to=suraj.gupta2@amd.com \
    --cc=andrew+netdev@lunn.ch \
    --cc=davem@davemloft.net \
    --cc=edumazet@google.com \
    --cc=git@amd.com \
    --cc=harini.katakam@amd.com \
    --cc=horms@kernel.org \
    --cc=kuba@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=michal.simek@amd.com \
    --cc=netdev@vger.kernel.org \
    --cc=pabeni@redhat.com \
    --cc=radhey.shyam.pandey@amd.com \
    --cc=sean.anderson@linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).