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Sun, 24 Nov 2024 06:38:48 -0800 (PST) Received: from thinkpad ([36.255.17.192]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724de532d59sm4653362b3a.130.2024.11.24.06.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 06:38:47 -0800 (PST) Date: Sun, 24 Nov 2024 20:08:39 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Conor Dooley Subject: Re: [PATCH v8 0/7] PCI: dwc: opitimaze RC Host/EP pci_fixup_addr() Message-ID: <20241124143839.hg2yj462h22rftqa@thinkpad> References: <20241119-pci_fixup_addr-v8-0-c4bfa5193288@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241119-pci_fixup_addr-v8-0-c4bfa5193288@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241124_063850_452998_F232D212 X-CRM114-Status: GOOD ( 28.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 19, 2024 at 02:44:18PM -0500, Frank Li wrote: > == RC side: > > ┌─────────┐ ┌────────────┐ > ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ > │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ > └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ > CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ > 0x7ff8_0000─┼───┘ │ │ │ │ │ │ > │ │ │ │ │ │ │ PCI Addr > 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► > │ │ │ │ │ 0 > 0x7000_0000─┼────────►├─────────┐ │ │ │ > └─────────┘ │ └──────► CfgSpace ─┼────────────► > BUS Fabric │ │ │ 0 > │ │ │ > └──────────► MemSpace ─┼────────────► > IA: 0x8000_0000 │ │ 0x8000_0000 > └────────────┘ > > Current dwc implimemnt, pci_fixup_addr() call back is needed when bus > fabric convert cpu address before send to PCIe controller. > > bus@5f000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > pcie@5f010000 { > compatible = "fsl,imx8q-pcie"; > reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; > reg-names = "dbi", "config"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > bus-range = <0x00 0xff>; > ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, > <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; > ... > }; > }; > > Device tree already can descript all address translate. Some hardware > driver implement fixup function by mask some bits of cpu address. Last > pci-imx6.c are little bit better by fetch memory resource's offset to do > fixup. > > static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > { > ... > entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > return cpu_addr - entry->offset; > } > > But it is not good by using IORESOURCE_MEM to fix up io/cfg address map > although address translate is the same as IORESOURCE_MEM. > > This patches to fetch untranslate range information for PCIe controller > (pcie@5f010000: ranges). So current config ATU without cpu_fixup_addr(). > > == EP side: > > Endpoint > ┌───────────────────────────────────────────────┐ > │ pcie-ep@5f010000 │ > │ ┌────────────────┐│ > │ │ Endpoint ││ > │ │ PCIe ││ > │ │ Controller ││ > │ bus@5f000000 │ ││ > │ ┌──────────┐ │ ││ > │ │ │ Outbound Transfer ││ > │┌─────┐ │ Bus ┼─────►│ ATU ──────────┬┬─────► > ││ │ │ Fabric │Bus │ ││PCI Addr > ││ CPU ├───►│ │Addr │ ││0xA000_0000 > ││ │CPU │ │0x8000_0000 ││ > │└─────┘Addr└──────────┘ │ ││ > │ 0x7000_0000 └────────────────┘│ > └───────────────────────────────────────────────┘ > > bus@5f000000 { > compatible = "simple-bus"; > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > pcie-ep@5f010000 { > reg = <0x5f010000 0x00010000>, > <0x80000000 0x10000000>; > reg-names = "dbi", "addr_space"; > ... ^^^^ > }; > ... > }; > > Add `bus_addr_base` to configure the outbound window address for CPU write. > The BUS fabric generally passes the same address to the PCIe EP controller, > but some BUS fabrics convert the address before sending it to the PCIe EP > controller. > > Above diagram, CPU write data to outbound windows address 0x7000_0000, > Bus fabric convert it to 0x8000_0000. ATU should use BUS address > 0x8000_0000 as input address and convert to PCI address 0xA000_0000. > > Previously, `cpu_addr_fixup()` was used to handle address conversion. Now, > the device tree provides this information. > > The both pave the road to eliminate ugle cpu_fixup_addr() callback function. > Series looks good to me. Thanks a lot for your persistence! But it missed 6.13 cycle. So let's get it merged early once 6.13-rc1 is out. - Mani > Signed-off-by: Frank Li > --- > Changes in v8: > - Add mani's review tages > - use rename use_dt_ranges to use_parent_dt_ranges > - Add dev_warn_once to reminder to fix their dt file and remove > cpu_fixup_addr() callback. > - rename dw_pcie_get_untranslate_addr() to dw_pcie_get_parent_addr() > - Link to v7: https://lore.kernel.org/r/20241029-pci_fixup_addr-v7-0-8310dc24fb7c@nxp.com > > Changes in v7: > - fix > | Reported-by: kernel test robot > | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ > - Link to v6: https://lore.kernel.org/r/20241028-pci_fixup_addr-v6-0-ebebcd8fd4ff@nxp.com > > Changes in v6: > - merge RC and EP to one thread! > - Link to v5: https://lore.kernel.org/r/20241015-pci_fixup_addr-v5-0-ced556c85270@nxp.com > > Changes in v5: > - update address order in diagram patches. > - remove confused 0x5f00_0000 range > - update patch1's commit message. > - Link to v4: https://lore.kernel.org/r/20241008-pci_fixup_addr-v4-0-25e5200657bc@nxp.com > > Changes in v4: > - Improve commit message by add driver source code path. > - Link to v3: https://lore.kernel.org/r/20240930-pci_fixup_addr-v3-0-80ee70352fc7@nxp.com > > Changes in v3: > - see each patch > - Link to v2: https://lore.kernel.org/r/20240926-pci_fixup_addr-v2-0-e4524541edf4@nxp.com > > Changes in v2: > - see each patch > - Link to v1: https://lore.kernel.org/r/20240924-pci_fixup_addr-v1-0-57d14a91ec4f@nxp.com > > --- > Frank Li (7): > of: address: Add parent_bus_addr to struct of_pci_range > PCI: dwc: Use devicetree 'ranges' property to get rid of cpu_addr_fixup() callback > PCI: dwc: ep: Add bus_addr_base for outbound window > PCI: imx6: Remove cpu_addr_fixup() > dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep > PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() > PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support > > .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 38 ++++++++++++++- > drivers/of/address.c | 2 + > drivers/pci/controller/dwc/pci-imx6.c | 46 +++++++++-------- > drivers/pci/controller/dwc/pcie-designware-ep.c | 18 ++++++- > drivers/pci/controller/dwc/pcie-designware-host.c | 57 +++++++++++++++++++++- > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++ > drivers/pci/controller/dwc/pcie-designware.h | 8 +++ > include/linux/of_address.h | 1 + > 8 files changed, 155 insertions(+), 24 deletions(-) > --- > base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc > change-id: 20240924-pci_fixup_addr-a8568f9bbb34 > > Best regards, > --- > Frank Li > -- மணிவண்ணன் சதாசிவம்