From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46D53D6ACE4 for ; Wed, 27 Nov 2024 14:51:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ay4xBIuQ2fbyiN1pWrAhVvNJGGwduRJ8wyqtCi0OE1M=; b=oh0ARVT6e1o3zXMbeezLXON/99 s9uLjXNWE3CGFmRq23AFsSFo8/wPQQnryT/E2ME50H0WGwxuQpZychZYVfIpFsPdxI0ZalDwjzCkx KycLIzZca6gJpHI3yYXMKei3lxZe5NyNE1AUcmkfpDtRSh0qAuWFz24bYyHBU4uA2XGcmuGKGOiqS OZJE5N5UXA2Rq5P7PDRv+a4XRq7vRzrn2ivfsPtuGUsXGOjL1YzIoEU/APjT27+DaBYaM5dUcyCyO D43lF9rHp6URV8peJq52s4J+CuG++yAEBA0p5Qd+jDsky5fDR+Ku6IDEQkuPIp2kye6xLiHwWYogz TXPevsmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tGJNz-0000000DPm2-1KEG; Wed, 27 Nov 2024 14:51:23 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tGJMy-0000000DPby-3Jwg for linux-arm-kernel@lists.infradead.org; Wed, 27 Nov 2024 14:50:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 11B63A438CE; Wed, 27 Nov 2024 14:48:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 605F3C4CECC; Wed, 27 Nov 2024 14:50:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732719019; bh=U2ecL/KEEP79Jt7wprQzaK3Tla/TiL0FGSn6os/og+Y=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=X+KtNtRMvjSlNWfdV06UDwOYFuqvopZwRoBM/jIUmaqaSKpf52pvM5vDZyzy+hybL PuCerNneQGz29SjTYigCYcZ24ofVthHPnJAa7oSNFJMBHyTkr8H7ifieAund5XEYlL ONjQIjvW97MQNc72Xw5ogC568FuZS+pgjCNsJbpE0sR/y05Sd4ubcqCd1OnZ8ggKb4 aCRi0VV21Tc76qzMyaXVBF7H3DNTDdQ1r/OlGIT6MQfWJRp3tMlHEa/6SRweHcioCW BXg68Ai7dXus9d5tOuWPJFoZi6sLZ+OwaeYi9D1vdIzc/dTId1CwvbEbWcYuFWau5a Pd0+lB8LvUTsA== Date: Wed, 27 Nov 2024 08:50:17 -0600 From: Rob Herring To: Christian Bruel Cc: lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, p.zabel@pengutronix.de, cassel@kernel.org, quic_schintav@quicinc.com, fabrice.gasnier@foss.st.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings Message-ID: <20241127145017.GA3473844-robh@kernel.org> References: <20241126155119.1574564-1-christian.bruel@foss.st.com> <20241126155119.1574564-2-christian.bruel@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241126155119.1574564-2-christian.bruel@foss.st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241127_065020_965882_52588F24 X-CRM114-Status: GOOD ( 21.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 26, 2024 at 04:51:15PM +0100, Christian Bruel wrote: > Document the bindings for STM32MP25 PCIe Controller configured in > root complex mode. > > Supports 4 legacy interrupts and MSI interrupts from the ARM > GICv2m controller. > > STM32 PCIe may be in a power domain which is the case for the STM32MP25 > based boards. > > Supports wake# from wake-gpios > > Signed-off-by: Christian Bruel > --- > .../bindings/pci/st,stm32-pcie-common.yaml | 45 +++++++++ > .../bindings/pci/st,stm32-pcie-host.yaml | 99 +++++++++++++++++++ > 2 files changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml > create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml > > diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml > new file mode 100644 > index 000000000000..479c03134da3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32MP25 PCIe RC/EP controller > + > +maintainers: > + - Christian Bruel > + > +description: > + STM32MP25 PCIe RC/EP common properties > + > +properties: > + clocks: > + maxItems: 1 > + description: PCIe system clock > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy > + > + power-domains: > + maxItems: 1 > + > + access-controllers: > + maxItems: 1 > + > + reset-gpios: > + description: GPIO controlled connection to PERST# signal > + maxItems: 1 > + > +required: > + - clocks > + - resets > + - phys > + - phy-names > + > +additionalProperties: true > diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml > new file mode 100644 > index 000000000000..18083cc69024 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml > @@ -0,0 +1,99 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32MP25 PCIe root complex driver > + > +maintainers: > + - Christian Bruel > + > +description: > + PCIe root complex controller based on the Synopsys DesignWare PCIe core. > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# > + > +select: You don't need select. > + properties: > + compatible: > + const: st,stm32mp25-pcie-rc > + required: > + - compatible > + > +properties: > + compatible: > + const: st,stm32mp25-pcie-rc > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers. > + - description: PCIe configuration registers. > + > + reg-names: > + items: > + - const: dbi > + - const: config > + > + num-lanes: > + const: 1 Not required, so what's the default? If it can only ever be 1, then why do you need the property? > + > + msi-parent: > + maxItems: 1 > + > + wake-gpios: > + description: GPIO controlled connection to WAKE# input signal > + maxItems: 1 > + > + wakeup-source: true > + > +dependentRequired: > + wakeup-source: [ wake-gpios ] > + > +required: > + - interrupt-map > + - interrupt-map-mask > + - ranges > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + pcie@48400000 { > + compatible = "st,stm32mp25-pcie-rc"; > + device_type = "pci"; > + num-lanes = <1>; > + reg = <0x48400000 0x400000>, > + <0x10000000 0x10000>; > + reg-names = "dbi", "config"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>, > + <0x02000000 0 0x10020000 0x10020000 0 0x7fe0000>, > + <0x42000000 0 0x18000000 0x18000000 0 0x8000000>; > + clocks = <&rcc CK_BUS_PCIE>; > + phys = <&combophy PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + resets = <&rcc PCIE_R>; > + msi-parent = <&v2m0>; > + wakeup-source; > + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; > + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; > + access-controllers = <&rifsc 68>; > + power-domains = <&CLUSTER_PD>; > + }; > + > -- > 2.34.1 >