From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Bjorn Andersson <andersson@kernel.org>,
Christoffer Dall <christoffer.dall@arm.com>
Subject: [PATCH 09/11] KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits
Date: Mon, 2 Dec 2024 17:21:32 +0000 [thread overview]
Message-ID: <20241202172134.384923-10-maz@kernel.org> (raw)
In-Reply-To: <20241202172134.384923-1-maz@kernel.org>
Allow a guest hypervisor to trap accesses to CNT{P,V}CT_EL02 by
propagating these trap bits to the host trap configuration.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/arch_timer.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index 2c4499dd63732..f4607c4f68d2e 100644
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -822,6 +822,10 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map)
* Apply the enable bits that the guest hypervisor has requested for
* its own guest. We can only add traps that wouldn't have been set
* above.
+ * Implementation choices: we do not support NV when E2H=0 in the
+ * guest, and we don't support configuration where E2H is writable
+ * by the guest (either FEAT_VHE or FEAT_E2H0 is implemented, but
+ * not both). This simplifies the handling of the EL1NV* bits.
*/
if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
@@ -832,6 +836,9 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map)
tpt |= !(val & (CNTHCTL_EL1PCEN << 10));
tpc |= !(val & (CNTHCTL_EL1PCTEN << 10));
+
+ tpt02 |= (val & CNTHCTL_EL1NVPCT);
+ tvt02 |= (val & CNTHCTL_EL1NVVCT);
}
/*
--
2.39.2
next prev parent reply other threads:[~2024-12-02 17:33 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-02 17:21 [PATCH 00/11] KVM: arm64: Add NV timer support Marc Zyngier
2024-12-02 17:21 ` [PATCH 01/11] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2024-12-02 17:21 ` [PATCH 02/11] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2024-12-05 0:26 ` Oliver Upton
2024-12-02 17:21 ` [PATCH 03/11] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2024-12-02 17:21 ` [PATCH 04/11] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2024-12-02 17:21 ` [PATCH 05/11] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in use Marc Zyngier
2024-12-02 17:21 ` [PATCH 06/11] KVM: arm64: nv: Acceletate EL0 counter accesses from hypervisor context Marc Zyngier
2024-12-05 0:37 ` Oliver Upton
2024-12-05 11:03 ` Marc Zyngier
2024-12-05 17:07 ` Oliver Upton
2024-12-05 12:07 ` Joey Gouly
2024-12-05 13:31 ` Marc Zyngier
2024-12-02 17:21 ` [PATCH 07/11] KVM: arm64: Handle counter access early in non-HYP context Marc Zyngier
2024-12-02 17:21 ` [PATCH 08/11] KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT} Marc Zyngier
2024-12-02 17:21 ` Marc Zyngier [this message]
2024-12-02 17:21 ` [PATCH 10/11] KVM: arm64: nv: Sanitise CNTHCTL_EL2 Marc Zyngier
2024-12-02 17:21 ` [PATCH 11/11] KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity Marc Zyngier
2024-12-05 0:40 ` [PATCH 00/11] KVM: arm64: Add NV timer support Oliver Upton
2024-12-09 14:24 ` Chase Conklin
2024-12-09 15:15 ` Marc Zyngier
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